drm/i915/display: Use fixed_rr timings in modeset sequence

During modeset enable sequence, program the fixed timings, and turn on the
VRR Timing Generator (VRR TG) for platforms that always use VRR TG.

For this intel_vrr_set_transcoder now always programs fixed timings.
Later if vrr timings are required, vrr_enable() will switch
to the real VRR timings.

For platforms that will always use VRR TG, the VRR_CTL Enable bit is set
and reset in the transcoder enable/disable path.

v2: Update intel_vrr_set_transcoder_timings for fixed_rr.
v3: Update intel_set_transcoder_timings_lrr for fixed_rr. (Ville)
v4: Have separate functions to enable/disable VRR CTL
v5:
-For platforms that do not always have VRRTG on, do write bits other
than enable bit and also use write the TRANS_VRR_PUSH register. (Ville)
-Avoid writing trans_ctl_vrr if !vrr_possible().
v6:
-Disable VRR just before intel_ddi_disable_transcoder_func(). (Ville)
-Correct the sequence of configuring PUSH and VRR Enable/Disable. (Ville)
v7: Reset trans_vrr_ctl to 0 unconditionally in
intel_vrr_transcoder_disable(). (Ville)
v8: Reset trans_vrr_ctl if flipline is not set. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/20250324133248.4071909-9-ankit.k.nautiyal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f38c998935b977176a093efe0ab3e3f2163edf0b..44f4465c27e21c2ab2f288189c685df96f981076 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -78,6 +78,7 @@
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
+#include "intel_vrr.h"
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 
@@ -3249,6 +3250,8 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
                drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
        }
 
+       intel_vrr_transcoder_disable(old_crtc_state);
+
        intel_ddi_disable_transcoder_func(old_crtc_state);
 
        for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
@@ -3522,6 +3525,8 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 
        intel_ddi_enable_transcoder_func(encoder, crtc_state);
 
+       intel_vrr_transcoder_enable(crtc_state);
+
        /* Enable/Disable DP2.0 SDP split config before transcoder */
        intel_audio_sdp_split_update(crtc_state);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index bd47cf127b4c0b9fc7d0240fbbb19253ea70ab7d..d2988b9a6e7bd55d2ea4d34230c4d017e1f4cc93 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1065,6 +1065,8 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
        drm_dp_remove_payload_part2(&intel_dp->mst.mgr, new_mst_state,
                                    old_payload, new_payload);
 
+       intel_vrr_transcoder_disable(old_crtc_state);
+
        intel_ddi_disable_transcoder_func(old_crtc_state);
 
        for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
@@ -1326,6 +1328,8 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 
        intel_ddi_enable_transcoder_func(encoder, pipe_config);
 
+       intel_vrr_transcoder_enable(pipe_config);
+
        intel_ddi_clear_act_sent(encoder, pipe_config);
 
        intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0,

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8a0d27666ea721208c7fe04b2527cff780a48525..96b6b730bea42bacc4601be6e6e4b425ecd0b740 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -479,14 +479,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
                               lower_32_bits(crtc_state->cmrr.cmrr_n));
        }
 
-       intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
-                      crtc_state->vrr.vmin - 1);
-       intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
-                      crtc_state->vrr.vmax - 1);
-       intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-                      trans_vrr_ctl(crtc_state));
-       intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
-                      crtc_state->vrr.flipline - 1);
+       intel_vrr_set_fixed_rr_timings(crtc_state);
 
        if (HAS_AS_SDP(display))
                intel_de_write(display,
@@ -620,6 +613,48 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
        intel_vrr_set_fixed_rr_timings(old_crtc_state);
 }
 
+void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
+{
+       struct intel_display *display = to_intel_display(crtc_state);
+       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+       if (!HAS_VRR(display))
+               return;
+
+       if (!intel_vrr_possible(crtc_state))
+               return;
+
+       if (!intel_vrr_always_use_vrr_tg(display)) {
+               intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
+                              trans_vrr_ctl(crtc_state));
+               return;
+       }
+
+       intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
+                      TRANS_PUSH_EN);
+
+       intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
+                      VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+}
+
+void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
+{
+       struct intel_display *display = to_intel_display(crtc_state);
+       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+       if (!HAS_VRR(display))
+               return;
+
+       if (!intel_vrr_possible(crtc_state))
+               return;
+
+       intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0);
+
+       intel_de_wait_for_clear(display, TRANS_VRR_STATUS(display, cpu_transcoder),
+                               VRR_STATUS_VRR_EN_LIVE, 1000);
+       intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
+}
+
 bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
 {
        return crtc_state->vrr.flipline &&

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 65d2b0eead51fdb5266b9a6605e9822136eb7e51..859f1dc8a6d7feff6028654217db56e190b1969b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -36,5 +36,7 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
+void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
+void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VRR_H__ */