Define VECTOR_STORE_FLAG_VALUE

gcc/ChangeLog:

	* config/i386/i386.h (VECTOR_STORE_FLAG_VALUE): New macro.

gcc/testsuite/ChangeLog:
	* gcc.dg/rtl/x86_64/vector_eq.c: New test.

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 751c250ddb311490e1a5c9e13c8302653697fe1e..58e6f2826bf637fc009fb6cca1b7ea872fe37b66 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -899,7 +899,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
    and give entire struct the alignment of an int.  */
 /* Required on the 386 since it doesn't have bit-field insns.  */
 #define PCC_BITFIELD_TYPE_MATTERS 1
-\f
+
+#define VECTOR_STORE_FLAG_VALUE(MODE) \
+  (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT ? constm1_rtx : NULL_RTX)
+
 /* Standard register usage.  */
 
 /* This processor has special stack-like registers.  See reg-stack.cc

diff --git a/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
new file mode 100644 (file)
index 0000000..6704c28
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && lp64 } } } */
+/* { dg-additional-options "-O2 -march=x86-64-v3" } */
+
+typedef int v4si __attribute__((vector_size(16)));
+
+v4si __RTL (startwith ("vregs")) foo (void)
+{
+(function "foo"
+  (insn-chain
+    (block 2
+      (edge-from entry (flags "FALLTHRU"))
+      (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
+      (cnote 2 NOTE_INSN_FUNCTION_BEG)
+      (cinsn 3 (set (reg:V4SI <0>) (const_vector:V4SI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])))
+      (cinsn 5 (set (reg:V4SI <2>)
+                   (eq:V4SI (reg:V4SI <0>) (reg:V4SI <1>))))
+      (cinsn 6 (set (reg:V4SI <3>) (reg:V4SI <2>)))
+      (cinsn 7 (set (reg:V4SI xmm0) (reg:V4SI <3>)))
+      (edge-to exit (flags "FALLTHRU"))
+    )
+  )
+ (crtl (return_rtx (reg/i:V4SI xmm0)))
+)
+}
+
+/* { dg-final { scan-assembler-not "vpxor" } } */