arm64: dts: rockchip: add vicap node to rk356x

Add the device tree node for the RK356x Video Capture (VICAP) unit.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
Link: https://patch.msgid.link/20240220-rk3568-vicap-v15-13-8f4915ee365d@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index c005135089d465d30a3bc8d59d37c532e3d4fdd3..8893b7b6cc9ff3fe337786103be2854230f6fa9a 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -619,6 +619,50 @@
                #iommu-cells = <0>;
        };
 
+       vicap: video-capture@fdfe0000 {
+               compatible = "rockchip,rk3568-vicap";
+               reg = <0x0 0xfdfe0000 0x0 0x200>;
+               interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+               assigned-clocks = <&cru DCLK_VICAP>;
+               assigned-clock-rates = <300000000>;
+               clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
+                        <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
+               clock-names = "aclk", "hclk", "dclk", "iclk";
+               iommus = <&vicap_mmu>;
+               power-domains = <&power RK3568_PD_VI>;
+               resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
+                        <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
+                        <&cru SRST_I_VICAP>;
+               reset-names = "arst", "hrst", "drst", "prst", "irst";
+               rockchip,grf = <&grf>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       vicap_dvp: port@0 {
+                               reg = <0>;
+                       };
+
+                       vicap_mipi: port@1 {
+                               reg = <1>;
+                       };
+               };
+       };
+
+       vicap_mmu: iommu@fdfe0800 {
+               compatible = "rockchip,rk3568-iommu";
+               reg = <0x0 0xfdfe0800 0x0 0x100>;
+               interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
+               clock-names = "aclk", "iface";
+               #iommu-cells = <0>;
+               power-domains = <&power RK3568_PD_VI>;
+               rockchip,disable-mmu-reset;
+               status = "disabled";
+       };
+
        sdmmc2: mmc@fe000000 {
                compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xfe000000 0x0 0x4000>;