clk: renesas: r9a09g077: Add TSU module clock

The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a TSU
peripheral which is controlled by a module clock.

The TSU module clock is enabled in register MSTPCRD (0x30c), at bit 7,
resulting in a (0x30c - 0x300) / 4 * 100 + 7 = 307 index.

Add it to the list of module clocks.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023081925.2412325-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index 4ec6c4ddc5f5fd1a84cca3e9a720de6ff831a625..8b7e84a4c307f7a20f0e088541bed329b853f02c 100644 (file)
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -191,6 +191,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
        DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
        DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
        DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),
+       DEF_MOD("tsu", 307, R9A09G077_CLK_PCLKL),
        DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),
        DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),
        DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),