]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports
authorJosua Mayer <josua@solid-run.com>
Thu, 11 Sep 2025 18:28:06 +0000 (20:28 +0200)
committerGregory CLEMENT <gregory.clement@bootlin.com>
Fri, 12 Sep 2025 12:54:38 +0000 (14:54 +0200)
The mvebu-comphy driver does not currently know how to pass correct
lane-count to ATF while configuring the serdes lanes.

This causes the system to hard reset during reconfiguration, if a pci
card is present and has established a link during bootloader.

Remove the comphy handles from the respective pci nodes to avoid runtime
reconfiguration, relying solely on bootloader configuration - while
avoiding the hard reset.

When bootloader has configured the lanes correctly, the pci ports are
functional under Linux.

This issue may be addressed in the comphy driver at a future point.

Fixes: e9ff907f4076 ("arm64: dts: add description for solidrun cn9132 cex7 module and clearfog board")
Cc: stable@vger.kernel.org
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
arch/arm64/boot/dts/marvell/cn9132-clearfog.dts

index 115c55d73786e2b9265e1caa4c62ee26f498fb41..6f237d3542b9102695f8a48457f43340da994a2c 100644 (file)
 /* SRDS #0,#1,#2,#3 - PCIe */
 &cp0_pcie0 {
        num-lanes = <4>;
-       phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
+       /*
+        * The mvebu-comphy driver does not currently know how to pass correct
+        * lane-count to ATF while configuring the serdes lanes.
+        * Rely on bootloader configuration only.
+        *
+        * phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
+        */
        status = "okay";
 };
 
 /* SRDS #0,#1 - PCIe */
 &cp1_pcie0 {
        num-lanes = <2>;
-       phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
+       /*
+        * The mvebu-comphy driver does not currently know how to pass correct
+        * lane-count to ATF while configuring the serdes lanes.
+        * Rely on bootloader configuration only.
+        *
+        * phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
+        */
        status = "okay";
 };