arm: zynq: Remove fclk-enable property for cse-nor target

Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
index ba6f9a1a79e3cd1a5c6ea77678893e24d7cb88ff..edc8f59f6cea904f9d1529146f76c1289870c7ac 100644 (file)
--- a/arch/arm/dts/zynq-cse-nor.dts
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -56,7 +56,6 @@
                        clkc: clkc@100 {
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
-                               fclk-enable = <0xf>;
                                clock-output-names = "armpll", "ddrpll",
                                                "iopll", "cpu_6or4x",
                                                "cpu_3or2x", "cpu_2x", "cpu_1x",