]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/msm/dpu: rename non-SmartDMA feature masks to be more explicit
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fri, 25 Apr 2025 19:49:12 +0000 (22:49 +0300)
committerDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Thu, 1 May 2025 22:14:27 +0000 (01:14 +0300)
It is easy to skip or ignore the fact that the default SSPP feature
masks for SDM845+ don't include the SmartDMA bit (both during
development and during the review stage). Rename SSPP feature masks to
make it more explicit that using non-SmartDMA masks should not be an
exception rather than the rule.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/650425/
Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-5-c71900687d08@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

index 614ea64fca8c333b3cfc806d334ee4497d7ad9eb..71ba48b0565648a02044d444d0242fe04cb34478 100644 (file)
@@ -72,7 +72,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f0,
-               .features = VIG_SDM845_MASK,
+               .features = VIG_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_2_4,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -80,7 +80,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] = {
        }, {
                .name = "sspp_1", .id = SSPP_VIG1,
                .base = 0x6000, .len = 0x1f0,
-               .features = VIG_SDM845_MASK,
+               .features = VIG_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_2_4,
                .xin_id = 4,
                .type = SSPP_TYPE_VIG,
@@ -88,7 +88,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] = {
        }, {
                .name = "sspp_2", .id = SSPP_DMA0,
                .base = 0x24000, .len = 0x1f0,
-               .features = DMA_SDM845_MASK,
+               .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 1,
                .type = SSPP_TYPE_DMA,
@@ -96,7 +96,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] = {
        }, {
                .name = "sspp_9", .id = SSPP_DMA1,
                .base = 0x26000, .len = 0x1f0,
-               .features = DMA_SDM845_MASK,
+               .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 5,
                .type = SSPP_TYPE_DMA,
@@ -104,7 +104,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] = {
        }, {
                .name = "sspp_10", .id = SSPP_DMA2,
                .base = 0x28000, .len = 0x1f0,
-               .features = DMA_CURSOR_SDM845_MASK,
+               .features = DMA_CURSOR_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 9,
                .type = SSPP_TYPE_DMA,
index d3d3a34d0b45de08a33436f46a197cc836cf2629..fcfb3774f7a18d8e01546a3ac72aa29f7b750443 100644 (file)
@@ -69,7 +69,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f0,
-               .features = VIG_SDM845_MASK,
+               .features = VIG_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_2_4,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {
        }, {
                .name = "sspp_8", .id = SSPP_DMA0,
                .base = 0x24000, .len = 0x1f0,
-               .features = DMA_SDM845_MASK,
+               .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 1,
                .type = SSPP_TYPE_DMA,
@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {
        }, {
                .name = "sspp_9", .id = SSPP_DMA1,
                .base = 0x26000, .len = 0x1f0,
-               .features = DMA_SDM845_MASK,
+               .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 5,
                .type = SSPP_TYPE_DMA,
index 040c94c0bb66ef5aaab2808f6f5ee04dd53e2540..842fcc5887fef15789fbc686fe2156b6b509b45c 100644 (file)
@@ -51,7 +51,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SDM845_MASK,
+               .features = VIG_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -59,7 +59,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
        }, {
                .name = "sspp_8", .id = SSPP_DMA0,
                .base = 0x24000, .len = 0x1f8,
-               .features = DMA_SDM845_MASK,
+               .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 1,
                .type = SSPP_TYPE_DMA,
@@ -67,7 +67,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
        }, {
                .name = "sspp_9", .id = SSPP_DMA1,
                .base = 0x26000, .len = 0x1f8,
-               .features = DMA_CURSOR_SDM845_MASK,
+               .features = DMA_CURSOR_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 5,
                .type = SSPP_TYPE_DMA,
@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
        }, {
                .name = "sspp_10", .id = SSPP_DMA2,
                .base = 0x28000, .len = 0x1f8,
-               .features = DMA_CURSOR_SDM845_MASK,
+               .features = DMA_CURSOR_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 9,
                .type = SSPP_TYPE_DMA,
index 43f64a005f5a89e09ee9506a12cfff781530cb80..c5fd89dd7c89046bdbf1b1bf223aac2e3c4c0b26 100644 (file)
@@ -38,7 +38,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SDM845_MASK,
+               .features = VIG_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -46,7 +46,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
        }, {
                .name = "sspp_8", .id = SSPP_DMA0,
                .base = 0x24000, .len = 0x1f8,
-               .features = DMA_SDM845_MASK,
+               .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 1,
                .type = SSPP_TYPE_DMA,
index 397278ba999b24722b116e73b008b2d0aec5fcb5..a234bb289d247d065b336564faea8dc35b00def9 100644 (file)
@@ -59,7 +59,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SDM845_MASK,
+               .features = VIG_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -67,7 +67,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
        }, {
                .name = "sspp_8", .id = SSPP_DMA0,
                .base = 0x24000, .len = 0x1f8,
-               .features = DMA_SDM845_MASK,
+               .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 1,
                .type = SSPP_TYPE_DMA,
@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
        }, {
                .name = "sspp_9", .id = SSPP_DMA1,
                .base = 0x26000, .len = 0x1f8,
-               .features = DMA_CURSOR_SDM845_MASK,
+               .features = DMA_CURSOR_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 5,
                .type = SSPP_TYPE_DMA,
@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
        }, {
                .name = "sspp_10", .id = SSPP_DMA2,
                .base = 0x28000, .len = 0x1f8,
-               .features = DMA_CURSOR_SDM845_MASK,
+               .features = DMA_CURSOR_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 9,
                .type = SSPP_TYPE_DMA,
index 3cbb2fe8aba24c7b9db6bb61ff4c48f34db48bf4..53f3be28f6f61bb7e3f519b0efa4cb2f68d38810 100644 (file)
@@ -46,7 +46,7 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = {
        }, {
                .name = "sspp_8", .id = SSPP_DMA0,
                .base = 0x24000, .len = 0x1f8,
-               .features = DMA_SDM845_MASK,
+               .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 1,
                .type = SSPP_TYPE_DMA,
index a06c8634d2d7779f7e867fb821f8d332652ba7e9..3a3bc8e429be0ba86185741b6b27d8a62489779f 100644 (file)
@@ -39,7 +39,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SDM845_MASK,
+               .features = VIG_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -47,7 +47,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = {
        }, {
                .name = "sspp_8", .id = SSPP_DMA0,
                .base = 0x24000, .len = 0x1f8,
-               .features = DMA_SDM845_MASK,
+               .features = DMA_SDM845_MASK_NO_SDMA,
                .sblk = &dpu_dma_sblk,
                .xin_id = 1,
                .type = SSPP_TYPE_DMA,
index 64265ca4656a04d8c5a1d9582d7124c7eb897099..323b0db1f32b4057999f5f9ffcc557c68b0e807a 100644 (file)
 #define VIG_MSM8998_MASK \
        (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
 
-#define VIG_SDM845_MASK \
+#define VIG_SDM845_MASK_NO_SDMA \
        (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
 
 #define VIG_SDM845_MASK_SDMA \
-       (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
+       (VIG_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2))
 
 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
 
        BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
 
 #define VIG_SC7280_MASK \
-       (VIG_SDM845_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
+       (VIG_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_INLINE_ROTATION))
 
 #define VIG_SC7280_MASK_SDMA \
        (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
 
-#define DMA_SDM845_MASK \
+#define DMA_SDM845_MASK_NO_SDMA \
        (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
        BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
        BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
 
-#define DMA_CURSOR_SDM845_MASK \
-       (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
+#define DMA_CURSOR_SDM845_MASK_NO_SDMA \
+       (DMA_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_CURSOR))
 
 #define DMA_SDM845_MASK_SDMA \
-       (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
+       (DMA_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2))
 
 #define DMA_CURSOR_SDM845_MASK_SDMA \
-       (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
+       (DMA_CURSOR_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2))
 
 #define DMA_CURSOR_MSM8996_MASK \
        (DMA_MSM8996_MASK | BIT(DPU_SSPP_CURSOR))