cxl/core/regs: Add rcd_pcie_cap initialization

Add rcd_pcie_cap and its initialization to cache the offset of cxl1.1
device link status information. By caching it, avoid the walking
memory map area to find the offset when output the register value.

Given that this solution involves port lookups via cxl_pci_find_port()
and multiple exit paths where that reference needs to be dropped,
introduce a new put_cxl_root() scope-based-free handler.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Kobayashi,Daisuke <kobayashi.da-06@fujitsu.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/20241002011549.408412-2-kobayashi.da-06@fujitsu.com
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 0c62b4069ba00a5380d456a516eb7968dc51062b..800466f96a68517f0c6930faa555b347cf0e156b 100644 (file)
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -89,6 +89,11 @@ resource_size_t __rcrb_to_component(struct device *dev,
                                    enum cxl_rcrb which);
 u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
 
+#define PCI_RCRB_CAP_LIST_ID_MASK      GENMASK(7, 0)
+#define PCI_RCRB_CAP_HDR_ID_MASK       GENMASK(7, 0)
+#define PCI_RCRB_CAP_HDR_NEXT_MASK     GENMASK(15, 8)
+#define PCI_CAP_EXP_SIZEOF             0x3c
+
 extern struct rw_semaphore cxl_dpa_rwsem;
 extern struct rw_semaphore cxl_region_rwsem;
 

diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index e1082e749c69e6a447ca21352f89ad719c3deab5..1c1c10c8bc7ae43acb758bd7429cc13abf8a40f1 100644 (file)
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -506,6 +506,62 @@ out:
        return offset;
 }
 
+static resource_size_t cxl_rcrb_to_linkcap(struct device *dev, struct cxl_dport *dport)
+{
+       resource_size_t rcrb = dport->rcrb.base;
+       void __iomem *addr;
+       u32 cap_hdr;
+       u16 offset;
+
+       if (!request_mem_region(rcrb, SZ_4K, "CXL RCRB"))
+               return CXL_RESOURCE_NONE;
+
+       addr = ioremap(rcrb, SZ_4K);
+       if (!addr) {
+               dev_err(dev, "Failed to map region %pr\n", addr);
+               release_mem_region(rcrb, SZ_4K);
+               return CXL_RESOURCE_NONE;
+       }
+
+       offset = FIELD_GET(PCI_RCRB_CAP_LIST_ID_MASK, readw(addr + PCI_CAPABILITY_LIST));
+       cap_hdr = readl(addr + offset);
+       while ((FIELD_GET(PCI_RCRB_CAP_HDR_ID_MASK, cap_hdr)) != PCI_CAP_ID_EXP) {
+               offset = FIELD_GET(PCI_RCRB_CAP_HDR_NEXT_MASK, cap_hdr);
+               if (offset == 0 || offset > SZ_4K) {
+                       offset = 0;
+                       break;
+               }
+               cap_hdr = readl(addr + offset);
+       }
+
+       iounmap(addr);
+       release_mem_region(rcrb, SZ_4K);
+       if (!offset)
+               return CXL_RESOURCE_NONE;
+
+       return offset;
+}
+
+int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport)
+{
+       void __iomem *dport_pcie_cap = NULL;
+       resource_size_t pos;
+       struct cxl_rcrb_info *ri;
+
+       ri = &dport->rcrb;
+       pos = cxl_rcrb_to_linkcap(&pdev->dev, dport);
+       if (pos == CXL_RESOURCE_NONE)
+               return -ENXIO;
+
+       dport_pcie_cap = devm_cxl_iomap_block(&pdev->dev,
+                                             ri->base + pos,
+                                             PCI_CAP_EXP_SIZEOF);
+       dport->regs.rcd_pcie_cap = dport_pcie_cap;
+
+       return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_dport_map_rcd_linkcap, CXL);
+
 resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri,
                                    enum cxl_rcrb which)
 {

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 0d8b810a51f04de299e88ee8b29136bff11ed93e..1cfe3dd42e2f3cdbc1e5d54d8f7df38e449ea79c 100644 (file)
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -235,6 +235,14 @@ struct cxl_regs {
        struct_group_tagged(cxl_rch_regs, rch_regs,
                void __iomem *dport_aer;
        );
+
+       /*
+        * RCD upstream port specific PCIe cap register
+        * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB
+        */
+       struct_group_tagged(cxl_rcd_regs, rcd_regs,
+               void __iomem *rcd_pcie_cap;
+       );
 };
 
 struct cxl_reg_map {
@@ -304,6 +312,7 @@ int cxl_setup_regs(struct cxl_register_map *map);
 struct cxl_dport;
 resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
                                           struct cxl_dport *dport);
+int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport);
 
 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
 #define CXL_TARGET_STRLEN 20

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 188412d45e0d266b19f7401a1cdc51ed6fb0ea0a..0a48d29a7df8405c5e46c05b05c344062c6bf67b 100644 (file)
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -475,9 +475,9 @@ static bool is_cxl_restricted(struct pci_dev *pdev)
 }
 
 static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
-                                 struct cxl_register_map *map)
+                                 struct cxl_register_map *map,
+                                 struct cxl_dport *dport)
 {
-       struct cxl_dport *dport;
        resource_size_t component_reg_phys;
 
        *map = (struct cxl_register_map) {
@@ -513,11 +513,24 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
         * is an RCH and try to extract the Component Registers from
         * an RCRB.
         */
-       if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev))
-               rc = cxl_rcrb_get_comp_regs(pdev, map);
-
-       if (rc)
+       if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) {
+               struct cxl_dport *dport;
+               struct cxl_port *port __free(put_cxl_port) =
+                       cxl_pci_find_port(pdev, &dport);
+               if (!port)
+                       return -EPROBE_DEFER;
+
+               rc = cxl_rcrb_get_comp_regs(pdev, map, dport);
+               if (rc)
+                       return rc;
+
+               rc = cxl_dport_map_rcd_linkcap(pdev, dport);
+               if (rc)
+                       return rc;
+
+       } else if (rc) {
                return rc;
+       }
 
        return cxl_setup_regs(map);
 }