]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
EDAC/{skx_common,i10nm}: Remove the AMAP register for determing DDR5
authorQiuxu Zhuo <qiuxu.zhuo@intel.com>
Thu, 29 Aug 2024 06:13:09 +0000 (14:13 +0800)
committerTony Luck <tony.luck@intel.com>
Tue, 3 Sep 2024 19:36:59 +0000 (12:36 -0700)
The configuration flag 'res_config->support_ddr5 = true' sufficiently
indicates DDR5 memory support for Sapphire Rapids and Granite Rapids.
Additionally, the i10nm_edac driver doesn't need to use the AMAP
register for setting the 'fine_grain_bank' of each DIMM. Therefore,
remove the AMAP register for determining DDR5.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/all/20240829061309.57738-1-qiuxu.zhuo@intel.com
drivers/edac/i10nm_base.c
drivers/edac/skx_common.c

index c5b99d575cc7a4f50314493b6da683b3bb7b3806..e2a954de913b429c38d3b829744cf868b25dc824 100644 (file)
        readl((m)->mbase + ((m)->hbm_mc ? 0xef8 :       \
        (res_cfg->type == GNR ? 0xaf8 : 0x20ef8)) +     \
        (i) * (m)->chan_mmio_sz)
-#define I10NM_GET_AMAP(m, i)           \
-       readl((m)->mbase + ((m)->hbm_mc ? 0x814 :       \
-       (res_cfg->type == GNR ? 0xc14 : 0x20814)) +     \
-       (i) * (m)->chan_mmio_sz)
 #define I10NM_GET_REG32(m, i, offset)  \
        readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
 #define I10NM_GET_REG64(m, i, offset)  \
@@ -971,7 +967,7 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
 {
        struct skx_pvt *pvt = mci->pvt_info;
        struct skx_imc *imc = pvt->imc;
-       u32 mtr, amap, mcddrtcfg = 0;
+       u32 mtr, mcddrtcfg = 0;
        struct dimm_info *dimm;
        int i, j, ndimms;
 
@@ -980,7 +976,6 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
                        continue;
 
                ndimms = 0;
-               amap = I10NM_GET_AMAP(imc, i);
 
                if (res_cfg->type != GNR)
                        mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
@@ -992,7 +987,7 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
                                 mtr, mcddrtcfg, imc->mc, i, j);
 
                        if (IS_DIMM_PRESENT(mtr))
-                               ndimms += skx_get_dimm_info(mtr, 0, amap, dimm,
+                               ndimms += skx_get_dimm_info(mtr, 0, 0, dimm,
                                                            imc, i, j, cfg);
                        else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
                                ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
index 7cd074401167127ad02bb83b2c7205fab74006a0..85713646957b3e22f07e4b6563ded9e068d32280 100644 (file)
@@ -363,7 +363,7 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
        if (imc->hbm_mc) {
                banks = 32;
                mtype = MEM_HBM2;
-       } else if (cfg->support_ddr5 && (amap & 0x8)) {
+       } else if (cfg->support_ddr5) {
                banks = 32;
                mtype = MEM_DDR5;
        } else {