pinctrl: amd: Don't access irq_data's hwirq member directly

There is an irqd_to_hwirq() intended to get the hwirq number. Switch
all use to it.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/20250821144942.2463014-1-superm1@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 127eeb0104d856ad37f017543212877408da6a4b..2dac5c71eb008f447976b49c520451a696feb519 100644 (file)
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -383,14 +383,15 @@ static void amd_gpio_irq_enable(struct irq_data *d)
        unsigned long flags;
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+       irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-       gpiochip_enable_irq(gc, d->hwirq);
+       gpiochip_enable_irq(gc, hwirq);
 
        raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-       pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+       pin_reg = readl(gpio_dev->base + hwirq * 4);
        pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
        pin_reg |= BIT(INTERRUPT_MASK_OFF);
-       writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+       writel(pin_reg, gpio_dev->base + hwirq * 4);
        raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 }
 
@@ -400,15 +401,16 @@ static void amd_gpio_irq_disable(struct irq_data *d)
        unsigned long flags;
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+       irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
        raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-       pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+       pin_reg = readl(gpio_dev->base + hwirq * 4);
        pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
        pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
-       writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+       writel(pin_reg, gpio_dev->base + hwirq * 4);
        raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
-       gpiochip_disable_irq(gc, d->hwirq);
+       gpiochip_disable_irq(gc, hwirq);
 }
 
 static void amd_gpio_irq_mask(struct irq_data *d)
@@ -417,11 +419,12 @@ static void amd_gpio_irq_mask(struct irq_data *d)
        unsigned long flags;
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+       irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
        raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-       pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+       pin_reg = readl(gpio_dev->base + hwirq * 4);
        pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
-       writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+       writel(pin_reg, gpio_dev->base + hwirq * 4);
        raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 }
 
@@ -431,11 +434,12 @@ static void amd_gpio_irq_unmask(struct irq_data *d)
        unsigned long flags;
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+       irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
        raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-       pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+       pin_reg = readl(gpio_dev->base + hwirq * 4);
        pin_reg |= BIT(INTERRUPT_MASK_OFF);
-       writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+       writel(pin_reg, gpio_dev->base + hwirq * 4);
        raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 }
 
@@ -446,20 +450,21 @@ static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
        u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
+       irq_hw_number_t hwirq = irqd_to_hwirq(d);
        int err;
 
        pm_pr_dbg("Setting wake for GPIO %lu to %s\n",
-                  d->hwirq, str_enable_disable(on));
+                  hwirq, str_enable_disable(on));
 
        raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-       pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+       pin_reg = readl(gpio_dev->base + hwirq * 4);
 
        if (on)
                pin_reg |= wake_mask;
        else
                pin_reg &= ~wake_mask;
 
-       writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+       writel(pin_reg, gpio_dev->base + hwirq * 4);
        raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
        if (on)
@@ -495,9 +500,10 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
        unsigned long flags;
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+       irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
        raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-       pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+       pin_reg = readl(gpio_dev->base + hwirq * 4);
 
        switch (type & IRQ_TYPE_SENSE_MASK) {
        case IRQ_TYPE_EDGE_RISING:
@@ -563,10 +569,10 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
        pin_reg_irq_en = pin_reg;
        pin_reg_irq_en |= mask;
        pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
-       writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
-       while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
+       writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4);
+       while ((readl(gpio_dev->base + hwirq * 4) & mask) != mask)
                continue;
-       writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+       writel(pin_reg, gpio_dev->base + hwirq * 4);
        raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
        return ret;