drm/i915/display: Add PHY_CMN1_CONTROL register definitions

Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS
sending.

Bspec: 68962
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250526120512.1702815-10-jouni.hogander@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 59c22beaf1de50e121b5e79753b5c3bed27403db..580a43be195e6e7a1b77ad45ca3d422eccf008fb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -285,6 +285,9 @@
 #define PHY_CX0_TX_CONTROL(tx, control)        (0x400 + ((tx) - 1) * 0x200 + (control))
 #define   CONTROL2_DISABLE_SINGLE_TX   REG_BIT(6)
 
+#define PHY_CMN1_CONTROL(tx, control)  (0x800 + ((tx) - 1) * 0x200 + (control))
+#define   CONTROL0_MAC_TRANSMIT_LFPS   REG_BIT(1)
+
 /* C20 Registers */
 #define PHY_C20_WR_ADDRESS_L           0xC02
 #define PHY_C20_WR_ADDRESS_H           0xC03