]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
ARM: dts: meson: add the clock inputs for the Meson timer
authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Fri, 16 Nov 2018 20:42:35 +0000 (21:42 +0100)
committerKevin Hilman <khilman@baylibre.com>
Thu, 29 Nov 2018 00:49:03 +0000 (16:49 -0800)
The Meson Timer IP block has two clock inputs:
- clk81 for using the system clock as timebase
- xtal for a timebase with 1us, 10us, 100us and 1ms resolution

The clocksource driver does not use these yet, but it's still a good
idea to add them as this describes how the hardware actually works
internally.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm/boot/dts/meson.dtsi
arch/arm/boot/dts/meson6.dtsi
arch/arm/boot/dts/meson8.dtsi
arch/arm/boot/dts/meson8b.dtsi

index f0255450bcb2f21058b2cfba094a2174b528c71f..0839da07a75ca9e20c7d509bf3137fe7c1bb7801 100644 (file)
                                interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
                        };
 
-                       timer@9940 {
+                       timer_abcde: timer@9940 {
                                compatible = "amlogic,meson6-timer";
                                reg = <0x9940 0x18>;
                                interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
index 9b463211339f5f5bc9156e88da3881607ba22ecc..ca978ab952cd6d6ec5f14649ae6e4284c8afbea9 100644 (file)
        status = "disabled";
 };
 
+&timer_abcde {
+       clocks = <&xtal>, <&clk81>;
+       clock-names = "xtal", "pclk";
+};
+
 &uart_AO {
        clocks = <&xtal>, <&clk81>, <&clk81>;
        clock-names = "xtal", "pclk", "baud";
index 08c54cf5420ad2b73a8167fabe13ad70d80bcc7e..3be5fbd07997b71f3adf517589ec7cf3600ffc86 100644 (file)
        clocks = <&clkc CLKID_CLK81>;
 };
 
+&timer_abcde {
+       clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+       clock-names = "xtal", "pclk";
+};
+
 &uart_AO {
        compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
        clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
index 46b3564a6536bc4ee0444cabf58afcb2b19de0cb..587a855f872bc394b6a3e5c6c86c0816f7da8f45 100644 (file)
        clock-names = "core", "clkin";
 };
 
+&timer_abcde {
+       clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+       clock-names = "xtal", "pclk";
+};
+
 &uart_AO {
        compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
        clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;