arm64: dts: qcom: sdm845: Add DT nodes for the TBUs

Add the device-tree nodes for the TBUs (translation buffer units) that
are present on the sdm845 platforms. The TBUs can be used debug the
kernel and provide additional information when a context faults occur.

Describe the all registers, clocks, interconnects and power-domain
resources that are needed for each of the TBUs.

Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
Link: https://lore.kernel.org/r/20240417133731.2055383-6-quic_c_gdjako@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 26b1638c76f9480a80807d13d9d16da37ed3e74f..493c99c8ce10483d28902ac1a40db85e6a26a811 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/firmware/qcom,scm.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sdm845.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -5107,6 +5108,78 @@
                                     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               anoc_1_tbu: tbu@150c5000 {
+                       compatible = "qcom,sdm845-tbu";
+                       reg = <0x0 0x150c5000 0x0 0x1000>;
+                       interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>;
+                       qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
+               };
+
+               anoc_2_tbu: tbu@150c9000 {
+                       compatible = "qcom,sdm845-tbu";
+                       reg = <0x0 0x150c9000 0x0 0x1000>;
+                       interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>;
+                       qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
+               };
+
+               mnoc_hf_0_tbu: tbu@150cd000 {
+                       compatible = "qcom,sdm845-tbu";
+                       reg = <0x0 0x150cd000 0x0 0x1000>;
+                       interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
+                       qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
+               };
+
+               mnoc_hf_1_tbu: tbu@150d1000 {
+                       compatible = "qcom,sdm845-tbu";
+                       reg = <0x0 0x150d1000 0x0 0x1000>;
+                       interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
+                       qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
+               };
+
+               mnoc_sf_0_tbu: tbu@150d5000 {
+                       compatible = "qcom,sdm845-tbu";
+                       reg = <0x0 0x150d5000 0x0 0x1000>;
+                       interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>;
+                       qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
+               };
+
+               compute_dsp_tbu: tbu@150d9000 {
+                       compatible = "qcom,sdm845-tbu";
+                       reg = <0x0 0x150d9000 0x0 0x1000>;
+                       interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
+               };
+
+               adsp_tbu: tbu@150dd000 {
+                       compatible = "qcom,sdm845-tbu";
+                       reg = <0x0 0x150dd000 0x0 0x1000>;
+                       interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>;
+                       qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
+               };
+
+               anoc_1_pcie_tbu: tbu@150e1000 {
+                       compatible = "qcom,sdm845-tbu";
+                       reg = <0x0 0x150e1000 0x0 0x1000>;
+                       clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+                       interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
+                       qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
+               };
+
                lpasscc: clock-controller@17014000 {
                        compatible = "qcom,sdm845-lpasscc";
                        reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;