uint32_t low, high;
uint64_t queue_addr = 0;
+ if (!adev->debug_exp_resets &&
+ !adev->gfx.num_gfx_rings)
+ return 0;
+
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
amdgpu_gfx_rlc_enter_safe_mode(adev, inst);
struct amdgpu_device *adev = ring->adev;
uint32_t value = 0;
+ if (!adev->debug_exp_resets)
+ return;
+
value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
unsigned long flags;
int r, i;
+ if (!adev->debug_exp_resets)
+ return -EINVAL;
+
if (amdgpu_sriov_vf(adev))
return -EINVAL;