RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vnmsub.vv to the
vnmsub.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

Before this patch:
  11   │     beq a3,zero,.L8
  12   │     vsetvli a5,zero,e32,m1,ta,ma
  13   │     vmv.v.x v2,a2
  ...
  16   │ .L3:
  17   │     vsetvli a5,a3,e32,m1,ta,ma
  ...
  22   │     vnmsub.vv v1,v2,v3
  ...
  25   │     bne a3,zero,.L3

After this patch:
  11   │     beq a3,zero,.L8
  ...
  14   │ .L3:
  15   │     vsetvli a5,a3,e32,m1,ta,ma
  ...
  20   │     vnmsub.vx v1,a2,v3
  ...
  23   │     bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*vnmsac_vx_<mode>): Rename from.
	(*mul_minus_vx_<mode>): Rename to and add nmsub support.
	* config/riscv/vector.md (@pred_vnmsac_vx_<mode>): Rename from.
	(@pred_mul_minus_vx_<mode>): Rename to and add nmsub support.
	(*pred_nmsac_<mode>_scalar_undef): Rename from.
	(*pred_mul_minus_vx<mode>_undef): Rename to and add nmsub support.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 331d08c2e4205d828f02cf5ce053f8f879d2f100..328ee0e096fe46a33e3ad9576450ba95ad7b037d 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1846,10 +1846,10 @@
   }
   [(set_attr "type" "vimuladd")])
 
-(define_insn_and_split "*vnmsac_vx_<mode>"
+(define_insn_and_split "*mul_minus_vx_<mode>"
  [(set (match_operand:V_VLSI 0 "register_operand")
    (minus:V_VLSI
-    (match_operand:V_VLSI   3 "register_operand")
+    (match_operand:V_VLSI    3 "register_operand")
     (mult:V_VLSI
      (vec_duplicate:V_VLSI
       (match_operand:<VEL>   1 "register_operand"))
@@ -1859,9 +1859,9 @@
   "&& 1"
   [(const_int 0)]
   {
-    insn_code icode = code_for_pred_vnmsac_vx (<MODE>mode);
-    rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
-                RVV_VUNDEF(<MODE>mode)};
+    insn_code icode = code_for_pred_mul_minus_vx (<MODE>mode);
+    rtx v_undef = RVV_VUNDEF(<MODE>mode);
+    rtx ops[] = {operands[0], operands[1], operands[2], operands[3], v_undef};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::TERNARY_OP, ops);
 
     DONE;

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 969510b752cf1a192806dd54b998e9104d7f0595..95d44baf6fddf7e8ecb54cc9a2294dc2eb888930 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -5493,7 +5493,7 @@
   "TARGET_VECTOR"
 {})
 
-(define_expand "@pred_vnmsac_vx_<mode>"
+(define_expand "@pred_mul_minus_vx_<mode>"
   [(set (match_operand:V_VLSI_QHS       0 "register_operand")
        (if_then_else:V_VLSI_QHS
          (unspec:<VM>
@@ -5516,7 +5516,7 @@
   riscv_vector::prepare_ternary_operands (operands);
 })
 
-(define_expand "@pred_vnmsac_vx_<mode>"
+(define_expand "@pred_mul_minus_vx_<mode>"
   [(set (match_operand:V_VLSI_D       0 "register_operand")
        (if_then_else:V_VLSI_D
          (unspec:<VM>
@@ -8888,52 +8888,56 @@
   [(set_attr "type" "vssegt<order>x")
    (set_attr "mode" "<V32T:MODE>")])
 
-(define_insn "*pred_nmsac_<mode>_scalar_undef"
-  [(set (match_operand:V_VLSI_QHS       0 "register_operand"      "=vd,  vr")
+(define_insn "*pred_mul_minus_vx<mode>_undef"
+  [(set (match_operand:V_VLSI_QHS       0 "register_operand"      "=vd,  vd,  vr,  vr")
        (if_then_else:V_VLSI_QHS
          (unspec:<VM>
-           [(match_operand:<VM>        1 "vector_mask_operand"   " vm, Wc1")
-            (match_operand             6 "vector_length_operand" "rvl, rvl")
-            (match_operand             7 "const_int_operand"     "  i,   i")
-            (match_operand             8 "const_int_operand"     "  i,   i")
-            (match_operand             9 "const_int_operand"     "  i,   i")
+           [(match_operand:<VM>        1 "vector_mask_operand"   " vm,  vm, Wc1, Wc1")
+            (match_operand             6 "vector_length_operand" "rvl, rvl, rvl, rvl")
+            (match_operand             7 "const_int_operand"     "  i,   i,   i,   i")
+            (match_operand             8 "const_int_operand"     "  i,   i,   i,   i")
+            (match_operand             9 "const_int_operand"     "  i,   i,   i,   i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (minus:V_VLSI_QHS
-           (match_operand:V_VLSI_QHS   5 "register_operand"     "   0,   0")
+           (match_operand:V_VLSI_QHS   5 "register_operand"     "  vr,   0,  vr,   0")
            (mult:V_VLSI_QHS
              (vec_duplicate:V_VLSI_QHS
-               (match_operand:<VEL>    3 "reg_or_0_operand"     "  rJ,  rJ"))
-             (match_operand:V_VLSI_QHS 4 "register_operand"     "  vr,  vr")))
+               (match_operand:<VEL>    3 "reg_or_0_operand"     "  rJ,  rJ,  rJ,  rJ"))
+             (match_operand:V_VLSI_QHS 4 "register_operand"     "   0,  vr,   0,  vr")))
          (match_operand:V_VLSI_QHS     2 "vector_undef_operand")))]
   "TARGET_VECTOR"
   "@
+   vnmsub.vx\t%0,%z3,%5%p1
    vnmsac.vx\t%0,%z3,%4%p1
+   vnmsub.vx\t%0,%z3,%5%p1
    vnmsac.vx\t%0,%z3,%4%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*pred_nmsac_<mode>_scalar_undef"
-  [(set (match_operand:V_VLSI_D       0 "register_operand"      "=vd,  vr")
+(define_insn "*pred_mul_minus_vx<mode>_undef"
+  [(set (match_operand:V_VLSI_D       0 "register_operand"      "=vd,  vd,  vr,  vr")
        (if_then_else:V_VLSI_D
          (unspec:<VM>
-           [(match_operand:<VM>      1 "vector_mask_operand"   " vm, Wc1")
-            (match_operand           6 "vector_length_operand" "rvl, rvl")
-            (match_operand           7 "const_int_operand"     "  i,   i")
-            (match_operand           8 "const_int_operand"     "  i,   i")
-            (match_operand           9 "const_int_operand"     "  i,   i")
+           [(match_operand:<VM>      1 "vector_mask_operand"   " vm,  vm, Wc1, Wc1")
+            (match_operand           6 "vector_length_operand" "rvl, rvl, rvl, rvl")
+            (match_operand           7 "const_int_operand"     "  i,   i,   i,   i")
+            (match_operand           8 "const_int_operand"     "  i,   i,   i,   i")
+            (match_operand           9 "const_int_operand"     "  i,   i,   i,   i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (minus:V_VLSI_D
-           (match_operand:V_VLSI_D   5 "register_operand"     "   0,   0")
+           (match_operand:V_VLSI_D   5 "register_operand"     "  vr,   0,  vr,   0")
            (mult:V_VLSI_D
              (vec_duplicate:V_VLSI_D
-               (match_operand:<VEL>  3 "reg_or_0_operand"     "  rJ,  rJ"))
-             (match_operand:V_VLSI_D 4 "register_operand"     "  vr,  vr")))
+               (match_operand:<VEL>  3 "reg_or_0_operand"     "  rJ,  rJ,  rJ,  rJ"))
+             (match_operand:V_VLSI_D 4 "register_operand"     "   0,  vr,   0,  vr")))
          (match_operand:V_VLSI_D     2 "vector_undef_operand")))]
   "TARGET_VECTOR && TARGET_64BIT"
   "@
+   vnmsub.vx\t%0,%z3,%5%p1
    vnmsac.vx\t%0,%z3,%4%p1
+   vnmsub.vx\t%0,%z3,%5%p1
    vnmsac.vx\t%0,%z3,%4%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")])