arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode

Add overlay to enable the PCIe0 and PCIe1 instances of PCIe on J784S4-EVM
in Endpoint mode of operation.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240529082259.1619695-4-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 381a7870c88fdd755e05fba5cdad3655faa9d550..d956372a716358128398086e2fc88da402181fdf 100644 (file)
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -103,6 +103,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
 # Boards with J784s4 SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
 
@@ -156,6 +157,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
        k3-j721e-sk-csi2-dual-imx219.dtbo
 k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
        k3-j721s2-evm-pcie1-ep.dtbo
+k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \
+       k3-j784s4-evm-pcie0-pcie1-ep.dtbo
 k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
        k3-j784s4-evm-quad-port-eth-exp1.dtbo
 k3-j784s4-evm-usxgmii-exp1-exp2-dtbs := k3-j784s4-evm.dtb \
@@ -182,6 +185,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
        k3-j721e-evm-pcie0-ep.dtb \
        k3-j721e-sk-csi2-dual-imx219.dtb \
        k3-j721s2-evm-pcie1-ep.dtb \
+       k3-j784s4-evm-pcie0-pcie1-ep.dtb \
        k3-j784s4-evm-quad-port-eth-exp1.dtb \
        k3-j784s4-evm-usxgmii-exp1-exp2.dtb
 

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
new file mode 100644 (file)
index 0000000..6853050
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE0 and PCIE1 instances in Endpoint Configuration
+ * on J784S4 EVM.
+ *
+ * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie0_rc {
+       status = "disabled";
+};
+
+&pcie1_rc {
+       status = "disabled";
+};
+
+&cbass_main {
+       #address-cells = <2>;
+       #size-cells = <2>;
+       interrupt-parent = <&gic500>;
+
+       pcie0_ep: pcie-ep@2900000 {
+               compatible = "ti,j784s4-pcie-ep";
+               reg = <0x00 0x02900000 0x00 0x1000>,
+                     <0x00 0x02907000 0x00 0x400>,
+                     <0x00 0x0d000000 0x00 0x00800000>,
+                     <0x00 0x10000000 0x00 0x08000000>;
+               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+               interrupt-names = "link_state";
+               interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+               ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+               max-link-speed = <3>;
+               num-lanes = <4>;
+               power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 332 0>;
+               clock-names = "fck";
+               max-functions = /bits/ 8 <6>;
+               max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+               dma-coherent;
+               phys = <&serdes1_pcie0_link>;
+               phy-names = "pcie-phy";
+       };
+
+       pcie1_ep: pcie-ep@2910000 {
+               compatible = "ti,j784s4-pcie-ep";
+               reg = <0x00 0x02910000 0x00 0x1000>,
+                     <0x00 0x02917000 0x00 0x400>,
+                     <0x00 0x0d800000 0x00 0x00800000>,
+                     <0x00 0x18000000 0x00 0x08000000>;
+               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+               interrupt-names = "link_state";
+               interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+               ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
+               max-link-speed = <3>;
+               num-lanes = <2>;
+               power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 333 0>;
+               clock-names = "fck";
+               max-functions = /bits/ 8 <6>;
+               max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+               dma-coherent;
+               phys = <&serdes0_pcie1_link>;
+               phy-names = "pcie-phy";
+       };
+};