misc: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later...

Systems that issue PCIe hot reset requests during a suspend/resume
cycle cause PCI1XXXX device revisions prior to C0 to get its GPIO
configuration registers reset to hardware default values. This results
in device inaccessibility and GPIO read/write failure. Starting with
Revision C0, support was added in the device hardware (via the Hot
Reset Disable Bit) to allow resetting only the PCIe interface and its
associated logic, but preserving the GPIO configurations during a hot
reset. This patch enables the hot reset disable feature during suspend/
resume for C0 and later revisions of the device.

mchp_pci1xxxx_gpio is an auxiliary child of mchp_pci1xxxx_gp and does
not have access to system register address space for reading the device
revision. Hence, the device revision is retrieved directly from PCIe
config space.

Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
Link: https://lore.kernel.org/r/20250513091557.3660-2-rengarajan.s@microchip.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
index c76ffa396669ba0f27e175d0bfb389ca010e689b..971ad7344767847c1903e316dce6e305d7d224a5 100644 (file)
--- a/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
+++ b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
@@ -7,12 +7,14 @@
 #include <linux/gpio/driver.h>
 #include <linux/bio.h>
 #include <linux/mutex.h>
+#include <linux/pci.h>
 #include <linux/kthread.h>
 #include <linux/interrupt.h>
 
 #include "mchp_pci1xxxx_gp.h"
 
 #define PCI1XXXX_NR_PINS               93
+#define PCI_DEV_REV_OFFSET             0x08
 #define PERI_GEN_RESET                 0
 #define OUT_EN_OFFSET(x)               ((((x) / 32) * 4) + 0x400)
 #define INP_EN_OFFSET(x)               ((((x) / 32) * 4) + 0x400 + 0x10)
@@ -41,8 +43,25 @@ struct pci1xxxx_gpio {
        struct gpio_chip gpio;
        spinlock_t lock;
        int irq_base;
+       u8 dev_rev;
 };
 
+static int pci1xxxx_gpio_get_device_revision(struct pci1xxxx_gpio *priv)
+{
+       struct device *parent = priv->aux_dev->dev.parent;
+       struct pci_dev *pcidev = to_pci_dev(parent);
+       int ret;
+       u32 val;
+
+       ret = pci_read_config_dword(pcidev, PCI_DEV_REV_OFFSET, &val);
+       if (ret)
+               return ret;
+
+       priv->dev_rev = val;
+
+       return 0;
+}
+
 static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
 {
        struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
@@ -316,6 +335,10 @@ static int pci1xxxx_gpio_suspend(struct device *dev)
        pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
                           17, false);
        pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true);
+
+       if (priv->dev_rev >= 0xC0)
+               pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 17, true);
+
        spin_unlock_irqrestore(&priv->lock, flags);
 
        return 0;
@@ -332,6 +355,10 @@ static int pci1xxxx_gpio_resume(struct device *dev)
        pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
                           16, false);
        pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false);
+
+       if (priv->dev_rev >= 0xC0)
+               pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 17, false);
+
        spin_unlock_irqrestore(&priv->lock, flags);
 
        return 0;
@@ -413,6 +440,10 @@ static int pci1xxxx_gpio_probe(struct auxiliary_device *aux_dev,
        if (retval < 0)
                return retval;
 
+       retval = pci1xxxx_gpio_get_device_revision(priv);
+       if (retval)
+               return retval;
+
        dev_set_drvdata(&aux_dev->dev, priv);
 
        return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv);