net: stmmac: visconti: re-arrange speed decode

Re-arrange the speed decode in visconti_eth_set_clk_tx_rate() to be
more readable by first checking to see if we're using RGMII or RMII
and then decoding the speed, rather than decoding the speed and then
testing the interface mode.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/E1uRH21-004UyG-50@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
index 5e6ac82a89b9f0def4efe8fcf41470620bff8973..ef86f9dce791e9348604e2106d32b85862a1194d 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
@@ -57,30 +57,38 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
                                        phy_interface_t interface, int speed)
 {
        struct visconti_eth *dwmac = bsp_priv;
-       struct net_device *netdev = dev_get_drvdata(dwmac->dev);
        unsigned int val, clk_sel_val = 0;
 
-       switch (speed) {
-       case SPEED_1000:
-               if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII)
+       if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) {
+               switch (speed) {
+               case SPEED_1000:
                        clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_125M;
-               break;
-       case SPEED_100:
-               if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII)
+                       break;
+
+               case SPEED_100:
                        clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_25M;
-               if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII)
-                       clk_sel_val = ETHER_CLK_SEL_DIV_SEL_2;
-               break;
-       case SPEED_10:
-               if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII)
+                       break;
+
+               case SPEED_10:
                        clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_2P5M;
-               if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII)
+                       break;
+
+               default:
+                       return -EINVAL;
+               }
+       } else if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII) {
+               switch (speed) {
+               case SPEED_100:
+                       clk_sel_val = ETHER_CLK_SEL_DIV_SEL_2;
+                       break;
+
+               case SPEED_10:
                        clk_sel_val = ETHER_CLK_SEL_DIV_SEL_20;
-               break;
-       default:
-               /* No bit control */
-               netdev_err(netdev, "Unsupported speed request (%d)", speed);
-               return -EINVAL;
+                       break;
+
+               default:
+                       return -EINVAL;
+               }
        }
 
        /* Stop internal clock */