PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up()

rockchip_pcie_link_up() currently has two issues:
1. Value 0x11 of PCIE_L0S_ENTRY corresponds to L0 state, not L0S. So the
naming is wrong from the very beginning.
2. Checking for value 0x11 treats other states like L0S and L1 as link
down, which is wrong.

Hence, remove the PCIE_L0S_ENTRY check and also its definition. This allows
adding ASPM support in the successive commits.

Fixes: 0e898eb8df4e ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[mani: commit message rewording]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/1744850111-236269-1-git-send-email-shawn.lin@rock-chips.com

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index c624b7ebd118c06a15da32ecf6966177232c7e4a..21dc99c9d95c8f7834a107d3cb89a87944fe62d8 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -44,7 +44,6 @@
 #define PCIE_LINKUP                    (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
 #define PCIE_RDLH_LINK_UP_CHGED                BIT(1)
 #define PCIE_LINK_REQ_RST_NOT_INT      BIT(2)
-#define PCIE_L0S_ENTRY                 0x11
 #define PCIE_CLIENT_GENERAL_CONTROL    0x0
 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
 #define PCIE_CLIENT_INTR_MASK_LEGACY   0x1c
@@ -177,8 +176,7 @@ static int rockchip_pcie_link_up(struct dw_pcie *pci)
        struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
        u32 val = rockchip_pcie_get_ltssm(rockchip);
 
-       if ((val & PCIE_LINKUP) == PCIE_LINKUP &&
-           (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
+       if ((val & PCIE_LINKUP) == PCIE_LINKUP)
                return 1;
 
        return 0;