]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ath11k: add extended interrupt support for QCN9074
authorKarthikeyan Periyasamy <periyasa@codeaurora.org>
Tue, 16 Feb 2021 07:16:24 +0000 (09:16 +0200)
committerKalle Valo <kvalo@codeaurora.org>
Wed, 17 Feb 2021 09:33:04 +0000 (11:33 +0200)
Update the specific hw ring mask for QCN9074. Update the timestamp
information while processing DP and CE interrupts.

Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1

Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org>
Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/1612946530-28504-11-git-send-email-akolli@codeaurora.org
drivers/net/wireless/ath/ath11k/core.c
drivers/net/wireless/ath/ath11k/dp_tx.c
drivers/net/wireless/ath/ath11k/hw.c
drivers/net/wireless/ath/ath11k/hw.h
drivers/net/wireless/ath/ath11k/pci.c

index 82b5e8c41f8fae19e2e4482daf54b158e1cf7ec7..ddedc331edef119cfbd54dedbce705ecb0c886bd 100644 (file)
@@ -162,6 +162,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
                .single_pdev_only = false,
                .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
                .hw_ops = &qcn9074_ops,
+               .ring_mask = &ath11k_hw_ring_mask_qcn9074,
                .internal_sleep_clock = false,
                .regs = &qcn9074_regs,
                .host_ce_config = ath11k_host_ce_config_qcn9074,
index f5c277977e080e9e7d83337d2ef386b644431632..8bba5234f81fc4723c14fd298500868004a3715e 100644 (file)
@@ -792,8 +792,8 @@ int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
        cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >>
                                              HAL_ADDR_MSB_REG_SHIFT;
 
-       cmd->ring_msi_addr_lo = params.msi_addr & 0xffffffff;
-       cmd->ring_msi_addr_hi = ((uint64_t)(params.msi_addr) >> 32) & 0xffffffff;
+       cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr);
+       cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr);
        cmd->msi_data = params.msi_data;
 
        cmd->intr_info = FIELD_PREP(
index c943e34c3721e12af5e6e0c3e82447e7d39aeb38..377ae8d5b58f1b45c14e77eef9dd7a178d7d6b68 100644 (file)
@@ -1435,6 +1435,47 @@ const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = {
        },
 };
 
+const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = {
+       .tx  = {
+               ATH11K_TX_RING_MASK_0,
+               ATH11K_TX_RING_MASK_1,
+               ATH11K_TX_RING_MASK_2,
+       },
+       .rx_mon_status = {
+               0, 0, 0,
+               ATH11K_RX_MON_STATUS_RING_MASK_0,
+               ATH11K_RX_MON_STATUS_RING_MASK_1,
+               ATH11K_RX_MON_STATUS_RING_MASK_2,
+       },
+       .rx = {
+               0, 0, 0, 0,
+               ATH11K_RX_RING_MASK_0,
+               ATH11K_RX_RING_MASK_1,
+               ATH11K_RX_RING_MASK_2,
+               ATH11K_RX_RING_MASK_3,
+       },
+       .rx_err = {
+               0, 0, 0,
+               ATH11K_RX_ERR_RING_MASK_0,
+       },
+       .rx_wbm_rel = {
+               0, 0, 0,
+               ATH11K_RX_WBM_REL_RING_MASK_0,
+       },
+       .reo_status = {
+               0, 0, 0,
+               ATH11K_REO_STATUS_RING_MASK_0,
+       },
+       .rxdma2host = {
+               0, 0, 0,
+               ATH11K_RXDMA2HOST_RING_MASK_0,
+       },
+       .host2rxdma = {
+               0, 0, 0,
+               ATH11K_HOST2RXDMA_RING_MASK_0,
+       },
+};
+
 const struct ath11k_hw_regs ipq8074_regs = {
        /* SW2TCL(x) R0 ring configuration address */
        .hal_tcl1_ring_base_lsb = 0x00000510,
index 54b7edfc4f8897ebf36484930c22b14b4d77ebce..c81a6328361d3f4d3a75c60d65cdb9fccabd3de6 100644 (file)
@@ -208,6 +208,7 @@ extern const struct ath11k_hw_ops qcn9074_ops;
 
 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
+extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074;
 
 static inline
 int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw,
index f58ee67626602cbab63983cb5ed0ddec4616aff9..74e4903562511047a1d1bd69b22b50ce3b56373f 100644 (file)
@@ -592,6 +592,9 @@ static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg)
 {
        struct ath11k_ce_pipe *ce_pipe = arg;
 
+       /* last interrupt received for this CE */
+       ce_pipe->timestamp = jiffies;
+
        ath11k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);
        tasklet_schedule(&ce_pipe->intr_tq);
 
@@ -686,6 +689,9 @@ static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg)
 
        ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq);
 
+       /* last interrupt received for this group */
+       irq_grp->timestamp = jiffies;
+
        ath11k_pci_ext_grp_disable(irq_grp);
 
        napi_schedule(&irq_grp->napi);
@@ -696,8 +702,9 @@ static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg)
 static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
 {
        int i, j, ret, num_vectors = 0;
-       u32 user_base_data = 0, base_vector = 0;
+       u32 user_base_data = 0, base_vector = 0, base_idx;
 
+       base_idx = ATH11K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
        ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP",
                                                 &num_vectors,
                                                 &user_base_data,
@@ -727,7 +734,7 @@ static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
                }
 
                irq_grp->num_irq = num_irq;
-               irq_grp->irqs[0] = base_vector + i;
+               irq_grp->irqs[0] = base_idx + i;
 
                for (j = 0; j < irq_grp->num_irq; j++) {
                        int irq_idx = irq_grp->irqs[j];
@@ -738,6 +745,8 @@ static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
 
                        ath11k_dbg(ab, ATH11K_DBG_PCI,
                                   "irq:%d group:%d\n", irq, i);
+
+                       irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
                        ret = request_irq(irq, ath11k_pci_ext_interrupt_handler,
                                          IRQF_SHARED,
                                          "DP_EXT_IRQ", irq_grp);