net/mlx5: Add support for MTPTM and MTCTR registers

Make Management Precision Time Measurement (MTPTM) register and Management
Cross Timestamp (MTCTR) register usable in mlx5 driver.

Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Wojciech Drewek <wojciech.drewek@intel.com>
Tested-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
Link: https://patch.msgid.link/20240730134055.1835261-2-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
index b61b7d96611413deda2c987282326d84a019531c..76ad46bf477d62eeb4e8d9cc134226432c5b9b7c 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
@@ -224,6 +224,7 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
        if (MLX5_CAP_GEN(dev, mcam_reg)) {
                mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
                mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
+               mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9180_0x91FF);
        }
 
        if (MLX5_CAP_GEN(dev, qcam_reg))

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index ba875a619b971c03ac5ccc090a8a761de869f82a..a94bc9e3af96be7febbd1a320930e9e873cbf9ba 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -1243,7 +1243,8 @@ enum mlx5_pcam_feature_groups {
 enum mlx5_mcam_reg_groups {
        MLX5_MCAM_REGS_FIRST_128                    = 0x0,
        MLX5_MCAM_REGS_0x9100_0x917F                = 0x2,
-       MLX5_MCAM_REGS_NUM                          = 0x3,
+       MLX5_MCAM_REGS_0x9180_0x91FF                = 0x3,
+       MLX5_MCAM_REGS_NUM                          = 0x4,
 };
 
 enum mlx5_mcam_feature_groups {
@@ -1392,6 +1393,10 @@ enum mlx5_qcam_feature_groups {
        MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
                 mng_access_reg_cap_mask.access_regs2.reg)
 
+#define MLX5_CAP_MCAM_REG3(mdev, reg) \
+       MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \
+                mng_access_reg_cap_mask.access_regs3.reg)
+
 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
        MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
 

diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index a96438ded15fe9b3ada935de2248f5ebf55b3a85..9f42834f57c59f65f05b115a8902d4f520769e46 100644 (file)
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -159,6 +159,8 @@ enum {
        MLX5_REG_MSECQ           = 0x9155,
        MLX5_REG_MSEES           = 0x9156,
        MLX5_REG_MIRC            = 0x9162,
+       MLX5_REG_MTPTM           = 0x9180,
+       MLX5_REG_MTCTR           = 0x9181,
        MLX5_REG_SBCAM           = 0xB01F,
        MLX5_REG_RESOURCE_DUMP   = 0xC000,
        MLX5_REG_DTOR            = 0xC00E,

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index cab228cf51c6347da2c0c58f25f802561d2ae468..234ad6f16e928fb3fc963caab696667a202483a8 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -10401,6 +10401,18 @@ struct mlx5_ifc_mcam_access_reg_bits2 {
        u8         regs_31_to_0[0x20];
 };
 
+struct mlx5_ifc_mcam_access_reg_bits3 {
+       u8         regs_127_to_96[0x20];
+
+       u8         regs_95_to_64[0x20];
+
+       u8         regs_63_to_32[0x20];
+
+       u8         regs_31_to_2[0x1e];
+       u8         mtctr[0x1];
+       u8         mtptm[0x1];
+};
+
 struct mlx5_ifc_mcam_reg_bits {
        u8         reserved_at_0[0x8];
        u8         feature_group[0x8];
@@ -10413,6 +10425,7 @@ struct mlx5_ifc_mcam_reg_bits {
                struct mlx5_ifc_mcam_access_reg_bits access_regs;
                struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
                struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
+               struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
                u8         reserved_at_0[0x80];
        } mng_access_reg_cap_mask;
 
@@ -11166,6 +11179,34 @@ struct mlx5_ifc_mtmp_reg_bits {
        u8         sensor_name_lo[0x20];
 };
 
+struct mlx5_ifc_mtptm_reg_bits {
+       u8         reserved_at_0[0x10];
+       u8         psta[0x1];
+       u8         reserved_at_11[0xf];
+
+       u8         reserved_at_20[0x60];
+};
+
+enum {
+       MLX5_MTCTR_REQUEST_NOP = 0x0,
+       MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
+       MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
+       MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
+};
+
+struct mlx5_ifc_mtctr_reg_bits {
+       u8         first_clock_timestamp_request[0x8];
+       u8         second_clock_timestamp_request[0x8];
+       u8         reserved_at_10[0x10];
+
+       u8         first_clock_valid[0x1];
+       u8         second_clock_valid[0x1];
+       u8         reserved_at_22[0x1e];
+
+       u8         first_clock_timestamp[0x40];
+       u8         second_clock_timestamp[0x40];
+};
+
 union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
        struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
@@ -11230,6 +11271,8 @@ union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
        struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
        struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
+       struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
+       struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
        u8         reserved_at_0[0x60e0];
 };