]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/i915/dpll: Rename crtc_get_shared_dpll
authorSuraj Kandpal <suraj.kandpal@intel.com>
Thu, 15 May 2025 07:17:55 +0000 (12:47 +0530)
committerSuraj Kandpal <suraj.kandpal@intel.com>
Tue, 20 May 2025 08:04:16 +0000 (13:34 +0530)
Rename crtc_get_shared_dpll to take into the individual PLL framework
which came in at DISPLAY_VER >= 14.
Also having shared dpll stuff also in intel_dpll.c is just confusing.

--v2
-Change naming to dpll_global to keep consistency with rest of the
naming

--v3
-Just use intel_dpll [Jani]

--v4
-Modify commit message [Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/20250515071801.2221120-9-suraj.kandpal@intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_dpll.c
drivers/gpu/drm/i915/display/intel_dpll.h

index 858d9397b6708263408ec89a4ecc3562b24bea6b..bb57e6a98064342e1cf90a0eafdd75b73a09fe2c 100644 (file)
@@ -4225,7 +4225,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
                crtc_state->update_wm_post = true;
 
        if (intel_crtc_needs_modeset(crtc_state)) {
-               ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
+               ret = intel_dpll_crtc_get_dpll(state, crtc);
                if (ret)
                        return ret;
        }
index 80de897a761fb59afdb90653666b49c12e9db722..4f8be9ac9f8afe03c037b5d0b86febbc989d046e 100644 (file)
@@ -28,8 +28,8 @@
 struct intel_dpll_global_funcs {
        int (*crtc_compute_clock)(struct intel_atomic_state *state,
                                  struct intel_crtc *crtc);
-       int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
-                                   struct intel_crtc *crtc);
+       int (*crtc_get_dpll)(struct intel_atomic_state *state,
+                            struct intel_crtc *crtc);
 };
 
 struct intel_limit {
@@ -1177,8 +1177,8 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
        return 0;
 }
 
-static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
-                                   struct intel_crtc *crtc)
+static int hsw_crtc_get_dpll(struct intel_atomic_state *state,
+                            struct intel_crtc *crtc)
 {
        struct intel_display *display = to_intel_display(state);
        struct intel_crtc_state *crtc_state =
@@ -1405,8 +1405,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
        return ret;
 }
 
-static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
-                                   struct intel_crtc *crtc)
+static int ilk_crtc_get_dpll(struct intel_atomic_state *state,
+                            struct intel_crtc *crtc)
 {
        struct intel_crtc_state *crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
@@ -1701,12 +1701,12 @@ static const struct intel_dpll_global_funcs dg2_dpll_funcs = {
 
 static const struct intel_dpll_global_funcs hsw_dpll_funcs = {
        .crtc_compute_clock = hsw_crtc_compute_clock,
-       .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
+       .crtc_get_dpll = hsw_crtc_get_dpll,
 };
 
 static const struct intel_dpll_global_funcs ilk_dpll_funcs = {
        .crtc_compute_clock = ilk_crtc_compute_clock,
-       .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
+       .crtc_get_dpll = ilk_crtc_get_dpll,
 };
 
 static const struct intel_dpll_global_funcs chv_dpll_funcs = {
@@ -1759,8 +1759,8 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
        return 0;
 }
 
-int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
-                                   struct intel_crtc *crtc)
+int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
+                            struct intel_crtc *crtc)
 {
        struct intel_display *display = to_intel_display(state);
        struct intel_crtc_state *crtc_state =
@@ -1773,10 +1773,10 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
        if (!crtc_state->hw.enable || crtc_state->intel_dpll)
                return 0;
 
-       if (!display->funcs.dpll->crtc_get_shared_dpll)
+       if (!display->funcs.dpll->crtc_get_dpll)
                return 0;
 
-       ret = display->funcs.dpll->crtc_get_shared_dpll(state, crtc);
+       ret = display->funcs.dpll->crtc_get_dpll(state, crtc);
        if (ret) {
                drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
                            crtc->base.base.id, crtc->base.name);
index 280e90a57c87516522675c968db036e07b49d226..3444a2dd3166e5b73c1a23f8ebf5560ff152935c 100644 (file)
@@ -19,8 +19,8 @@ struct intel_dpll_hw_state;
 void intel_dpll_init_clock_hook(struct intel_display *display);
 int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
                                  struct intel_crtc *crtc);
-int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
-                                   struct intel_crtc *crtc);
+int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
+                            struct intel_crtc *crtc);
 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
 void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,