RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vminu.vv to the
vminu.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_VX_BINARY(T, FUNC)                                      \
  void                                                                \
  test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
  {                                                                   \
    for (unsigned i = 0; i < n; i++)                                  \
      out[i] = FUNC (in[i], x);                                       \
  }

  uint32_t min(uint32 a, uint32 b)
  {
    return a > b ? b : a;
  }

  DEF_VX_BINARY(uint32_t, min)

Before this patch:
  10   │ test_vx_binary_or_int32_t_case_0:
  11   │     beq a3,zero,.L8
  12   │     vsetvli a5,zero,e32,m1,ta,ma
  13   │     vmv.v.x v2,a2
  14   │     slli    a3,a3,32
  15   │     srli    a3,a3,32
  16   │ .L3:
  17   │     vsetvli a5,a3,e32,m1,ta,ma
  18   │     vle32.v v1,0(a1)
  19   │     slli    a4,a5,2
  20   │     sub a3,a3,a5
  21   │     add a1,a1,a4
  22   │     vminu.vv v1,v1,v2
  23   │     vse32.v v1,0(a0)
  24   │     add a0,a0,a4
  25   │     bne a3,zero,.L3

After this patch:
  10   │ test_vx_binary_or_int32_t_case_0:
  11   │     beq a3,zero,.L8
  12   │     slli    a3,a3,32
  13   │     srli    a3,a3,32
  14   │ .L3:
  15   │     vsetvli a5,a3,e32,m1,ta,ma
  16   │     vle32.v v1,0(a1)
  17   │     slli    a4,a5,2
  18   │     sub a3,a3,a5
  19   │     add a1,a1,a4
  20   │     vminu.vx v1,v1,a2
  21   │     vse32.v v1,0(a0)
  22   │     add a0,a0,a4
  23   │     bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_vx_binary_vec_dup_vec): Add
	new case UMIN.
	(expand_vx_binary_vec_vec_dup): Ditto.
	* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
	* config/riscv/vector-iterators.md: Add new op umin.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a903de9280ab4c720204e7e1fb2c480379544622..ac690df3688aed6e3fc9774b388927dd364105bb 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5540,6 +5540,7 @@ expand_vx_binary_vec_dup_vec (rtx op_0, rtx op_1, rtx op_2,
     case SMAX:
     case UMAX:
     case SMIN:
+    case UMIN:
       icode = code_for_pred_scalar (code, mode);
       break;
     case MINUS:
@@ -5577,6 +5578,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx op_2,
     case SMAX:
     case UMAX:
     case SMIN:
+    case UMIN:
       icode = code_for_pred_scalar (code, mode);
       break;
     default:

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 86444b0bef8e339cb288c804a9ff22864adf0736..3c1bb74675a201f3a8649b3d6dbb1320be3851a6 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4012,6 +4012,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
              case SMAX:
              case UMAX:
              case SMIN:
+             case UMIN:
                {
                  rtx op;
                  rtx op_0 = XEXP (x, 0);

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 6cfa9269f93578b6263c62db444bee043a66ec22..44ae79c48aa7cd1cf75726f1a79b63285e89d355 100644 (file)
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,11 +4042,11 @@
 ])
 
 (define_code_iterator any_int_binop_no_shift_v_vdup [
-  plus minus and ior xor mult div udiv mod umod smax umax smin
+  plus minus and ior xor mult div udiv mod umod smax umax smin umin
 ])
 
 (define_code_iterator any_int_binop_no_shift_vdup_v [
-  plus minus and ior xor mult smax umax smin
+  plus minus and ior xor mult smax umax smin umin
 ])
 
 (define_code_iterator any_int_unop [neg not])