RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vmaxu.vv to the
vmaxu.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_VX_BINARY(T, OP)                                        \
  void                                                                \
  test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
  {                                                                   \
    for (unsigned i = 0; i < n; i++)                                  \
      out[i] = in[i] OP x;                                            \
  }

  DEF_VX_BINARY(int32_t, /)

Before this patch:
  10   │ test_vx_binary_or_int32_t_case_0:
  11   │     beq a3,zero,.L8
  12   │     vsetvli a5,zero,e32,m1,ta,ma
  13   │     vmv.v.x v2,a2
  14   │     slli    a3,a3,32
  15   │     srli    a3,a3,32
  16   │ .L3:
  17   │     vsetvli a5,a3,e32,m1,ta,ma
  18   │     vle32.v v1,0(a1)
  19   │     slli    a4,a5,2
  20   │     sub a3,a3,a5
  21   │     add a1,a1,a4
  22   │     vmaxu.vv v1,v1,v2
  23   │     vse32.v v1,0(a0)
  24   │     add a0,a0,a4
  25   │     bne a3,zero,.L3

After this patch:
  10   │ test_vx_binary_or_int32_t_case_0:
  11   │     beq a3,zero,.L8
  12   │     slli    a3,a3,32
  13   │     srli    a3,a3,32
  14   │ .L3:
  15   │     vsetvli a5,a3,e32,m1,ta,ma
  16   │     vle32.v v1,0(a1)
  17   │     slli    a4,a5,2
  18   │     sub a3,a3,a5
  19   │     add a1,a1,a4
  20   │     vmaxu.vx v1,v1,a2
  21   │     vse32.v v1,0(a0)
  22   │     add a0,a0,a4
  23   │     bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_vx_binary_vec_dup_vec): Add new
	case UMAX.
	(expand_vx_binary_vec_vec_dup): Ditto.
	* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
	* config/riscv/vector-iterators.md: Add new op umax.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index ef69991b431a5034de2fc5cf96fac051fa393e51..011594966d35f9a4e07f3c94bc7024636d889021 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5538,6 +5538,7 @@ expand_vx_binary_vec_dup_vec (rtx op_0, rtx op_1, rtx op_2,
     case XOR:
     case MULT:
     case SMAX:
+    case UMAX:
       icode = code_for_pred_scalar (code, mode);
       break;
     case MINUS:
@@ -5573,6 +5574,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx op_2,
     case MOD:
     case UMOD:
     case SMAX:
+    case UMAX:
       icode = code_for_pred_scalar (code, mode);
       break;
     default:

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f6608bd872b3a9a7f421f52e911038fc7ffe7399..74462cc76a590ac7a57002d85eaca125753010be 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3979,6 +3979,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
              case XOR:
              case MULT:
              case SMAX:
+             case UMAX:
                {
                  rtx op;
                  rtx op_0 = XEXP (x, 0);

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index c9b836cc042b65274d823f5431de42492ffcfab5..1e048c190a821c5e4c19de07d9daa9215cbbbca2 100644 (file)
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,11 +4042,11 @@
 ])
 
 (define_code_iterator any_int_binop_no_shift_v_vdup [
-  plus minus and ior xor mult div udiv mod umod smax
+  plus minus and ior xor mult div udiv mod umod smax umax
 ])
 
 (define_code_iterator any_int_binop_no_shift_vdup_v [
-  plus minus and ior xor mult smax
+  plus minus and ior xor mult smax umax
 ])
 
 (define_code_iterator any_int_unop [neg not])