PINMUX_NOGP_ALL(),
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - Audio Clock ------------------------------------------------------------ */
static const unsigned int audio_clka_pins[] = {
/* CLKA */
static const unsigned int audio_clkout_c_mux[] = {
AUDIO_CLKOUT_C_MARK,
};
+#endif
+
/* - AVB -------------------------------------------------------------------- */
static const unsigned int avb_link_pins[] = {
RCAR_GP_PIN(3, 26),
AVB_COL_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - CAN -------------------------------------------------------------------- */
static const unsigned int can0_data_pins[] = {
/* TX, RX */
static const unsigned int du1_disp_mux[] = {
DU1_DISP_MARK
};
+#endif
+
/* - ETH -------------------------------------------------------------------- */
static const unsigned int eth_link_pins[] = {
/* LINK */
static const unsigned int i2c5_d_mux[] = {
I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
};
+
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - INTC ------------------------------------------------------------------- */
static const unsigned int intc_irq0_pins[] = {
/* IRQ0 */
static const unsigned int intc_irq9_mux[] = {
IRQ9_MARK,
};
+#endif
+
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc_data_pins[] = {
/* D[0:7] */
static const unsigned int mmc_ctrl_mux[] = {
MMC_CLK_MARK, MMC_CMD_MARK,
};
+
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+#endif
+
/* - QSPI ------------------------------------------------------------------- */
static const unsigned int qspi_ctrl_pins[] = {
/* SPCLK, SSL */
static const unsigned int sdhi2_wp_mux[] = {
SD2_WP_MARK,
};
+
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - SSI -------------------------------------------------------------------- */
static const unsigned int ssi0_data_pins[] = {
/* SDATA0 */
static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
+#endif
+
/* - TPU -------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
RCAR_GP_PIN(3, 31),
USB1_PWEN_MARK,
USB1_OVC_MARK,
};
+
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - VIN0 ------------------------------------------------------------------- */
static const unsigned int vin0_data_pins[] = {
/* B */
static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
+#endif
static const struct sh_pfc_pin_group pinmux_groups[] = {
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(audio_clka),
SH_PFC_PIN_GROUP(audio_clka_b),
SH_PFC_PIN_GROUP(audio_clka_c),
SH_PFC_PIN_GROUP(audio_clkout),
SH_PFC_PIN_GROUP(audio_clkout_b),
SH_PFC_PIN_GROUP(audio_clkout_c),
+#endif
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_gmii),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can0_data_c),
SH_PFC_PIN_GROUP(du1_oddf),
SH_PFC_PIN_GROUP(du1_cde),
SH_PFC_PIN_GROUP(du1_disp),
+#endif
SH_PFC_PIN_GROUP(eth_link),
SH_PFC_PIN_GROUP(eth_magic),
SH_PFC_PIN_GROUP(eth_mdio),
SH_PFC_PIN_GROUP(i2c5_b),
SH_PFC_PIN_GROUP(i2c5_c),
SH_PFC_PIN_GROUP(i2c5_d),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(intc_irq0),
SH_PFC_PIN_GROUP(intc_irq1),
SH_PFC_PIN_GROUP(intc_irq2),
SH_PFC_PIN_GROUP(intc_irq7),
SH_PFC_PIN_GROUP(intc_irq8),
SH_PFC_PIN_GROUP(intc_irq9),
+#endif
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(pwm5_c),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(pwm6_b),
+#endif
SH_PFC_PIN_GROUP(qspi_ctrl),
BUS_DATA_PIN_GROUP(qspi_data, 2),
BUS_DATA_PIN_GROUP(qspi_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(ssi0_data),
SH_PFC_PIN_GROUP(ssi0129_ctrl),
SH_PFC_PIN_GROUP(ssi1_data),
SH_PFC_PIN_GROUP(ssi9_ctrl),
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+#endif
SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(tpu_to0_b),
SH_PFC_PIN_GROUP(tpu_to0_c),
SH_PFC_PIN_GROUP(tpu_to3_c),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
+#ifdef CONFIG_PINCTRL_PFC_FULL
BUS_DATA_PIN_GROUP(vin0_data, 24),
BUS_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
SH_PFC_PIN_GROUP(vin1_clk),
+#endif
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const audio_clk_groups[] = {
"audio_clka",
"audio_clka_b",
"audio_clkout_b",
"audio_clkout_c",
};
+#endif
static const char * const avb_groups[] = {
"avb_link",
"avb_gmii",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const can0_groups[] = {
"can0_data",
"can0_data_b",
"du1_cde",
"du1_disp",
};
+#endif
static const char * const eth_groups[] = {
"eth_link",
"i2c5_d",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const intc_groups[] = {
"intc_irq0",
"intc_irq1",
"intc_irq8",
"intc_irq9",
};
+#endif
static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_ctrl",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"pwm6",
"pwm6_b",
};
+#endif
static const char * const qspi_groups[] = {
"qspi_ctrl",
"sdhi2_wp",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const ssi_groups[] = {
"ssi0_data",
"ssi0129_ctrl",
"ssi9_data_b",
"ssi9_ctrl_b",
};
+#endif
static const char * const tpu_groups[] = {
"tpu_to0",
"usb1",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const vin0_groups[] = {
"vin0_data24",
"vin0_data20",
"vin1_clkenb",
"vin1_clk",
};
+#endif
static const struct sh_pfc_function pinmux_functions[] = {
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(audio_clk),
+#endif
SH_PFC_FUNCTION(avb),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
+#endif
SH_PFC_FUNCTION(eth),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c4),
SH_PFC_FUNCTION(i2c5),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(intc),
+#endif
SH_PFC_FUNCTION(mmc),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
+#endif
SH_PFC_FUNCTION(qspi),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(ssi),
+#endif
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(vin0),
SH_PFC_FUNCTION(vin1),
+#endif
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {