mtd: spi-nor: Add entries for mt25q variants

Add entries for mt25q*256a and mt25q*512a flashes. These are similar to
existing n25q variants but support stateless 4 byte addressing opcodes

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index c9e054c8d437653cf45a44175f2cb2b1abf23be6..77d29604d4dbfb0a09c1b9e84ad9355db8a8842d 100644 (file)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2478,8 +2478,17 @@ static const struct flash_info spi_nor_ids[] = {
        { "n25q064a",    INFO(0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
        { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
        { "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
+       { "mt25ql256a",  INFO6(0x20ba19, 0x104400, 64 * 1024,  512,
+                              SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+                              SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
        { "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+       { "mt25qu256a",  INFO6(0x20bb19, 0x104400, 64 * 1024,  512,
+                              SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+                              SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
        { "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
+       { "mt25ql512a",  INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
+                              SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+                              SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
        { "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
        { "mt25qu512a",  INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
                               SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |