- script: |
KSYMLST=`mktemp`
KUSEDLST=`mktemp`
+ RET=0
cat `find . -name "Kconfig*"` | \
sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
cut -d , -f 3`
if [[ $NUM -ne 0 ]]; then
- echo "Unmigrated symbols found in $CFG"
- exit 1
+ echo "Unmigrated symbols found in $CFG:"
+ comm -12 ${KSYMLST} ${KUSEDLST}
+ RET=1
fi
done
+ exit $RET
- job: cppcheck
displayName: 'Static code analysis with cppcheck'
script:
- KSYMLST=`mktemp`;
KUSEDLST=`mktemp`;
+ RET=0;
cat `find . -name "Kconfig*"` |
sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
cut -d , -f 3`;
if [[ $NUM -ne 0 ]]; then
- echo "Unmigrated symbols found in $CFG";
- exit 1;
+ echo "Unmigrated symbols found in $CFG:";
+ comm -12 ${KSYMLST} ${KUSEDLST};
+ RET=1;
fi;
- done
+ done;
+ exit $RET
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
hex "Size of malloc() pool before relocation"
depends on SYS_MALLOC_F
default 0x1000 if AM33XX
- default 0x4000 if SANDBOX
- default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
- ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
- ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
- ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI || ARCH_OWL)
+ default 0x4000 if SANDBOX || RISCV
+ default 0x2000 if (ARCH_MX7 || ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
+ ARCH_QEMU || ARCH_SUNXI || ARCH_OWL || IMX8MQ)
+ default 0x10000 if (ARCH_IMX8 || (ARCH_IMX8M && !IMX8MQ) || \
+ ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
+ ARCH_LS1046A)
default 0x400
help
Before relocation, memory is very limited on many platforms. Still,
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
+ default 0x4000000 if SANDBOX
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
default 0x200000 if ARCH_BMIPS || X86
default 0x120000 if MACH_SUNIV
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
+config VALGRIND
+ bool "Inform valgrind about memory allocations"
+ help
+ Valgrind is an instrumentation framework for building dynamic analysis
+ tools. In particular, it may be used to detect memory management bugs
+ in U-Boot. It relies on knowing when heap blocks are allocated in
+ order to give accurate results. This happens automatically for
+ standard allocator functions provided by the host OS. However, this
+ doesn't automatically happen for U-Boot's malloc implementation.
+
+ Enable this option to annotate U-Boot's malloc implementation so that
+ it can be handled accurately by Valgrind. If you aren't planning on
+ using valgrind to debug U-Boot, say 'n'.
+
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
special image will be automatically built upon calling
make / buildman.
+config HAS_BOARD_SIZE_LIMIT
+ bool "Define a maximum size for the U-Boot image"
+ default y if RCAR_GEN3
+ help
+ In some cases, we need to enforce a hard limit on how big the U-Boot
+ image itself can be.
+
+config BOARD_SIZE_LIMIT
+ int "Maximum size of the U-Boot image in bytes"
+ default 1048576 if RCAR_GEN3
+ depends on HAS_BOARD_SIZE_LIMIT
+ help
+ Maximum size of the U-Boot image. When defined, the build system
+ checks that the actual size does not exceed it. This does not
+ include SPL nor TPL, on platforms that use that functionality, they
+ have a separate option to restict size.
+
config SYS_CUSTOM_LDSCRIPT
bool "Use a custom location for the U-Boot linker script"
help
Full name SPDX Identifier OSI Approved File name URI
=======================================================================================================================================
+bzip2 and libbzip2 License v1.0.6 bzip2-1.0.6 bzip2-1.0.6.txt https://spdx.org/licenses/bzip2-1.0.6.html
GNU General Public License v2.0 only GPL-2.0 Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt
GNU General Public License v2.0 or later GPL-2.0+ Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt
GNU Library General Public License v2 or later LGPL-2.0+ Y lgpl-2.0.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.0.txt
--- /dev/null
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+2. The origin of this software must not be misrepresented; you must
+ not claim that you wrote the original software. If you use this
+ software in a product, an acknowledgment in the product
+ documentation would be appreciated but is not required.
+
+3. Altered source versions must be plainly marked as such, and must
+ not be misrepresented as being the original software.
+
+4. The name of the author may not be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
F: drivers/ram/stm32mp1/
F: drivers/remoteproc/stm32_copro.c
F: drivers/reset/stm32-reset.c
+F: drivers/rng/optee_rng.c
F: drivers/rng/stm32mp1_rng.c
F: drivers/rtc/stm32_rtc.c
F: drivers/serial/serial_stm32.*
F: board/sunxi/
F: drivers/clk/sunxi/
F: drivers/phy/allwinner/
+F: drivers/pinctrl/sunxi/
F: drivers/video/sunxi/
+F: tools/sunxi*
ARM TEGRA
M: Tom Warren <twarren@nvidia.com>
F: drivers/net/zynq_gem.c
F: drivers/phy/phy-zynqmp.c
F: drivers/power/domain/zynqmp-power-domain.c
+F: drivers/pwm/pwm-cadence-ttc.c
F: drivers/serial/serial_zynq.c
F: drivers/reset/reset-zynqmp.c
F: drivers/rtc/zynqmp_rtc.c
F: drivers/watchdog/sp805_wdt.c
F: drivers/watchdog/sbsa_gwdt.c
+GATEWORKS_SC
+M: Tim Harvey <tharvey@gateworks.com>
+S: Maintained
+F: drivers/misc/gsc.c
+F: include/gsc.h
+
I2C
M: Heiko Schocher <hs@denx.de>
S: Maintained
F: doc/kwboot.1
F: tools/kwb*
+LED
+M: Ivan Vozvakhov <i.vozvakhov@vk.team>
+S: Supported
+F: doc/device-tree-bindings/leds/leds-pwm.txt
+F: drivers/led/led_pwm.c
+
LOGGING
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: configs/tools-only_defconfig
F: *
F: */
+
+CAAM
+M: Gaurav Jain <gaurav.jain@nxp.com>
+S: Maintained
+F: drivers/crypto/fsl/
+F: include/fsl_sec.h
VERSION = 2022
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc5
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
quiet_cmd_u-boot-elf ?= LD $@
cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \
+ $(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \
-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
-Ttext=$(CONFIG_SYS_TEXT_BASE)
u-boot.elf: u-boot.bin u-boot-elf.lds
# Run the environment text file through the preprocessor, but only if it is
# non-empty, to save time and possible build errors if something is wonky with
-# the board
+# the board.
+# If there is no ENV_FILE, produce an empty output file, to prevent a previous
+# build's file being used in the case of in-tree builds.
quiet_cmd_gen_envp = ENVP $@
cmd_gen_envp = \
if [ -s "$(ENV_FILE)" ]; then \
-I$(srctree)/arch/$(ARCH)/include \
$< -o $@; \
else \
+ rm -f $@; \
touch $@ ; \
fi
include/generated/env.in: include/generated/env.txt FORCE
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
- drivers/video/u_boot_logo.S tools/version.h \
- u-boot* MLO* SPL System.map fit-dtb.blob* \
+ include/generated/env.in drivers/video/u_boot_logo.S \
+ tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \
quiet_cmd_genenv = GENENV $@
cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \
- sed --in-place -e 's/\x00/\x0A/g' $@
+ sed --in-place -e 's/\x00/\x0A/g' $@; sed --in-place -e '/^\s*$$/d' $@; \
+ sort --field-separator== -k1,1 --stable $@ -o $@
u-boot-initial-env: u-boot.bin
$(call if_changed,genenv)
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
- CONFIG_SYS_FSL_HAS_DP_DDR
- Defines the SoC has DP-DDR used for DPAA.
-
CONFIG_SYS_FSL_SEC_BE
Defines the SEC controller register space as Big Endian
of the backslashes before semicolons and special
symbols.
-- Command Line Editing and History:
- CONFIG_CMDLINE_PS_SUPPORT
-
- Enable support for changing the command prompt string
- at run-time. Only static string is supported so far.
- The string is obtained from environment variables PS1
- and PS2.
-
- Default Environment:
CONFIG_EXTRA_ENV_SETTINGS
later, once stdio is running and output goes to the LCD, if
present.
-- CONFIG_BOARD_SIZE_LIMIT:
- Maximum size of the U-Boot image. When defined, the
- build system checks that the actual size does not
- exceed it.
-
Low Level (hardware related) configuration options:
---------------------------------------------------
this functionality.
config SYS_IMMR
- hex
+ hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
default 0xFF000000 if MPC8xx
default 0xF0000000 if ARCH_MPC8313
config ARCH_IMX8
bool "NXP i.MX8 platform"
select ARM64
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
select DM
select GPIO_EXTRA_HEADER
select MACH_IMX
select ARM64
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select SYS_I2C_MXC
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select ROM_UNIFIED_SECTIONS
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
imply BOARD_EARLY_INIT_F
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
+ select PINCTRL
select SPECIFY_CONSOLE_INDEX
select SPL_SEPARATE_BSS if SPL
select SPL_STACK_R if SPL
obj-y += cpu.o
-obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
# some files can only build in ARM mode
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Cirrus Logic EP93xx CPU-specific Makefile
-#
-# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
-#
-# Copyright (C) 2004, 2005
-# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
-#
-# Copyright (C) 2006
-# Dominic Rath <Dominic.Rath@gmx.de>
-#
-# Based on an original Makefile, which is
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = cpu.o led.o speed.o timer.o
-obj-y += lowlevel_init.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic EP93xx CPU-specific support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-
-/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
-extern void reset_cpu(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- uint32_t value;
-
- /* Unlock DeviceCfg and set SWRST */
- writel(0xAA, &syscon->sysswlock);
- value = readl(&syscon->devicecfg);
- value |= SYSCON_DEVICECFG_SWRST;
- writel(value, &syscon->devicecfg);
-
- /* Unlock DeviceCfg and clear SWRST */
- writel(0xAA, &syscon->sysswlock);
- value = readl(&syscon->devicecfg);
- value &= ~SYSCON_DEVICECFG_SWRST;
- writel(value, &syscon->devicecfg);
-
- /* Dying... */
- while (1)
- ; /* noop */
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- */
-
-#include <asm/io.h>
-#include <asm/arch/ep93xx.h>
-#include <config.h>
-#include <status_led.h>
-
-static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
-static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
- 1 << CONFIG_LED_STATUS_RED};
-
-static inline void switch_LED_on(uint8_t led)
-{
- register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
- writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
- saved_state[led] = CONFIG_LED_STATUS_ON;
-}
-
-static inline void switch_LED_off(uint8_t led)
-{
- register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
- writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
- saved_state[led] = CONFIG_LED_STATUS_OFF;
-}
-
-void red_led_on(void)
-{
- switch_LED_on(CONFIG_LED_STATUS_RED);
-}
-
-void red_led_off(void)
-{
- switch_LED_off(CONFIG_LED_STATUS_RED);
-}
-
-void green_led_on(void)
-{
- switch_LED_on(CONFIG_LED_STATUS_GREEN);
-}
-
-void green_led_off(void)
-{
- switch_LED_off(CONFIG_LED_STATUS_GREEN);
-}
-
-void __led_init(led_id_t mask, int state)
-{
- __led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
- if (CONFIG_LED_STATUS_RED == mask) {
- if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
- red_led_off();
- else
- red_led_on();
- } else if (CONFIG_LED_STATUS_GREEN == mask) {
- if (CONFIG_LED_STATUS_ON ==
- saved_state[CONFIG_LED_STATUS_GREEN])
- green_led_off();
- else
- green_led_on();
- }
-}
-
-void __led_set(led_id_t mask, int state)
-{
- if (CONFIG_LED_STATUS_RED == mask) {
- if (CONFIG_LED_STATUS_ON == state)
- red_led_on();
- else
- red_led_off();
- } else if (CONFIG_LED_STATUS_GREEN == mask) {
- if (CONFIG_LED_STATUS_ON == state)
- green_led_on();
- else
- green_led_off();
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Low-level initialization for EP93xx
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- * Copyright (C) 2013
- * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
- * Copyright (C) 2006 Cirrus Logic Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- */
-
-#include <config.h>
-#include <asm/arch-ep93xx/ep93xx.h>
-
-/*
-/* Configure the SDRAM based on the supplied settings.
- *
- * Input: r0 - SDRAM DEVCFG register
- * r2 - configuration for SDRAM chips
- * Output: none
- * Modifies: r3, r4
- */
-ep93xx_sdram_config:
- /* Program the SDRAM device configuration register. */
- ldr r3, =SDRAM_BASE
-#ifdef CONFIG_EDB93XX_SDCS0
- str r0, [r3, #SDRAM_OFF_DEVCFG0]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS1
- str r0, [r3, #SDRAM_OFF_DEVCFG1]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS2
- str r0, [r3, #SDRAM_OFF_DEVCFG2]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS3
- str r0, [r3, #SDRAM_OFF_DEVCFG3]
-#endif
-
- /* Set the Initialize and MRS bits (issue continuous NOP commands
- * (INIT & MRS set))
- */
- ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
- EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
- EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
- str r4, [r3, #SDRAM_OFF_GLCONFIG]
-
- /* Delay for 200us. */
- mov r4, #0x3000
-delay1:
- subs r4, r4, #1
- bne delay1
-
- /* Clear the MRS bit to issue a precharge all. */
- ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
- EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
- str r4, [r3, #SDRAM_OFF_GLCONFIG]
-
- /* Temporarily set the refresh timer to 0x10. Make it really low so
- * that refresh cycles are generated.
- */
- ldr r4, =0x10
- str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
-
- /* Delay for at least 80 SDRAM clock cycles. */
- mov r4, #80
-delay2:
- subs r4, r4, #1
- bne delay2
-
- /* Set the refresh timer to the fastest required for any device
- * that might be used. Set 9.6 ms refresh time.
- */
- ldr r4, =0x01e0
- str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
-
- /* Select mode register update mode. */
- ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
- EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
- str r4, [r3, #SDRAM_OFF_GLCONFIG]
-
- /* Program the mode register on the SDRAM by performing fake read */
- ldr r4, [r2]
-
- /* Select normal operating mode. */
- ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
- str r4, [r3, #SDRAM_OFF_GLCONFIG]
-
- /* Return to the caller. */
- mov pc, lr
-
-/*
- * Test to see if the SDRAM has been configured in a usable mode.
- *
- * Input: r0 - Test address of SDRAM
- * Output: r0 - 0 -- Test OK, -1 -- Failed
- * Modifies: r0-r5
- */
-ep93xx_sdram_test:
- /* Load the test patterns to be written to SDRAM. */
- ldr r1, =0xf00dface
- ldr r2, =0xdeadbeef
- ldr r3, =0x08675309
- ldr r4, =0xdeafc0ed
-
- /* Store the test patterns to SDRAM. */
- stmia r0, {r1-r4}
-
- /* Load the test patterns from SDRAM one at a time and compare them
- * to the actual pattern.
- */
- ldr r5, [r0]
- cmp r5, r1
- ldreq r5, [r0, #0x0004]
- cmpeq r5, r2
- ldreq r5, [r0, #0x0008]
- cmpeq r5, r3
- ldreq r5, [r0, #0x000c]
- cmpeq r5, r4
-
- /* Return -1 if a mismatch was encountered, 0 otherwise. */
- mvnne r0, #0xffffffff
- moveq r0, #0x00000000
-
- /* Return to the caller. */
- mov pc, lr
-
-/*
- * Determine the size of the SDRAM. Use data=address for the scan.
- *
- * Input: r0 - Start SDRAM address
- * Return: r0 - Single block size
- * r1 - Valid block mask
- * r2 - Total block count
- * Modifies: r0-r5
- */
-ep93xx_sdram_size:
- /* Store zero at offset zero. */
- str r0, [r0]
-
- /* Start checking for an alias at 1MB into SDRAM. */
- ldr r1, =0x00100000
-
- /* Store the offset at the current offset. */
-check_block_size:
- str r1, [r0, r1]
-
- /* Read back from zero. */
- ldr r2, [r0]
-
- /* Stop searching of an alias was found. */
- cmp r1, r2
- beq found_block_size
-
- /* Advance to the next power of two boundary. */
- mov r1, r1, lsl #1
-
- /* Loop back if the size has not reached 256MB. */
- cmp r1, #0x10000000
- bne check_block_size
-
- /* A full 256MB of memory was found, so return it now. */
- ldr r0, =0x10000000
- ldr r1, =0x00000000
- ldr r2, =0x00000001
- mov pc, lr
-
- /* An alias was found. See if the first block is 128MB in size. */
-found_block_size:
- cmp r1, #0x08000000
-
- /* The first block is 128MB, so there is no further memory. Return it
- * now.
- */
- ldreq r0, =0x08000000
- ldreq r1, =0x00000000
- ldreq r2, =0x00000001
- moveq pc, lr
-
- /* Save the block size, set the block address bits to zero, and
- * initialize the block count to one.
- */
- mov r3, r1
- ldr r4, =0x00000000
- ldr r5, =0x00000001
-
- /* Look for additional blocks of memory by searching for non-aliases. */
-find_blocks:
- /* Store zero back to address zero. It may be overwritten. */
- str r0, [r0]
-
- /* Advance to the next power of two boundary. */
- mov r1, r1, lsl #1
-
- /* Store the offset at the current offset. */
- str r1, [r0, r1]
-
- /* Read back from zero. */
- ldr r2, [r0]
-
- /* See if a non-alias was found. */
- cmp r1, r2
-
- /* If a non-alias was found, then or in the block address bit and
- * multiply the block count by two (since there are two unique
- * blocks, one with this bit zero and one with it one).
- */
- orrne r4, r4, r1
- movne r5, r5, lsl #1
-
- /* Continue searching if there are more address bits to check. */
- cmp r1, #0x08000000
- bne find_blocks
-
- /* Return the block size, address mask, and count. */
- mov r0, r3
- mov r1, r4
- mov r2, r5
-
- /* Return to the caller. */
- mov pc, lr
-
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r6, lr
-
- /* Make sure caches are off and invalidated. */
- ldr r0, =0x00000000
- mcr p15, 0, r0, c1, c0, 0
- nop
- nop
- nop
- nop
- nop
-
- /* Turn off the green LED and turn on the red LED. If the red LED
- * is left on for too long, the external reset circuit described
- * by application note AN258 will cause the system to reset.
- */
- ldr r1, =EP93XX_LED_DATA
- ldr r0, [r1]
- bic r0, r0, #EP93XX_LED_GREEN_ON
- orr r0, r0, #EP93XX_LED_RED_ON
- str r0, [r1]
-
- /* Undo the silly static memory controller programming performed
- * by the boot rom.
- */
- ldr r0, =SMC_BASE
-
- /* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
- ldr r1, =0x0000fbe0
-
- /* Reset EP93XX_OFF_SMCBCR0 */
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR1]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR2]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR3]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR6]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR7]
-
- /* Set the PLL1 and processor clock. */
- ldr r0, =SYSCON_BASE
-#ifdef CONFIG_EDB9301
- /* 332MHz, giving a 166MHz processor clock. */
- ldr r1, = 0x02b49907
-#else
-
-#ifdef CONFIG_EDB93XX_INDUSTRIAL
- /* 384MHz, giving a 196MHz processor clock. */
- ldr r1, =0x02a4bb38
-#else
- /* 400MHz, giving a 200MHz processor clock. */
- ldr r1, =0x02a4e39e
-#endif
-#endif
- str r1, [r0, #SYSCON_OFF_CLKSET1]
-
- nop
- nop
- nop
- nop
- nop
-
- /* Need to make sure that SDRAM is configured correctly before
- * coping the code into it.
- */
-
-#ifdef CONFIG_EDB93XX_SDCS0
- mov r11, #SDRAM_DEVCFG0_BASE
-#endif
-#ifdef CONFIG_EDB93XX_SDCS1
- mov r11, #SDRAM_DEVCFG1_BASE
-#endif
-#ifdef CONFIG_EDB93XX_SDCS2
- mov r11, #SDRAM_DEVCFG2_BASE
-#endif
-#ifdef CONFIG_EDB93XX_SDCS3
- ldr r0, =SYSCON_BASE
- ldr r0, [r0, #SYSCON_OFF_SYSCFG]
- ands r0, r0, #SYSCON_SYSCFG_LASDO
- moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
- movne r11, #SDRAM_DEVCFG3_ASD1_BASE
-#endif
- /* See Table 13-5 in EP93xx datasheet for more info about DRAM
- * register mapping */
-
- /* Try a 32-bit wide configuration of SDRAM. */
- ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
- EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
- EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
- EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
-
- /* Set burst count: 4 and CAS: 2
- * Burst mode [A11:A10]; CAS [A16:A14]
- */
- orr r2, r11, #0x00008800
- bl ep93xx_sdram_config
-
- /* Test the SDRAM. */
- mov r0, r11
- bl ep93xx_sdram_test
- cmp r0, #0x00000000
- beq ep93xx_sdram_done
-
- /* Try a 16-bit wide configuration of SDRAM. */
- ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
- EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
- EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
- EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
- EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
-
- /* Set burst count: 8, CAS: 2, sequential burst
- * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
- * Burst mode [A10:A9]; CAS [A15:A13]
- */
- orr r2, r11, #0x00004600
- bl ep93xx_sdram_config
-
- /* Test the SDRAM. */
- mov r0, r11
- bl ep93xx_sdram_test
- cmp r0, #0x00000000
- beq ep93xx_sdram_done
-
- /* Turn off the red LED. */
- ldr r0, =EP93XX_LED_DATA
- ldr r1, [r0]
- bic r1, r1, #EP93XX_LED_RED_ON
- str r1, [r0]
-
- /* There is no SDRAM so flash the green LED. */
-flash_green:
- orr r1, r1, #EP93XX_LED_GREEN_ON
- str r1, [r0]
- ldr r2, =0x00010000
-flash_green_delay_1:
- subs r2, r2, #1
- bne flash_green_delay_1
- bic r1, r1, #EP93XX_LED_GREEN_ON
- str r1, [r0]
- ldr r2, =0x00010000
-flash_green_delay_2:
- subs r2, r2, #1
- bne flash_green_delay_2
- orr r1, r1, #EP93XX_LED_GREEN_ON
- str r1, [r0]
- ldr r2, =0x00010000
-flash_green_delay_3:
- subs r2, r2, #1
- bne flash_green_delay_3
- bic r1, r1, #EP93XX_LED_GREEN_ON
- str r1, [r0]
- ldr r2, =0x00050000
-flash_green_delay_4:
- subs r2, r2, #1
- bne flash_green_delay_4
- b flash_green
-
-
-ep93xx_sdram_done:
- ldr r1, =EP93XX_LED_DATA
- ldr r0, [r1]
- bic r0, r0, #EP93XX_LED_RED_ON
- str r0, [r1]
-
- /* Determine the size of the SDRAM. */
- mov r0, r11
- bl ep93xx_sdram_size
-
- /* Save the SDRAM characteristics. */
- mov r8, r0
- mov r9, r1
- mov r10, r2
-
- /* Compute total memory size into r1 */
- mul r1, r8, r10
-#ifdef CONFIG_EDB93XX_SDCS0
- ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS1
- ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS2
- ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS3
- ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
-#endif
-
- /* Consider small DRAM size as:
- * < 32Mb for 32bit bus
- * < 64Mb for 16bit bus
- */
- tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
- moveq r1, r1, lsr #1
- cmp r1, #0x02000000
-
-#if defined(CONFIG_EDB9301)
- /* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
- movlt r1, #0x03f0
- movge r1, #0x01e0
-#else
- /* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
- movlt r1, #0x0600
- movge r1, #0x2f0
-#endif
- str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
-
- /* Save the memory configuration information. */
- orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
- stmia r0, {r8-r11}
-
- mov lr, r6
- mov pc, lr
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic EP93xx PLL support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-/*
- * get_board_sys_clk() should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-
-/*
- * return the PLL output frequency
- *
- * PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
- * / (X2IPD + 1) / 2^PS
- */
-static ulong get_PLLCLK(uint32_t *pllreg)
-{
- uint8_t i;
- const uint32_t clkset = readl(pllreg);
- uint64_t rate = get_board_sys_clk();
- rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
- rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
- do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
- for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
- rate >>= 1;
-
- return (ulong)rate;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK(void)
-{
- const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
- const uint32_t clkset1 = readl(&syscon->clkset1);
- const uint8_t fclk_div =
- fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
- const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
-
- return fclk_rate;
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
- const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
- const uint32_t clkset1 = readl(&syscon->clkset1);
- const uint8_t hclk_div =
- hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
- const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
-
- return hclk_rate;
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
- const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
- const uint32_t clkset1 = readl(&syscon->clkset1);
- const uint8_t pclk_div =
- pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
- const ulong pclk_rate = get_HCLK() / pclk_div;
-
- return pclk_rate;
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- ulong uclk_rate;
-
- const uint32_t value = readl(&syscon->pwrcnt);
- if (value & SYSCON_PWRCNT_UART_BAUD)
- uclk_rate = get_board_sys_clk();
- else
- uclk_rate = get_board_sys_clk() / 2;
-
- return uclk_rate;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic EP93xx timer support.
- *
- * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
- * author unknown.
- */
-
-#include <common.h>
-#include <init.h>
-#include <time.h>
-#include <linux/delay.h>
-#include <linux/types.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-#define TIMER_CLKSEL (1 << 3)
-#define TIMER_ENABLE (1 << 7)
-
-#define TIMER_FREQ 508469 /* ticks / second */
-#define TIMER_MAX_VAL 0xFFFFFFFF
-
-static struct ep93xx_timer
-{
- unsigned long long ticks;
- unsigned long last_read;
-} timer;
-
-static inline unsigned long long usecs_to_ticks(unsigned long usecs)
-{
- unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
- do_div(ticks, 1000 * 1000);
-
- return ticks;
-}
-
-static inline void read_timer(void)
-{
- struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
- const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
-
- if (now >= timer.last_read)
- timer.ticks += now - timer.last_read;
- else
- /* an overflow occurred */
- timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
-
- timer.last_read = now;
-}
-
-/*
- * Get the number of ticks (in CONFIG_SYS_HZ resolution)
- */
-unsigned long long get_ticks(void)
-{
- unsigned long long sys_ticks;
-
- read_timer();
-
- sys_ticks = timer.ticks * CONFIG_SYS_HZ;
- do_div(sys_ticks, TIMER_FREQ);
-
- return sys_ticks;
-}
-
-unsigned long get_timer(unsigned long base)
-{
- return get_ticks() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long target;
-
- read_timer();
-
- target = timer.ticks + usecs_to_ticks(usec);
-
- while (timer.ticks < target)
- read_timer();
-}
-
-int timer_init(void)
-{
- struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
-
- /* use timer 3 with 508KHz and free running, not enabled now */
- writel(TIMER_CLKSEL, &timer_regs->timer3.control);
-
- /* set initial timer value */
- writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
-
- /* Enable the timer */
- writel(TIMER_ENABLE | TIMER_CLKSEL,
- &timer_regs->timer3.control);
-
- /* Reset the timer */
- read_timer();
- timer.ticks = 0;
-
- return 0;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-unsigned long get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <config.h>
#include <fsl_wdog.h>
#include <linux/delay.h>
+#include <dm.h>
#include "fsl_epu.h"
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
+
+ return 0;
+}
+#endif
config SYS_FSL_HAS_DP_DDR
bool
+ help
+ Defines the SoC has DP-DDR used for DPAA.
+
+config DP_DDR_CTRL
+ int
+ depends on SYS_FSL_HAS_DP_DDR
+ default 2 if ARCH_LS2080A
+
+config DP_DDR_NUM_CTRLS
+ int
+ depends on SYS_FSL_HAS_DP_DDR
+ default 1 if ARCH_LS2080A
+
+config SYS_DP_DDR_BASE
+ hex
+ depends on SYS_FSL_HAS_DP_DDR
+ default 0x6000000000 if ARCH_LS2080A
+
+config SYS_DP_DDR_BASE_PHY
+ int
+ depends on SYS_FSL_HAS_DP_DDR
+ default 0 if ARCH_LS2080A
+ help
+ DDR controller uses this value as the base address for binding.
+ It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
config SYS_FSL_SRDS_1
bool
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
#endif
#endif
#include <linux/mii.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_misc_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
serdes_misc_init();
return 0;
imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8M) += \
+ imx8mm-data-modul-edm-sbc.dtb \
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-n801x-s.dtb \
imx8mm-kontron-n801x-s-lvds.dtb \
+ imx8mm-mx8menlo.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
imx8mm-venice-gw73xx-0x.dtb \
imx8mm-venice-gw7901.dtb \
imx8mm-venice-gw7902.dtb \
+ imx8mm-venice-gw7903.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
+ imx8mn-bsh-smm-s2.dtb \
+ imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
power-domains = <&pd_dma>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_NONE>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = <SC_R_CAAM_JR1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr2: PD_CAAM_JR2 {
+ reg = <SC_R_CAAM_JR2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr3: PD_CAAM_JR3 {
+ reg = <SC_R_CAAM_JR3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ };
};
i2c0: i2c@5a800000 {
};
};
};
+
+ crypto: caam@0x31400000 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0 0x31400000 0 0x400000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x31400000 0x400000>;
+ fsl,first-jr-index = <2>;
+ fsl,sec-era = <9>;
+
+ sec_jr1: jr1@0x20000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x1000>;
+ interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr1>;
+ status = "disabled";
+ };
+
+ sec_jr2: jr2@30000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x1000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr2>;
+ status = "okay";
+ };
+
+ sec_jr3: jr3@40000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x1000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr3>;
+ status = "okay";
+ };
+ };
};
&A35_0 {
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
&{/imx8qm-pm} {
u-boot,dm-spl;
};
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
wakeup-irq = <349>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_NONE>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = <SC_R_CAAM_JR1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr2: PD_CAAM_JR2 {
+ reg = <SC_R_CAAM_JR2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr3: PD_CAAM_JR3 {
+ reg = <SC_R_CAAM_JR3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ };
};
i2c0: i2c@5a800000 {
power-domains = <&pd_conn_enet1>;
status = "disabled";
};
+
+ crypto: caam@0x31400000 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0 0x31400000 0 0x400000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x31400000 0x400000>;
+ fsl,first-jr-index = <2>;
+ fsl,sec-era = <9>;
+
+ sec_jr1: jr1@0x20000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x1000>;
+ interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr1>;
+ status = "disabled";
+ };
+
+ sec_jr2: jr2@30000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x1000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr2>;
+ status = "okay";
+ };
+
+ sec_jr3: jr3@40000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x1000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr3>;
+ status = "okay";
+ };
+ };
};
&A53_0 {
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
&{/imx8qx-pm} {
u-boot,dm-spl;
};
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor
*/
bus-width = <4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
/*
* Device Tree Include file for NXP Layerscape-1043A family SoC.
*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
+ * Copyright 2021 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
dr_mode = "host";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
status = "disabled";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <0 139 0x4>; /* Level high type */
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 140 0x4>; /* Level high type */
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 141 0x4>; /* Level high type */
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 142 0x4>; /* Level high type */
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 143 0x4>; /* Level high type */
+ };
+ };
+
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc", "simple-mfd";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
/*
* NXP lx2160a SOC common device tree source
*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
*/
clock-output-names = "sysclk";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
clockgen: clocking@1300000 {
compatible = "fsl,ls2080a-clockgen";
reg = <0 0x1300000 0 0xa0000>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+&aips1 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-pre-reloc;
+};
+
+&soc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+};
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
status = "disabled";
};
- bus@2000000 { /* AIPS1 */
+ aips1: bus@2000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
#include "imx6ull.dtsi"
/ {
+ /* Ethernet aliases to ensure correct MAC addresses */
+ aliases {
+ ethernet0 = &fec2;
+ ethernet1 = &fec1;
+ };
+
chosen {
stdout-path = &uart1;
};
regulator-max-microvolt = <5000000>;
};
- reg_sd1_vmmc: regulator-sd1-vmmc {
+ reg_sd1_vqmmc: regulator-sd1-vqmmc {
compatible = "regulator-gpio";
- gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_reg_sd>;
regulator-always-on;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
vin-supply = <®_5v0>;
};
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed-clock";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "eth_phy";
+ regulator-type = "voltage";
+ vin-supply = <®_module_3v3>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ startup-delay-us = <150000>;
+ };
};
&adc1 {
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
+ phy-supply = <®_eth_phy>;
status = "okay";
mdio {
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
+ bus-width = <4>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
+ disable-wp;
+ no-1-8-v;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- vmmc-supply = <®_sd1_vmmc>;
+ vqmmc-supply = <®_sd1_vqmmc>;
status = "okay";
};
pinctrl_usdhc1: usdhc1-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
stdout-path = &uart1;
};
};
+
+&aips3 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-pre-reloc;
+};
+
+&soc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+};
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
};
};
+ crypto: crypto@40240000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40240000 0x10000>;
+ ranges = <0 0x40240000 0x10000>;
+ clocks = <&clks IMX7ULP_CLK_CAAM>,
+ <&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
+ clock-names = "aclk", "ipg";
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
stdout-path = &uart3;
};
+ aliases {
+ eeprom0 = &i2c_eeprom0;
+ eeprom1 = &i2c_eeprom1;
+ };
+
reg_vusb_5v: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VUSB_5V";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- eeprom@54 {
+ i2c_eeprom0: eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
pagesize = <16>;
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+ i2c_eeprom1: eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
rtc@69 {
compatible = "abracon,ab1805";
reg = <0x69>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mm-u-boot.dtsi"
+
+/ {
+ aliases {
+ eeprom0 = &eeprom;
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc2; /* MicroSD */
+ };
+
+ config {
+ dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&buck4_reg {
+ u-boot,dm-spl;
+};
+
+&buck5_reg {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_hog_sbc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pmic {
+ u-boot,dm-spl;
+
+ regulators {
+ u-boot,dm-spl;
+ };
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&usbotg1 {
+ dr_mode = "peripheral";
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/net/qca-ar803x.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Data Modul i.MX8M Mini eDM SBC";
+ compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
+
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ /* There are 1/2/4 GiB options, adjusted by bootloader. */
+ reg = <0x0 0x40000000 0 0x40000000>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel_backlight>;
+ brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
+ default-brightness-level = <7>;
+ enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm1 0 5000000>;
+ /* Disabled by default, unless display board plugged in. */
+ status = "disabled";
+ };
+
+ clk_xtal25: clk-xtal25 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ panel: panel {
+ backlight = <&backlight>;
+ power-supply = <®_panel_vcc>;
+ /* Disabled by default, unless display board plugged in. */
+ status = "disabled";
+ };
+
+ reg_panel_vcc: regulator-panel-vcc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel_vcc_reg>;
+ regulator-name = "PANEL_VCC";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 6 0>;
+ enable-active-high;
+ /* Disabled by default, unless display board plugged in. */
+ status = "disabled";
+ };
+
+ reg_usdhc2_vcc: regulator-usdhc2-vcc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
+ regulator-name = "V_3V3_SD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 0>;
+ enable-active-high;
+ };
+
+ watchdog-gpio {
+ /* TPS3813 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_watchdog_gpio>;
+ compatible = "linux,wdt-gpio";
+ always-enabled;
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ hw_algo = "level";
+ /* Reset triggers in 2..3 seconds */
+ hw_margin_ms = <1500>;
+ /* Disabled by default */
+ status = "disabled";
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 { /* W25Q128FVSI */
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+};
+
+&ecspi2 { /* Feature connector SPI */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ /* Disabled by default, unless feature board plugged in. */
+ status = "disabled";
+};
+
+&ecspi3 { /* Display connector SPI */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ /* Disabled by default, unless display board plugged in. */
+ status = "disabled";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&fec1_phy>;
+ phy-supply = <&buck4_reg>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Atheros AR8031 PHY */
+ fec1_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ /*
+ * Dedicated ENET_WOL# signal is unused, the PHY
+ * can wake the SoC up via INT signal as well.
+ */
+ interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ qca,clk-out-frequency = <125000000>;
+ qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+ qca,keep-pll-enabled;
+ vddio-supply = <&vddio>;
+
+ vddio: vddio-regulator {
+ regulator-name = "VDDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddh: vddh-regulator {
+ regulator-name = "VDDH";
+ };
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
+ "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
+ "WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
+ "USB1_OTG_ID_3V3", "ENET_WOL#",
+ "", "", "", "ENET_INT#",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
+ "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
+ "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
+ "MEMCFG0", "WDOG_EN",
+ "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
+ "", "", "", "",
+ "", "", "", "SD2_RESET#", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
+ "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
+ "CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
+ "", "", "", "",
+ "", "", "", "M2-B_WAKE_WWAN_1V8#",
+ "M2-B_RESET_1V8#", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
+ "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
+ "BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
+ "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
+ "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
+ "NC20", "", "", "",
+ "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
+ "DIS_USB_DN2", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
+ "GPIO5_IO04", "", "", "",
+ "", "SPI1_CS#", "", "",
+ "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
+ "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
+ "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
+ "", "SPI3_CS#", "", "", "", "", "", "";
+};
+
+&i2c1 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic: pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ rohm,reset-snvs-powered;
+
+ /*
+ * i.MX 8M Mini Data Sheet for Consumer Products
+ * 3.1.3 Operating ranges
+ * MIMX8MM4DVTLZAA
+ */
+ regulators {
+ /* VDD_SOC */
+ buck1_reg: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ /* VDD_ARM */
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <950000>;
+ };
+
+ /* VDD_DRAM, BUCK5 */
+ buck3_reg: BUCK3 {
+ regulator-name = "buck3";
+ /* 1.5 GHz DDR bus clock */
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* 3V3_VDD, BUCK6 */
+ buck4_reg: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* 1V8_VDD, BUCK7 */
+ buck5_reg: BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* 1V1_NVCC_DRAM, BUCK8 */
+ buck6_reg: BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* 1V8_NVCC_SNVS */
+ ldo1_reg: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* 0V8_VDD_SNVS */
+ ldo2_reg: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* 1V8_VDDA */
+ ldo3_reg: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* 0V9_VDD_PHY */
+ ldo4_reg: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* 1V2_VDD_PHY */
+ ldo6_reg: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <320000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ usb-hub@2c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_hub>;
+ compatible = "microchip,usb2514bi";
+ reg = <0x2c>;
+ individual-port-switching;
+ reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ self-powered;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ rtc: rtc@68 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ compatible = "st,m41t62";
+ reg = <0x68>;
+ interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pcieclk: clk@6a {
+ compatible = "renesas,9fgv0241";
+ reg = <0x6a>;
+ clocks = <&clk_xtal25>;
+ #clock-cells = <1>;
+ };
+};
+
+&i2c3 { /* Display connector I2C */
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <320000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c4 { /* Feature connector I2C */
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <320000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
+ <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
+ <&pinctrl_panel_expansion>;
+
+ pinctrl_ecspi1: ecspi1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44
+ MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44
+ MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44
+ MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40
+ >;
+ };
+
+ pinctrl_fec1: fec1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ /* ENET_RST# */
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6
+ /* ENET_WOL# */
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090
+ /* ENET_INT# */
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090
+ >;
+ };
+
+ pinctrl_hog_feature: hog-feature-grp {
+ fsl,pins = <
+ /* GPIO4_IO27 */
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006
+ /* GPIO5_IO03 */
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
+ /* GPIO5_IO04 */
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
+
+ /* CAN_INT# */
+ MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
+ /* CAN_RST# */
+ MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26
+ >;
+ };
+
+ pinctrl_hog_panel: hog-panel-grp {
+ fsl,pins = <
+ /* GRAPHICS_GPIO0_1V8 */
+ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26
+ >;
+ };
+
+ pinctrl_hog_misc: hog-misc-grp {
+ fsl,pins = <
+ /* PG_V_IN_VAR# */
+ MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000
+ /* CSI_PD_1V8 */
+ MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0
+ /* CSI_RESET_1V8# */
+ MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0
+
+ /* DIS_USB_DN1 */
+ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0
+ /* DIS_USB_DN2 */
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0
+
+ /* EEPROM_WP_1V8# */
+ MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100
+ /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
+ /* GRAPHICS_PRSNT_1V8# */
+ MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000
+
+ /* CLK_CCM_CLKO1_3V3 */
+ MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10
+ >;
+ };
+
+ pinctrl_hog_sbc: hog-sbc-grp {
+ fsl,pins = <
+ /* MEMCFG[0..2] straps */
+ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140
+ MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140
+ MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140
+
+ /* BOOT_CFG[0..15] straps */
+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000
+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000
+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000
+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000
+ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000
+ MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000
+ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000
+ MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000
+
+ /* Not connected pins */
+ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0
+ MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0
+ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0
+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0
+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84
+ >;
+ };
+
+ pinctrl_i2c2: i2c2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84
+ >;
+ };
+
+ pinctrl_i2c3: i2c3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84
+ >;
+ };
+
+ pinctrl_i2c4: i2c4-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84
+ MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84
+ >;
+ };
+
+ pinctrl_panel_backlight: panel-backlight-grp {
+ fsl,pins = <
+ /* BL_ENABLE_1V8 */
+ MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104
+ >;
+ };
+
+ pinctrl_panel_expansion: panel-expansion-grp {
+ fsl,pins = <
+ /* DSI_RESET_1V8# */
+ MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2
+ /* DSI_IRQ_1V8# */
+ MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090
+ >;
+ };
+
+ pinctrl_panel_vcc_reg: panel-vcc-grp {
+ fsl,pins = <
+ /* TFT_ENABLE_1V8 */
+ MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104
+ >;
+ };
+
+ pinctrl_panel_pwm: panel-pwm-grp {
+ fsl,pins = <
+ /* BL_PWM_3V3 */
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12
+ >;
+ };
+
+ pinctrl_pcie0: pcie-grp {
+ fsl,pins = <
+ /* M2-B_RESET_1V8# */
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102
+ /* M2-B_PCIE_RST# */
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2
+ /* M2-B_FULL_CARD_PWROFF_1V8# */
+ MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102
+ /* M2-B_W_DISABLE1_WWAN_1V8# */
+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102
+ /* M2-B_W_DISABLE2_GPS_1V8# */
+ MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102
+ /* CLK_M2_32K768 */
+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14
+ /* M2-B_WAKE_WWAN_1V8# */
+ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140
+ /* M2-B_PCIE_WAKE# */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140
+ /* M2-B_PCIE_CLKREQ# */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140
+ >;
+ };
+
+ pinctrl_pmic: pmic-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090
+ >;
+ };
+
+ pinctrl_rtc: rtc-grp {
+ fsl,pins = <
+ /* RTC_IRQ# */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090
+ >;
+ };
+
+ pinctrl_sai5: sai5-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100
+ MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0
+ MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100
+ MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100
+ MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90
+ MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50
+ MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50
+ >;
+ };
+
+ pinctrl_uart2: uart2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50
+ MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90
+ MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50
+ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90
+ >;
+ };
+
+ pinctrl_uart3: uart3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
+ >;
+ };
+
+ pinctrl_uart4: uart4-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40
+ >;
+ };
+
+ pinctrl_usb_hub: usb-hub-grp {
+ fsl,pins = <
+ /* USBHUB_RESET# */
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4
+ >;
+ };
+
+ pinctrl_usb_otg1: usb-otg1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000
+ MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090
+ >;
+ };
+
+ pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
+ MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
+ MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
+ MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
+ >;
+ };
+
+ pinctrl_watchdog_gpio: watchdog-gpio-grp {
+ fsl,pins = <
+ /* WDOG_B# */
+ MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26
+ /* WDOG_EN -- ungate WDT RESET# signal propagation */
+ MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6
+ /* WDOG_KICK# / WDI */
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26
+ >;
+ };
+};
+
+&pcie_phy {
+ fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,tx-deemph-gen1 = <0x2d>;
+ fsl,tx-deemph-gen2 = <0xf>;
+ clocks = <&pcieclk 0>;
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&pcieclk 0>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel_pwm>;
+ /* Disabled by default, unless display board plugged in. */
+ status = "disabled";
+};
+
+&sai5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai5>;
+ fsl,sai-mclk-direction-output;
+ /* Input into codec PLL */
+ assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
+ assigned-clock-rates = <22579200>;
+ /* Disabled by default, unless display board plugged in. */
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "disabled";
+};
+
+&uart3 { /* A53 Debug */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart4 { /* M4 Debug */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ /* UART4 is reserved for CM and RDC blocks CA access to UART4. */
+ status = "disabled";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc2 { /* MicroSD */
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vcc>;
+ status = "okay";
+};
+
+&usdhc3 { /* eMMC */
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ vmmc-supply = <&buck4_reg>;
+ vqmmc-supply = <&buck5_reg>;
+ status = "okay";
+};
+
+&wdog1 {
+ status = "okay";
+};
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mm-u-boot.dtsi"
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
enable-active-high;
};
+ backlight: backlight {
+ status = "disabled";
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <250>;
+ };
+
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
+ >;
+ };
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021-2022 Marek Vasut <marex@denx.de>
+ */
+#include "imx8mm-verdin-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ aliases {
+ /delete-property/ eeprom1;
+ /delete-property/ eeprom2;
+ usbphy0 = &usbphynop1;
+ usbphy1 = &usbphynop2;
+ };
+};
+
+&i2c4 {
+ /delete-node/ codec@1a;
+};
+
+&pinctrl_uart1 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&uart1 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021-2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mm-verdin.dts"
+
+/ {
+ model = "MENLO MX8MM EMBEDDED DEVICE";
+ compatible = "menlo,mx8menlo",
+ "toradex,verdin-imx8mm",
+ "fsl,imx8mm";
+
+ /delete-node/ gpio-keys;
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+
+ user1 {
+ label = "TestLed601";
+ gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ user2 {
+ label = "TestLed602";
+ gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ beeper {
+ compatible = "gpio-beeper";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_beeper>;
+ gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ecspi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ /* CAN controller on the baseboard */
+ canfd: can@0 {
+ compatible = "microchip,mcp2518fd";
+ clocks = <&clk20m>;
+ gpio-controller;
+ interrupt-parent = <&gpio1>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ reg = <0>;
+ spi-max-frequency = <2000000>;
+ status = "okay";
+ };
+
+};
+
+&ecspi2 {
+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+};
+
+ðphy0 {
+ max-speed = <100>;
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&flexspi {
+ status = "okay";
+
+ flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <66000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "DISP_reset", "KBD_intI",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio4 {
+ /*
+ * CPLD_D[n] is ARM_CPLD[n] in schematic
+ * CPLD_int is SA_INTERRUPT in schematic
+ * CPLD_reset is RESET_SOFT in schematic
+ */
+ gpio-line-names =
+ "CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
+ "", "CPLD_D[0]", "", "",
+ "", "", "", "CPLD_D[2]",
+ "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
+ "CPLD_D[7]", "", "", "",
+ "", "", "", "",
+ "", "", "", "KBD_intK",
+ "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio_expander_21 {
+ status = "okay";
+};
+
+&i2c1 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <100000>;
+};
+
+&i2c2 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <100000>;
+};
+
+&i2c3 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c4 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <100000>;
+ /delete-node/ bridge@2c;
+ /delete-node/ hwmon@40;
+ /delete-node/ hdmi@48;
+ /delete-node/ touch@4a;
+ /delete-node/ hwmontemp@4f;
+ /delete-node/ eeprom@50;
+ /delete-node/ eeprom@57;
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
+ <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
+
+ pinctrl_beeper: beepergrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
+ MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
+ >;
+ };
+
+ pinctrl_uart4_rts: uart4rtsgrp {
+ fsl,pins = <
+ /* SODIMM 222 */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
+ >;
+ };
+};
+
+&pinctrl_gpio1 {
+ fsl,pins = <
+ /* SODIMM 206 */
+ MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
+ >;
+};
+
+&pinctrl_gpio_hog1 {
+ fsl,pins = <
+ /* SODIMM 88 */
+ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
+ /* CPLD_int */
+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
+ /* CPLD_reset */
+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
+ /* SODIMM 94 */
+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
+ /* SODIMM 96 */
+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
+ /* CPLD_D[7] */
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
+ /* CPLD_D[6] */
+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
+ /* CPLD_D[5] */
+ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
+ /* CPLD_D[4] */
+ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
+ /* CPLD_D[3] */
+ MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
+ /* CPLD_D[2] */
+ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
+ /* CPLD_D[1] */
+ MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
+ /* CPLD_D[0] */
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
+ /* KBD_intK */
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
+ /* DISP_reset */
+ MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
+ /* KBD_intI */
+ MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
+ /* SODIMM 46 */
+ MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
+ >;
+};
+
+&pinctrl_uart1 {
+ fsl,pins = <
+ /* SODIMM 149 */
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
+ /* SODIMM 147 */
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
+ /* SODIMM 210 */
+ MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
+ /* SODIMM 212 */
+ MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
+ >;
+};
+
+®_usb_otg1_vbus {
+ /delete-property/ enable-active-high;
+ gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
+};
+
+®_usb_otg2_vbus {
+ /delete-property/ enable-active-high;
+ gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
+};
+
+&sai2 {
+ status = "disabled";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
+ linux,rs485-enabled-at-boot-time;
+ rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "gadget";
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "okay";
+};
atf-blob {
filename = "bl31.bin";
- type = "blob-ext";
+ type = "atf-bl31";
};
};
gw,voltage-divider-ohms = <10000 10000>;
};
+ channel@9c {
+ gw,mode = <2>;
+ reg = <0x9c>;
+ label = "vdd_5p0";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include "imx8mm-venice-u-boot.dtsi"
+
+&fec1 {
+ phy-reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <300>;
+};
+
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Gateworks Venice GW7903 i.MX8MM board";
+ compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
+
+ aliases {
+ ethernet0 = &fec1;
+ usb0 = &usbotg1;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key_erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led01_red";
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led01_grn";
+ gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led02_red";
+ gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-3 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led02_grn";
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-4 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led03_red";
+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-5 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led03_grn";
+ gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-6 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led04_red";
+ gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-7 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led04_grn";
+ gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-8 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led05_red";
+ gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-9 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led05_grn";
+ gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-a {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led06_red";
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led06_grn";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2500>;
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
+ "dig1_out#", "dig1_in", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
+ "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ pinctrl-0 = <&pinctrl_gsc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ gw,voltage-offset-microvolt = <700000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vdd_5p0";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_0p9";
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_soc";
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_arm";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_1p8";
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_dram";
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+ };
+
+ gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ /* vdd_soc: 0.805-0.900V (typ=0.8V) */
+ BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ /* vdd_arm: 0.805-1.0V (typ=0.9V) */
+ buck2: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
+ BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_3p3 */
+ BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_1p8 */
+ BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_dram */
+ BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* nvcc_snvs_1p8 */
+ LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_snvs_0p8 */
+ LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdda_1p8 */
+ LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcie0_refclk>;
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ status = "okay";
+};
+
+/* off-board RS232/RS485/RS422 */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
+ MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
+ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
+ MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
+ MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
+ MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
+ MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
+ MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
+ >;
+ };
+
+ pinctrl_gsc: gscgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
+ MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
+ MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
+ MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
+ >;
+ };
+
+ pinctrl_pcie0: pciegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
+ MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+#include "imx8mn.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ fec_supply: fec_supply_en {
+ compatible = "regulator-fixed";
+ regulator-name = "tja1101_en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&buck4_reg>;
+ enable-active-high;
+ };
+
+ usdhc2_pwrseq: usdhc2_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
+ reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_espi2>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ phy-supply = <&fec_supply>;
+ phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <20>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ bd71847: pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ buck1_reg: BUCK1 {
+ /* PMIC_BUCK1 - VDD_SOC */
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ /* PMIC_BUCK2 - VDD_ARM */
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck3_reg: BUCK3 {
+ /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ /* PMIC_BUCK6 - VDD_3V3 */
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ /* PMIC_BUCK7 - VDD_1V8 */
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ /* PMIC_BUCK8 - NVCC_DRAM */
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ /* PMIC_LDO1 - NVCC_SNVS_1V8 */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ /* PMIC_LDO2 - VDD_SNVS_0V8 */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ /* PMIC_LDO3 - VDDA_1V8 */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ /* PMIC_LDO4 - VDD_MIPI_0V9 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ /* PMIC_LDO6 - VDD_MIPI_1V2 */
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MN_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bluetooth>;
+ shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ };
+};
+
+/* Console */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "peripheral";
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ mmc-pwrseq = <&usdhc2_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wlan>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_espi2: espi2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
+ MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
+ MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
+ MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2
+ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2
+ MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
+ MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
+ >;
+ };
+
+ pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6
+ >;
+ };
+
+ pinctrl_wlan: wlangrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
+ MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
+ MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
+ MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
+ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
+ MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
+ MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
+ MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
+ >;
+ };
+
+ pinctrl_bluetooth: bluetoothgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
+ MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
+ MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
+ MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
+ MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
+ MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
+ MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
+ MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&aips1 {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&aips4 {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&osc_24m {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart4 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
+&uart4 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ 1d-imem {
+ filename = "ddr3_imem_1d.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 1d_dmem {
+ filename = "ddr3_dmem_1d.bin";
+ size = <0x4000>;
+ type = "blob-ext";
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_SYS_TEXT_BASE>;
+ type = "standalone";
+
+ uboot_blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
+ };
+
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x960000>;
+ load = <0x960000>;
+ type = "firmware";
+
+ atf_blob {
+ filename = "bl31.bin";
+ type = "atf-bl31";
+ };
+ };
+
+ binman_fip: fip {
+ arch = "arm64";
+ compression = "none";
+ description = "Trusted Firmware FIP";
+ load = <0x40310000>;
+ type = "firmware";
+ };
+
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
+
+ uboot_fdt_blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
+ };
+ };
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+
+ binman_configuration: @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
+ loadables = "atf";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl {
+ filename = "spl.bin";
+ offset = <0x0>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.itb";
+ offset = <0x58000>;
+ type = "blob-ext";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+#include "imx8mn-bsh-smm-s2-u-boot-common.dtsi"
+
+&pinctrl_gpmi_nand {
+ u-boot,dm-spl;
+};
+
+&gpmi {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mn-bsh-smm-s2-common.dtsi"
+
+/ {
+ model = "BSH SMM S2";
+ compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x10000000>;
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpmi_nand: gpmi-nand {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
+ MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096
+ MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096
+ MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096
+ MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096
+ MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096
+ MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096
+ MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096
+ MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096
+ MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096
+ MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096
+ MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096
+ MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056
+ MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096
+ MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+#include "imx8mn-bsh-smm-s2-u-boot-common.dtsi"
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mn-bsh-smm-s2-common.dtsi"
+
+/ {
+ model = "BSH SMM S2 PRO";
+ compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ };
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0
+ MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0
+ MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0
+ MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0
+ MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0
+ MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4
+ MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4
+ MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4
+ MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4
+ MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4
+ MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6
+ MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6
+ MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6
+ MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6
+ MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6
+ MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096
+ >;
+ };
+};
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
/ {
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
- phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
fsl,magic-packet;
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ qca,disable-smarteee;
+ vddio-supply = <&vddio>;
+
+ vddio: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
};
};
};
atf_blob {
filename = "bl31.bin";
- type = "blob-ext";
+ type = "atf-bl31";
};
};
gw,voltage-divider-ohms = <10000 10000>;
};
+ channel@9c {
+ gw,mode = <2>;
+ reg = <0x9c>;
+ label = "vdd_5p0";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mp-u-boot.dtsi"
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&i2c1 {
u-boot,dm-spl;
};
};
&eqos {
- compatible = "fsl,imx-eqos";
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
load = <0x970000>;
entry = <0x970000>;
- atf_blob: blob-ext {
+ atf_blob: atf-blob {
filename = "bl31.bin";
+ type = "atf-bl31";
};
};
};
&eqos {
- compatible = "fsl,imx-eqos";
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
status = "disabled";
};
+ flexspi: spi@30bb0000 {
+ compatible = "nxp,imx8mp-fspi";
+ reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
+ <&clk IMX8MP_CLK_QSPI_ROOT>;
+ clock-names = "fspi_en", "fspi";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30bd0000 0x10000>;
u-boot,dm-spl;
};
+&anatop {
+ u-boot,dm-spl;
+};
+
&clks {
u-boot,dm-spl;
};
/dts-v1/;
#include "imxrt1020.dtsi"
#include "imxrt1020-evk-u-boot.dtsi"
-#include <dt-bindings/pinctrl/pins-imxrt1020.h>
+#include "imxrt1020-pinfunc.h"
/ {
model = "NXP IMXRT1020-evk board";
fsl,mux_mask = <0x7>;
};
+ anatop: anatop@400d8000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x400d8000 0x4000>;
+ };
+
clks: ccm@400fc000 {
compatible = "fsl,imxrt1020-ccm";
reg = <0x400fc000 0x4000>;
u-boot,dm-spl;
};
+&anatop {
+ u-boot,dm-spl;
+};
+
&clks {
u-boot,dm-spl;
};
/dts-v1/;
#include "imxrt1050.dtsi"
#include "imxrt1050-evk-u-boot.dtsi"
-#include <dt-bindings/pinctrl/pins-imxrt1050.h>
+#include "imxrt1050-pinfunc.h"
/ {
model = "NXP IMXRT1050-evk board";
fsl,mux_mask = <0x7>;
};
+ anatop: anatop@400d8000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x400d8000 0x4000>;
+ };
+
clks: ccm@400fc000 {
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
memorycontroller: memorycontroller@f300000 {
compatible = "ti,am64-ddrss";
reg = <0x00 0x0f308000 0x00 0x4000>,
- <0x00 0x43014000 0x00 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x00 0x43014000 0x00 0x100>,
+ <0x00 0x0f300000 0x00 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
<&k3_pds 55 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 138 0>, <&k3_clks 16 4>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
+ <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
compatible = "ti,omap5430-timer";
reg = <0x0 0x2400000 0x0 0x80>;
ti,timer-alwon;
- clock-frequency = <250000000>;
+ clock-frequency = <200000000>;
u-boot,dm-spl;
};
};
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ u-boot,dm-spl;
};
a53_0: a53@0 {
};
};
+&cbass_main {
+ main_esm: esm@420000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x420000 0x0 0x1000>;
+ ti,esm-pins = <160>, <161>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_mcu {
+ u-boot,dm-spl;
+ mcu_esm: esm@4100000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x4100000 0x0 0x1000>;
+ ti,esm-pins = <0>, <1>;
+ u-boot,dm-spl;
+ };
+};
+
&main_pmx0 {
u-boot,dm-spl;
main_uart0_pins_default: main-uart0-pins-default {
};
};
+&cbass_main {
+ main_esm: esm@420000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x420000 0x0 0x1000>;
+ ti,esm-pins = <160>, <161>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_mcu {
+ u-boot,dm-spl;
+ mcu_esm: esm@4100000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x4100000 0x0 0x1000>;
+ ti,esm-pins = <0>, <1>;
+ u-boot,dm-spl;
+ };
+};
+
&main_pmx0 {
u-boot,dm-spl;
main_uart0_pins_default: main-uart0-pins-default {
compatible = "ti,omap5430-timer";
reg = <0x0 0x2400000 0x0 0x80>;
ti,timer-alwon;
- clock-frequency = <250000000>;
+ clock-frequency = <200000000>;
u-boot,dm-spl;
};
};
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
- clock-frequency = <25000000>;
+ clock-frequency = <250000000>;
u-boot,dm-spl;
};
* Freescale ls1021a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include "skeleton.dtsi"
big-endian;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1700000 0x100000>;
+ ranges = <0x0 0x1700000 0x100000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;
/* DEBUG UART */
qup_uart9: qup-uart9-default {
- pinmux {
- pins = "GPIO_4", "GPIO_5";
- function = "qup9";
- };
+ pins = "GPIO_4", "GPIO_5";
+ function = "gpio";
};
};
/
{
+ framebuffer@9D400000 {
+ u-boot,dm-pre-reloc;
+ };
soc {
u-boot,dm-pre-reloc;
+ serial@a84000 {
+ u-boot,dm-pre-reloc;
+ };
gcc {
clock-controller@100000 {
u-boot,dm-pre-reloc;
};
- serial@0xa84000 {
- u-boot,dm-pre-reloc;
- };
gpio_north@3900000 {
u-boot,dm-pre-reloc;
};
method = "smc";
};
+ framebuffer: framebuffer@9D400000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9D400000 0 (2960 * 1440 * 4)>;//2400000
+ width = <1440>;
+ height = <2960>;
+ stride = <(1440 * 4)>;
+ format = "a8r8g8b8";
+ };
+
soc: soc {
- serial@0xa84000 {
- status = "ok";
+ serial@a84000 {
+ status = "okay";
};
pinctrl@3900000 {
/ {
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
+
+ aliases {
+ ethernet0 = &emac;
+ };
};
&ehci0 {
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
};
sdhci1: mmc@ff170000 {
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
};
smmu: iommu@fd800000 {
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Cirrus Logic EP93xx register definitions.
- *
- * Copyright (C) 2013
- * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (C) 2009
- * Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006
- * Dominic Rath <Dominic.Rath@gmx.de>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
- *
- * Copyright (C) 2004 Ray Lehtiniemi
- * Copyright (C) 2003 Cirrus Logic, Inc
- * Copyright (C) 1999 ARM Limited.
- */
-
-#define EP93XX_AHB_BASE 0x80000000
-#define EP93XX_APB_BASE 0x80800000
-
-/*
- * 0x80000000 - 0x8000FFFF: DMA
- */
-#define DMA_OFFSET 0x000000
-#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct dma_channel {
- uint32_t control;
- uint32_t interrupt;
- uint32_t ppalloc;
- uint32_t status;
- uint32_t reserved0;
- uint32_t remain;
- uint32_t reserved1[2];
- uint32_t maxcnt0;
- uint32_t base0;
- uint32_t current0;
- uint32_t reserved2;
- uint32_t maxcnt1;
- uint32_t base1;
- uint32_t current1;
- uint32_t reserved3;
-};
-
-struct dma_regs {
- struct dma_channel m2p_channel_0;
- struct dma_channel m2p_channel_1;
- struct dma_channel m2p_channel_2;
- struct dma_channel m2p_channel_3;
- struct dma_channel m2m_channel_0;
- struct dma_channel m2m_channel_1;
- struct dma_channel reserved0[2];
- struct dma_channel m2p_channel_5;
- struct dma_channel m2p_channel_4;
- struct dma_channel m2p_channel_7;
- struct dma_channel m2p_channel_6;
- struct dma_channel m2p_channel_9;
- struct dma_channel m2p_channel_8;
- uint32_t channel_arbitration;
- uint32_t reserved[15];
- uint32_t global_interrupt;
-};
-#endif
-
-/*
- * 0x80010000 - 0x8001FFFF: Ethernet MAC
- */
-#define MAC_OFFSET 0x010000
-#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct mac_queue {
- uint32_t badd;
- union { /* deal with half-word aligned registers */
- uint32_t blen;
- union {
- uint16_t filler;
- uint16_t curlen;
- };
- };
- uint32_t curadd;
-};
-
-struct mac_regs {
- uint32_t rxctl;
- uint32_t txctl;
- uint32_t testctl;
- uint32_t reserved0;
- uint32_t miicmd;
- uint32_t miidata;
- uint32_t miists;
- uint32_t reserved1;
- uint32_t selfctl;
- uint32_t inten;
- uint32_t intstsp;
- uint32_t intstsc;
- uint32_t reserved2[2];
- uint32_t diagad;
- uint32_t diagdata;
- uint32_t gt;
- uint32_t fct;
- uint32_t fcf;
- uint32_t afp;
- union {
- struct {
- uint32_t indad;
- uint32_t indad_upper;
- };
- uint32_t hashtbl;
- };
- uint32_t reserved3[2];
- uint32_t giintsts;
- uint32_t giintmsk;
- uint32_t giintrosts;
- uint32_t giintfrc;
- uint32_t txcollcnt;
- uint32_t rxmissnct;
- uint32_t rxruntcnt;
- uint32_t reserved4;
- uint32_t bmctl;
- uint32_t bmsts;
- uint32_t rxbca;
- uint32_t reserved5;
- struct mac_queue rxdq;
- uint32_t rxdqenq;
- struct mac_queue rxstsq;
- uint32_t rxstsqenq;
- struct mac_queue txdq;
- uint32_t txdqenq;
- struct mac_queue txstsq;
- uint32_t reserved6;
- uint32_t rxbufthrshld;
- uint32_t txbufthrshld;
- uint32_t rxststhrshld;
- uint32_t txststhrshld;
- uint32_t rxdthrshld;
- uint32_t txdthrshld;
- uint32_t maxfrmlen;
- uint32_t maxhdrlen;
-};
-#endif
-
-#define SELFCTL_RWP (1 << 7)
-#define SELFCTL_GPO0 (1 << 5)
-#define SELFCTL_PUWE (1 << 4)
-#define SELFCTL_PDWE (1 << 3)
-#define SELFCTL_MIIL (1 << 2)
-#define SELFCTL_RESET (1 << 0)
-
-#define INTSTS_RWI (1 << 30)
-#define INTSTS_RXMI (1 << 29)
-#define INTSTS_RXBI (1 << 28)
-#define INTSTS_RXSQI (1 << 27)
-#define INTSTS_TXLEI (1 << 26)
-#define INTSTS_ECIE (1 << 25)
-#define INTSTS_TXUHI (1 << 24)
-#define INTSTS_MOI (1 << 18)
-#define INTSTS_TXCOI (1 << 17)
-#define INTSTS_RXROI (1 << 16)
-#define INTSTS_MIII (1 << 12)
-#define INTSTS_PHYI (1 << 11)
-#define INTSTS_TI (1 << 10)
-#define INTSTS_AHBE (1 << 8)
-#define INTSTS_OTHER (1 << 4)
-#define INTSTS_TXSQ (1 << 3)
-#define INTSTS_RXSQ (1 << 2)
-
-#define BMCTL_MT (1 << 13)
-#define BMCTL_TT (1 << 12)
-#define BMCTL_UNH (1 << 11)
-#define BMCTL_TXCHR (1 << 10)
-#define BMCTL_TXDIS (1 << 9)
-#define BMCTL_TXEN (1 << 8)
-#define BMCTL_EH2 (1 << 6)
-#define BMCTL_EH1 (1 << 5)
-#define BMCTL_EEOB (1 << 4)
-#define BMCTL_RXCHR (1 << 2)
-#define BMCTL_RXDIS (1 << 1)
-#define BMCTL_RXEN (1 << 0)
-
-#define BMSTS_TXACT (1 << 7)
-#define BMSTS_TP (1 << 4)
-#define BMSTS_RXACT (1 << 3)
-#define BMSTS_QID_MASK 0x07
-#define BMSTS_QID_RXDATA 0x00
-#define BMSTS_QID_TXDATA 0x01
-#define BMSTS_QID_RXSTS 0x02
-#define BMSTS_QID_TXSTS 0x03
-#define BMSTS_QID_RXDESC 0x04
-#define BMSTS_QID_TXDESC 0x05
-
-#define AFP_MASK 0x07
-#define AFP_IAPRIMARY 0x00
-#define AFP_IASECONDARY1 0x01
-#define AFP_IASECONDARY2 0x02
-#define AFP_IASECONDARY3 0x03
-#define AFP_TX 0x06
-#define AFP_HASH 0x07
-
-#define RXCTL_PAUSEA (1 << 20)
-#define RXCTL_RXFCE1 (1 << 19)
-#define RXCTL_RXFCE0 (1 << 18)
-#define RXCTL_BCRC (1 << 17)
-#define RXCTL_SRXON (1 << 16)
-#define RXCTL_RCRCA (1 << 13)
-#define RXCTL_RA (1 << 12)
-#define RXCTL_PA (1 << 11)
-#define RXCTL_BA (1 << 10)
-#define RXCTL_MA (1 << 9)
-#define RXCTL_IAHA (1 << 8)
-#define RXCTL_IA3 (1 << 3)
-#define RXCTL_IA2 (1 << 2)
-#define RXCTL_IA1 (1 << 1)
-#define RXCTL_IA0 (1 << 0)
-
-#define TXCTL_DEFDIS (1 << 7)
-#define TXCTL_MBE (1 << 6)
-#define TXCTL_ICRC (1 << 5)
-#define TXCTL_TPD (1 << 4)
-#define TXCTL_OCOLL (1 << 3)
-#define TXCTL_SP (1 << 2)
-#define TXCTL_PB (1 << 1)
-#define TXCTL_STXON (1 << 0)
-
-#define MIICMD_REGAD_MASK (0x001F)
-#define MIICMD_PHYAD_MASK (0x03E0)
-#define MIICMD_OPCODE_MASK (0xC000)
-#define MIICMD_PHYAD_8950 (0x0000)
-#define MIICMD_OPCODE_READ (0x8000)
-#define MIICMD_OPCODE_WRITE (0x4000)
-
-#define MIISTS_BUSY (1 << 0)
-
-/*
- * 0x80020000 - 0x8002FFFF: USB OHCI
- */
-#define USB_OFFSET 0x020000
-#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
-
-/*
- * 0x80030000 - 0x8003FFFF: Raster engine
- */
-#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
-#define RASTER_OFFSET 0x030000
-#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
-#endif
-
-/*
- * 0x80040000 - 0x8004FFFF: Graphics accelerator
- */
-#if defined(CONFIG_EP9315)
-#define GFX_OFFSET 0x040000
-#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
-#endif
-
-/*
- * 0x80050000 - 0x8005FFFF: Reserved
- */
-
-/*
- * 0x80060000 - 0x8006FFFF: SDRAM controller
- */
-#define SDRAM_OFFSET 0x060000
-#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct sdram_regs {
- uint32_t reserved;
- uint32_t glconfig;
- uint32_t refrshtimr;
- uint32_t bootsts;
- uint32_t devcfg0;
- uint32_t devcfg1;
- uint32_t devcfg2;
- uint32_t devcfg3;
-};
-#endif
-
-#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
-#define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
-#define SDRAM_DEVCFG_SROMLL (1 << 5)
-#define SDRAM_DEVCFG_CASLAT_2 0x00010000
-#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
-
-#define SDRAM_OFF_GLCONFIG 0x0004
-#define SDRAM_OFF_REFRSHTIMR 0x0008
-
-#define SDRAM_OFF_DEVCFG0 0x0010
-#define SDRAM_OFF_DEVCFG1 0x0014
-#define SDRAM_OFF_DEVCFG2 0x0018
-#define SDRAM_OFF_DEVCFG3 0x001C
-
-#define SDRAM_DEVCFG0_BASE 0xC0000000
-#define SDRAM_DEVCFG1_BASE 0xD0000000
-#define SDRAM_DEVCFG2_BASE 0xE0000000
-#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
-#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
-
-#define GLCONFIG_INIT (1 << 0)
-#define GLCONFIG_MRS (1 << 1)
-#define GLCONFIG_SMEMBUSY (1 << 5)
-#define GLCONFIG_LCR (1 << 6)
-#define GLCONFIG_REARBEN (1 << 7)
-#define GLCONFIG_CLKSHUTDOWN (1 << 30)
-#define GLCONFIG_CKE (1 << 31)
-
-#define EP93XX_SDRAMCTRL 0x80060000
-#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
-#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
-#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
-#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
-#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
-#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
-#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
-
-#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
-
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
-
-#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
-#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
-#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
-#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
-#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
-#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
-#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
-#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
-#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
-#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
-#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
-
-/*
- * 0x80070000 - 0x8007FFFF: Reserved
- */
-
-/*
- * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
- */
-#define SMC_OFFSET 0x080000
-#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct smc_regs {
- uint32_t bcr0;
- uint32_t bcr1;
- uint32_t bcr2;
- uint32_t bcr3;
- uint32_t reserved0[2];
- uint32_t bcr6;
- uint32_t bcr7;
-#if defined(CONFIG_EP9315)
- uint32_t pcattribute;
- uint32_t pccommon;
- uint32_t pcio;
- uint32_t reserved1[5];
- uint32_t pcmciactrl;
-#endif
-};
-#endif
-
-#define EP93XX_OFF_SMCBCR0 0x00
-#define EP93XX_OFF_SMCBCR1 0x04
-#define EP93XX_OFF_SMCBCR2 0x08
-#define EP93XX_OFF_SMCBCR3 0x0C
-#define EP93XX_OFF_SMCBCR6 0x18
-#define EP93XX_OFF_SMCBCR7 0x1C
-
-#define SMC_BCR_IDCY_SHIFT 0
-#define SMC_BCR_WST1_SHIFT 5
-#define SMC_BCR_BLE (1 << 10)
-#define SMC_BCR_WST2_SHIFT 11
-#define SMC_BCR_MW_SHIFT 28
-
-/*
- * 0x80090000 - 0x8009FFFF: Boot ROM
- */
-
-/*
- * 0x800A0000 - 0x800AFFFF: IDE interface
- */
-
-/*
- * 0x800B0000 - 0x800BFFFF: VIC1
- */
-
-/*
- * 0x800C0000 - 0x800CFFFF: VIC2
- */
-
-/*
- * 0x800D0000 - 0x800FFFFF: Reserved
- */
-
-/*
- * 0x80800000 - 0x8080FFFF: Reserved
- */
-
-/*
- * 0x80810000 - 0x8081FFFF: Timers
- */
-#define TIMER_OFFSET 0x010000
-#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct timer {
- uint32_t load;
- uint32_t value;
- uint32_t control;
- uint32_t clear;
-};
-
-struct timer4 {
- uint32_t value_low;
- uint32_t value_high;
-};
-
-struct timer_regs {
- struct timer timer1;
- uint32_t reserved0[4];
- struct timer timer2;
- uint32_t reserved1[12];
- struct timer4 timer4;
- uint32_t reserved2[6];
- struct timer timer3;
-};
-#endif
-
-/*
- * 0x80820000 - 0x8082FFFF: I2S
- */
-#define I2S_OFFSET 0x020000
-#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
-
-/*
- * 0x80830000 - 0x8083FFFF: Security
- */
-#define SECURITY_OFFSET 0x030000
-#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
-
-#define EXTENSIONID (SECURITY_BASE + 0x2714)
-
-/*
- * 0x80840000 - 0x8084FFFF: GPIO
- */
-#define GPIO_OFFSET 0x040000
-#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct gpio_int {
- uint32_t inttype1;
- uint32_t inttype2;
- uint32_t eoi;
- uint32_t inten;
- uint32_t intsts;
- uint32_t rawintsts;
- uint32_t db;
-};
-
-struct gpio_regs {
- uint32_t padr;
- uint32_t pbdr;
- uint32_t pcdr;
- uint32_t pddr;
- uint32_t paddr;
- uint32_t pbddr;
- uint32_t pcddr;
- uint32_t pdddr;
- uint32_t pedr;
- uint32_t peddr;
- uint32_t reserved0[2];
- uint32_t pfdr;
- uint32_t pfddr;
- uint32_t pgdr;
- uint32_t pgddr;
- uint32_t phdr;
- uint32_t phddr;
- uint32_t reserved1;
- uint32_t finttype1;
- uint32_t finttype2;
- uint32_t reserved2;
- struct gpio_int pfint;
- uint32_t reserved3[10];
- struct gpio_int paint;
- struct gpio_int pbint;
- uint32_t eedrive;
-};
-#endif
-
-#define EP93XX_LED_DATA 0x80840020
-#define EP93XX_LED_GREEN_ON 0x0001
-#define EP93XX_LED_RED_ON 0x0002
-
-#define EP93XX_LED_DDR 0x80840024
-#define EP93XX_LED_GREEN_ENABLE 0x0001
-#define EP93XX_LED_RED_ENABLE 0x00020000
-
-/*
- * 0x80850000 - 0x8087FFFF: Reserved
- */
-
-/*
- * 0x80880000 - 0x8088FFFF: AAC
- */
-#define AAC_OFFSET 0x080000
-#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
-
-/*
- * 0x80890000 - 0x8089FFFF: Reserved
- */
-
-/*
- * 0x808A0000 - 0x808AFFFF: SPI
- */
-#define SPI_OFFSET 0x0A0000
-#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
-
-/*
- * 0x808B0000 - 0x808BFFFF: IrDA
- */
-#define IRDA_OFFSET 0x0B0000
-#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
-
-/*
- * 0x808C0000 - 0x808CFFFF: UART1
- */
-#define UART1_OFFSET 0x0C0000
-#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
-
-/*
- * 0x808D0000 - 0x808DFFFF: UART2
- */
-#define UART2_OFFSET 0x0D0000
-#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
-
-/*
- * 0x808E0000 - 0x808EFFFF: UART3
- */
-#define UART3_OFFSET 0x0E0000
-#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
-
-/*
- * 0x808F0000 - 0x808FFFFF: Key Matrix
- */
-#define KEY_OFFSET 0x0F0000
-#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
-
-/*
- * 0x80900000 - 0x8090FFFF: Touchscreen
- */
-#define TOUCH_OFFSET 0x900000
-#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
-
-/*
- * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
- */
-#define PWM_OFFSET 0x910000
-#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
-
-/*
- * 0x80920000 - 0x8092FFFF: Real time clock
- */
-#define RTC_OFFSET 0x920000
-#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
-
-/*
- * 0x80930000 - 0x8093FFFF: Syscon
- */
-#define SYSCON_OFFSET 0x930000
-#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
-
-/* Security */
-#define SECURITY_EXTENSIONID 0x80832714
-
-#ifndef __ASSEMBLY__
-struct syscon_regs {
- uint32_t pwrsts;
- uint32_t pwrcnt;
- uint32_t halt;
- uint32_t stby;
- uint32_t reserved0[2];
- uint32_t teoi;
- uint32_t stfclr;
- uint32_t clkset1;
- uint32_t clkset2;
- uint32_t reserved1[6];
- uint32_t scratch0;
- uint32_t scratch1;
- uint32_t reserved2[2];
- uint32_t apbwait;
- uint32_t bustmstrarb;
- uint32_t bootmodeclr;
- uint32_t reserved3[9];
- uint32_t devicecfg;
- uint32_t vidclkdiv;
- uint32_t mirclkdiv;
- uint32_t i2sclkdiv;
- uint32_t keytchclkdiv;
- uint32_t chipid;
- uint32_t reserved4;
- uint32_t syscfg;
- uint32_t reserved5[8];
- uint32_t sysswlock;
-};
-#else
-#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
-#endif
-
-#define SYSCON_OFF_CLKSET1 0x0020
-#define SYSCON_OFF_SYSCFG 0x009c
-
-#define SYSCON_PWRCNT_UART_BAUD (1 << 29)
-#define SYSCON_PWRCNT_USH_EN (1 << 28)
-
-#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
-#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
-#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
-#define SYSCON_CLKSET_PLL_PS_SHIFT 16
-#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
-#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
-#define SYSCON_CLKSET1_NBYP1 (1 << 23)
-#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
-
-#define SYSCON_CLKSET2_PLL2_EN (1 << 18)
-#define SYSCON_CLKSET2_NBYP2 (1 << 19)
-#define SYSCON_CLKSET2_USB_DIV_SHIFT 28
-
-#define SYSCON_CHIPID_REV_MASK 0xF0000000
-#define SYSCON_DEVICECFG_SWRST (1 << 31)
-
-#define SYSCON_SYSCFG_LASDO 0x00000020
-
-/*
- * 0x80930000 - 0x8093FFFF: Watchdog Timer
- */
-#define WATCHDOG_OFFSET 0x940000
-#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
-
-/*
- * 0x80950000 - 0x9000FFFF: Reserved
- */
-
-/*
- * During low_level init we store memory layout in memory at specific location
- */
-#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
-#define UBOOT_MEMORYCNF_BANK_MASK 0x2004
-#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008
#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */
#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */
#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */
+#define MXC_CPU_IMX8MPUL 0x189 /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __ASM_ARCH_IMX8_REGS_H__
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
+#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
u32 imx_get_uartclk(void);
int clock_init(void);
void init_clk_usdhc(u32 index);
+void init_nand_clk(void);
void init_uart_clk(u32 index);
void init_usb_clk(void);
void init_wdog_clk(void);
#define SRC_DDRC_RCR_ADDR 0x30391000
#define SRC_DDRC2_RCR_ADDR 0x30391004
+#define APBH_DMA_ARB_BASE_ADDR 0x33000000
+#define APBH_DMA_ARB_END_ADDR 0x33007FFF
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
u32 ddr2_rcr;
};
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASK BIT(0)
struct wdog_regs {
};
u32 cgc_clk_get_rate(enum cgc_clk clk);
-void cgc1_pll3_init(void);
-void cgc1_pll2_init(void);
+void cgc1_pll3_init(ulong freq);
+void cgc1_pll2_init(ulong freq);
void cgc1_soscdiv_init(void);
-void cgc1_init_core_clk(void);
-void cgc2_pll4_init(void);
+void cgc1_init_core_clk(ulong freq);
+void cgc2_pll4_init(bool pll4_reset);
void cgc2_ddrclk_config(u32 src, u32 div);
void cgc2_ddrclk_wait_unlock(void);
u32 cgc1_sosc_div(enum cgc_clk clk);
#ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
#define _ASM_ARCH_IMX8ULP_CLOCK_H
+#include <asm/arch/pcc.h>
+#include <asm/arch/cgc.h>
+
+#define MHZ(X) ((X) * 1000000UL)
+
/* Mainly for compatible to imx common code. */
enum mxc_clock {
MXC_ARM_CLK = 0,
void init_clk_fspi(int index);
void init_clk_ddr(void);
int set_ddr_clk(u32 phy_freq_mhz);
-void clock_init(void);
+void clock_init_early(void);
+void clock_init_late(void);
void cgc1_enet_stamp_sel(u32 clk_src);
void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
void reset_lcdclk(void);
#define CMC0_RBASE 0x28025000
+#define MU0_B_BASE_ADDR 0x29220000
#define CMC1_BASE_ADDR 0x29240000
#define SIM1_BASE_ADDR 0x29290000
UPOWER_PCC3_SLOT = 40,
WDOG3_PCC3_SLOT = 42,
WDOG4_PCC3_SLOT = 43,
+ CAAM_PCC3_SLOT = 46,
XRDC_MGR_PCC3_SLOT = 47,
SEMA42_1_PCC3_SLOT = 48,
ROMCP1_PCC3_SLOT = 49,
#define AHAB_READ_FUSE_REQ_CID 0x97
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
#define AHAB_WRITE_FUSE_REQ_CID 0xD6
+#define AHAB_CAAM_RELEASE_CID 0xD7
-#define S400_MAX_MSG 8U
+#define S400_MAX_MSG 255U
struct imx8ulp_s400_msg {
u8 version;
int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
+int ahab_release_caam(u32 core_did, u32 *response);
+int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
#endif
enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
+bool m33_image_booted(void);
+int m33_image_handshake(ulong timeout_ms);
#endif
#define GPIO4_BASE_ADDR 0x401C4000
#define GPIO5_BASE_ADDR 0x400C0000
-#define ANATOP_BASE_ADDR 0x400d8000
-
#define MXS_LCDIF_BASE 0x402b8000
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#define SUNXI_GPIO_OUTPUT 1
#define SUNXI_GPIO_DISABLE 7
-#define SUNXI_GPA_EMAC 2
-#define SUN6I_GPA_GMAC 2
-#define SUN7I_GPA_GMAC 5
#define SUN8I_H3_GPA_UART0 2
+#define SUN8I_H3_GPA_UART2 2
#define SUN4I_GPB_PWM 2
#define SUN4I_GPB_TWI0 2
#define SUN4I_GPB_TWI1 2
#define SUN5I_GPB_TWI1 2
-#define SUN4I_GPB_TWI2 2
-#define SUN5I_GPB_TWI2 2
#define SUN8I_V3S_GPB_TWI0 2
#define SUN4I_GPB_UART0 2
#define SUN5I_GPB_UART0 2
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3
-#define SUNXI_GPD_PWM 2
#define SUNIV_GPE_UART0 5
-#define SUN8I_GPE_TWI2 3
-#define SUN50I_GPE_TWI2 3
#define SUNXI_GPF_SDC0 2
#define SUNXI_GPF_UART0 4
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
#define SUN8I_GPG_UART1 2
-#define SUN6I_GPG_TWI3 2
#define SUN5I_GPG_UART1 4
#define SUN6I_GPH_PWM 2
#define SUN6I_GPH_TWI1 2
#define SUN8I_GPH_TWI1 2
#define SUN50I_GPH_TWI1 2
-#define SUN6I_GPH_TWI2 2
#define SUN6I_GPH_UART0 2
#define SUN9I_GPH_UART0 2
#define SUN50I_H6_GPH_UART0 2
#define SUN50I_H616_GPH_UART0 2
#define SUNXI_GPI_SDC3 2
-#define SUN7I_GPI_TWI3 3
-#define SUN7I_GPI_TWI4 3
#define SUN6I_GPL0_R_P2WI_SCK 3
#define SUN6I_GPL1_R_P2WI_SDA 3
#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5
#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
+struct sunxi_gpio_plat {
+ struct sunxi_gpio *regs;
+ char bank_name[3];
+};
+
void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
#ifdef CONFIG_I2C1_ENABLE
#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE
#endif
-#ifdef CONFIG_I2C2_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE
-#endif
-#ifdef CONFIG_I2C3_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE
-#endif
-#ifdef CONFIG_I2C4_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE
-#endif
#ifdef CONFIG_R_I2C_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE
+#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
u32 w1_gate_reset; /* 0x1ec */
u8 res10[0x1c]; /* 0x1f0 */
u32 rtc_gate_reset; /* 0x20c */
+ u8 res11[0x34]; /* 0x210 */
+ u32 pll_ldo_cfg; /* 0x244 */
+ u8 res12[0x8]; /* 0x248 */
+ u32 sys_pwroff_gating; /* 0x250 */
+ u8 res13[0xbc]; /* 0x254 */
+ u32 res_cal_ctrl; /* 0x310 */
+ u32 ohms200; /* 0x314 */
+ u32 ohms240; /* 0x318 */
+ u32 res_cal_status; /* 0x31c */
};
check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c);
+check_member(sunxi_prcm_reg, res_cal_status, 0x31c);
#define PRCM_TWI_GATE (1 << 0)
#define PRCM_TWI_RESET (1 << 16)
#define SUNIV_BOOTED_FROM_SPI 0xffff4130
#define SUNIV_BOOTED_FROM_MMC1 0xffff4150
-#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0)
-
uint32_t sunxi_get_boot_device(void);
+uint32_t sunxi_get_spl_size(void);
#endif
#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
- is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
+ is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL))
#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
+#define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
BT_DEV_TYPE_MMC = 2,
BT_DEV_TYPE_NAND = 3,
BT_DEV_TYPE_FLEXSPINOR = 4,
+ BT_DEV_TYPE_SPI_NOR = 6,
BT_DEV_TYPE_USB = 0xE,
BT_DEV_TYPE_MEM_DEV = 0xF,
int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+void board_late_mmc_env_init(void);
+
unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
unsigned long reg1, unsigned long reg2,
unsigned long reg3);
endif
obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
+ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),)
+obj-y += save_prev_bl_data.o
+endif
+
+# obj-$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) += save_prev_bl_data.o
obj-y += bdinfo.o
obj-y += sections.o
CFLAGS_REMOVE_sections.o := $(LTO_CFLAGS)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * save_prev_bl_data - saving previous bootloader data
+ * to environment variables.
+ *
+ * Copyright (c) 2022 Dzmitry Sankouski (dsankouski@gmail.com)
+ */
+#include <init.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <fdt.h>
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+static ulong reg0 __section(".data");
+
+/**
+ * Save x0 register value, assuming previous bootloader set it to
+ * point on loaded fdt or (for older linux kernels)atags.
+ */
+void save_boot_params(ulong r0)
+{
+ reg0 = r0;
+ save_boot_params_ret();
+}
+
+bool is_addr_accessible(phys_addr_t addr)
+{
+ struct mm_region *mem = mem_map;
+ phys_addr_t bank_start;
+ phys_addr_t bank_end;
+
+ while (mem->size) {
+ bank_start = mem->phys;
+ bank_end = bank_start + mem->size;
+ debug("check if block %pap - %pap includes %pap\n", &bank_start, &bank_end, &addr);
+ if (addr > bank_start && addr < bank_end)
+ return true;
+ mem++;
+ }
+
+ return false;
+}
+
+int save_prev_bl_data(void)
+{
+ struct fdt_header *fdt_blob;
+ int node;
+ u64 initrd_start_prop;
+
+ if (!is_addr_accessible((phys_addr_t)reg0))
+ return -ENODATA;
+
+ fdt_blob = (struct fdt_header *)reg0;
+ if (!fdt_valid(&fdt_blob)) {
+ pr_warn("%s: address 0x%lx is not a valid fdt\n", __func__, reg0);
+ return -ENODATA;
+ }
+
+ if (CONFIG_IS_ENABLED(SAVE_PREV_BL_FDT_ADDR))
+ env_set_addr("prevbl_fdt_addr", (void *)reg0);
+ if (!CONFIG_IS_ENABLED(SAVE_PREV_BL_INITRAMFS_START_ADDR))
+ return 0;
+
+ node = fdt_path_offset(fdt_blob, "/chosen");
+ if (!node) {
+ pr_warn("%s: chosen node not found in device tree at addr: 0x%lx\n",
+ __func__, reg0);
+ return -ENODATA;
+ }
+ /*
+ * linux,initrd-start property might be either 64 or 32 bit,
+ * depending on primary bootloader implementation.
+ */
+ initrd_start_prop = fdtdec_get_uint64(fdt_blob, node, "linux,initrd-start", 0);
+ if (!initrd_start_prop) {
+ debug("%s: attempt to get uint64 linux,initrd-start property failed, trying uint\n",
+ __func__);
+ initrd_start_prop = fdtdec_get_uint(fdt_blob, node, "linux,initrd-start", 0);
+ if (!initrd_start_prop) {
+ debug("%s: attempt to get uint failed, too\n", __func__);
+ return -ENODATA;
+ }
+ }
+ env_set_addr("prevbl_initrd_start_addr", (void *)initrd_start_prop);
+
+ return 0;
+}
}
};
+/* Apple M1 Ultra */
+
+static struct mm_region t6002_mem_map[] = {
+ {
+ /* I/O */
+ .virt = 0x280000000,
+ .phys = 0x280000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x380000000,
+ .phys = 0x380000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x580000000,
+ .phys = 0x580000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5a0000000,
+ .phys = 0x5a0000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5c0000000,
+ .phys = 0x5c0000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x700000000,
+ .phys = 0x700000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xb00000000,
+ .phys = 0xb00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xf00000000,
+ .phys = 0xf00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x1300000000,
+ .phys = 0x1300000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2280000000,
+ .phys = 0x2280000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2380000000,
+ .phys = 0x2380000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2580000000,
+ .phys = 0x2580000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x25a0000000,
+ .phys = 0x25a0000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x25c0000000,
+ .phys = 0x25c0000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2700000000,
+ .phys = 0x2700000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2b00000000,
+ .phys = 0x2b00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2f00000000,
+ .phys = 0x2f00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x3300000000,
+ .phys = 0x3300000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* RAM */
+ .virt = 0x10000000000,
+ .phys = 0x10000000000,
+ .size = 16UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Framebuffer */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
struct mm_region *mem_map;
int board_init(void)
mem_map = t6000_mem_map;
else if (of_machine_is_compatible("apple,t6001"))
mem_map = t6000_mem_map;
+ else if (of_machine_is_compatible("apple,t6002"))
+ mem_map = t6002_mem_map;
else
panic("Unsupported SoC\n");
obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
obj-$(CONFIG_SAM9X60) += sam9x60_devices.o
obj-$(CONFIG_AT91_EFLASH) += eflash.o
-obj-$(CONFIG_AT91_LED) += led.o
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
-#include <status_led.h>
-
-#ifdef CONFIG_RED_LED
-void red_led_on(void)
-{
- gpio_set_value(CONFIG_RED_LED, 1);
-}
-
-void red_led_off(void)
-{
- gpio_set_value(CONFIG_RED_LED, 0);
-}
-#endif
-
-#ifdef CONFIG_GREEN_LED
-void green_led_on(void)
-{
- gpio_set_value(CONFIG_GREEN_LED, 0);
-}
-
-void green_led_off(void)
-{
- gpio_set_value(CONFIG_GREEN_LED, 1);
-}
-#endif
-
-#ifdef CONFIG_YELLOW_LED
-void yellow_led_on(void)
-{
- gpio_set_value(CONFIG_YELLOW_LED, 0);
-}
-
-void yellow_led_off(void)
-{
- gpio_set_value(CONFIG_YELLOW_LED, 1);
-}
-#endif
#include <command.h>
#include <log.h>
#include <malloc.h>
+#include <memalign.h>
#include <asm/byteorder.h>
#include <linux/compiler.h>
#include <fsl_sec.h>
return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
case MXC_CPU_IMX8MP6:
return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
+ case MXC_CPU_IMX8MPUL:
+ return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */
case MXC_CPU_IMX8MN:
return "8MNano Quad"; /* Quad-core version */
case MXC_CPU_IMX8MND:
config IMX8
bool
+ select HAS_CAAM
config MU_BASE_SPL
hex "MU base address used in SPL"
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
select IMX8QM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
bool "Support i.MX8QXP MEK board"
select BOARD_LATE_INIT
select IMX8QXP
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
endchoice
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <common.h>
}
EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu);
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
+
+ return 0;
+}
+#endif
+
int print_bootinfo(void)
{
enum boot_device bt_dev = get_boot_device();
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
select IMX8MQ
select IMX8M_LPDDR4
+config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
+ bool "Data Modul eDM SBC i.MX8M Mini"
+ select BINMAN
+ select IMX8MM
+ select IMX8M_LPDDR4
+ select SUPPORT_SPL
+
config TARGET_IMX8MM_EVK
bool "imx8mm LPDDR4 EVK board"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
* i.Core MX8M Mini needs to mount on top of this Carrier board
for creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
+config TARGET_IMX8MM_MX8MENLO
+ bool "Support i.MX8M Mini MX8Menlo board based on Toradex Verdin SoM"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
select BINMAN
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_IMX8MN_BSH_SMM_S2
+ bool "imx8mn-bsh-smm-s2"
+ select BINMAN
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_DDR3L
+
+config TARGET_IMX8MN_BSH_SMM_S2PRO
+ bool "imx8mn-bsh-smm-s2pro"
+ select BINMAN
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_DDR3L
+
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
+ select FSL_CAAM
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MN_VENICE
bool "Support Gateworks Venice iMX8M Nano module"
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
source "board/advantech/imx8mp_rsb3720a1/Kconfig"
source "board/beacon/imx8mm/Kconfig"
source "board/beacon/imx8mn/Kconfig"
+source "board/bsh/imx8mn_smm_s2/Kconfig"
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
+source "board/data_modul/imx8mm_edm_sbc/Kconfig"
source "board/engicam/imx8mm/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
source "board/kontron/pitx_imx8m/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
+source "board/menlo/mx8menlo/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"
#ifdef CONFIG_SPL_BUILD
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
+ PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2019, 2021 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#include <asm/ptrace.h>
#include <asm/armv8/mmu.h>
#include <dm/uclass.h>
+#include <dm/device.h>
#include <efi_loader.h>
#include <env.h>
#include <env_internal.h>
#include <fdt_support.h>
#include <fsl_wdog.h>
#include <imx_sip.h>
-#include <linux/arm-smccc.h>
#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
* According to TRM, TZASC_ID_SWAP_BYPASS should be set in
* order to avoid AXI Bus errors when GPU is in use
*/
- if (is_imx8mm() || is_imx8mn() || is_imx8mp())
+ if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp())
setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
/*
void enable_caches(void)
{
- /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
- if (rom_pointer[1]) {
- /*
- * TEE are loaded, So the ddr bank structures
- * have been modified update mmu table accordingly
- */
- int i = 0;
- /*
- * please make sure that entry initial value matches
- * imx8m_mem_map for DRAM1
- */
- int entry = imx8m_find_dram_entry_in_mem_map();
- u64 attrs = imx8m_mem_map[entry].attrs;
-
- while (i < CONFIG_NR_DRAM_BANKS &&
- entry < ARRAY_SIZE(imx8m_mem_map)) {
- if (gd->bd->bi_dram[i].start == 0)
- break;
- imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
- imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
- imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
- imx8m_mem_map[entry].attrs = attrs;
- debug("Added memory mapping (%d): %llx %llx\n", entry,
- imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
- i++; entry++;
- }
+ /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
+ * If OPTEE does not run, still update the MMU table according to dram banks structure
+ * to set correct dram size from board_phys_sdram_size
+ */
+ int i = 0;
+ /*
+ * please make sure that entry initial value matches
+ * imx8m_mem_map for DRAM1
+ */
+ int entry = imx8m_find_dram_entry_in_mem_map();
+ u64 attrs = imx8m_mem_map[entry].attrs;
+
+ while (i < CONFIG_NR_DRAM_BANKS &&
+ entry < ARRAY_SIZE(imx8m_mem_map)) {
+ if (gd->bd->bi_dram[i].start == 0)
+ break;
+ imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+ imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+ imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
+ imx8m_mem_map[entry].attrs = attrs;
+ debug("Added memory mapping (%d): %llx %llx\n", entry,
+ imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
+ i++; entry++;
}
icache_enable();
return -EINVAL;
*size = PHYS_SDRAM_SIZE;
+
+#ifdef PHYS_SDRAM_2_SIZE
+ *size += PHYS_SDRAM_2_SIZE;
+#endif
return 0;
}
int dram_init(void)
{
- unsigned int entry = imx8m_find_dram_entry_in_mem_map();
phys_size_t sdram_size;
int ret;
else
gd->ram_size = sdram_size;
- /* also update the SDRAM size in the mem_map used externally */
- imx8m_mem_map[entry].size = sdram_size;
-
-#ifdef PHYS_SDRAM_2_SIZE
- gd->ram_size += PHYS_SDRAM_2_SIZE;
-#endif
-
return 0;
}
int bank = 0;
int ret;
phys_size_t sdram_size;
+ phys_size_t sdram_b1_size, sdram_b2_size;
ret = board_phys_sdram_size(&sdram_size);
if (ret)
return ret;
+ /* Bank 1 can't cross over 4GB space */
+ if (sdram_size > 0xc0000000) {
+ sdram_b1_size = 0xc0000000;
+ sdram_b2_size = sdram_size - 0xc0000000;
+ } else {
+ sdram_b1_size = sdram_size;
+ sdram_b2_size = 0;
+ }
+
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
- if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
+ if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
gd->bd->bi_dram[bank].start = optee_start + optee_size;
gd->bd->bi_dram[bank].size = PHYS_SDRAM +
- sdram_size - gd->bd->bi_dram[bank].start;
+ sdram_b1_size - gd->bd->bi_dram[bank].start;
}
} else {
- gd->bd->bi_dram[bank].size = sdram_size;
+ gd->bd->bi_dram[bank].size = sdram_b1_size;
}
-#ifdef PHYS_SDRAM_2_SIZE
- if (++bank >= CONFIG_NR_DRAM_BANKS) {
- puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
- return -1;
+ if (sdram_b2_size) {
+ if (++bank >= CONFIG_NR_DRAM_BANKS) {
+ puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
+ return -1;
+ }
+ gd->bd->bi_dram[bank].start = 0x100000000UL;
+ gd->bd->bi_dram[bank].size = sdram_b2_size;
}
- gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
-#endif
return 0;
}
phys_size_t get_effective_memsize(void)
{
- /* return the first bank as effective memory */
- if (rom_pointer[1])
- return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
+ int ret;
+ phys_size_t sdram_size;
+ phys_size_t sdram_b1_size;
+ ret = board_phys_sdram_size(&sdram_size);
+ if (!ret) {
+ /* Bank 1 can't cross over 4GB space */
+ if (sdram_size > 0xc0000000) {
+ sdram_b1_size = 0xc0000000;
+ } else {
+ sdram_b1_size = sdram_size;
+ }
-#ifdef PHYS_SDRAM_2_SIZE
- return gd->ram_size - PHYS_SDRAM_2_SIZE;
-#else
- return gd->ram_size;
-#endif
+ if (rom_pointer[1]) {
+ /* We will relocate u-boot to Top of dram1. Tee position has two cases:
+ * 1. At the top of dram1, Then return the size removed optee size.
+ * 2. In the middle of dram1, return the size of dram1.
+ */
+ if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
+ return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
+ }
+
+ return sdram_b1_size;
+ } else {
+ return PHYS_SDRAM_SIZE;
+ }
}
ulong board_get_usable_ram_top(ulong total_size)
/* npu disabled*/
if ((value & 0x8) == 0x8)
- flag |= (1 << 1);
+ flag |= BIT(1);
/* isp disabled */
if ((value & 0x3) == 0x3)
- flag |= (1 << 2);
+ flag |= BIT(2);
+
+ /* gpu disabled */
+ if ((value & 0xc0) == 0xc0)
+ flag |= BIT(3);
+
+ /* lvds disabled */
+ if ((value & 0x180000) == 0x180000)
+ flag |= BIT(4);
+
+ /* mipi dsi disabled */
+ if ((value & 0x60000) == 0x60000)
+ flag |= BIT(5);
switch (flag) {
+ case 0x3f:
+ return MXC_CPU_IMX8MPUL;
case 7:
return MXC_CPU_IMX8MPL;
case 2:
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+ icache_enable();
+#endif
+
/*
* ROM might disable clock for SCTR,
* enable the clock before timer_init.
case BT_DEV_TYPE_FLEXSPINOR:
boot_dev = QSPI_BOOT;
break;
+ case BT_DEV_TYPE_SPI_NOR:
+ boot_dev = SPI_NOR_BOOT;
+ break;
case BT_DEV_TYPE_USB:
boot_dev = USB_BOOT;
break;
}
#endif
+static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
+{
+ int lookup_node;
+ int nodeoff;
+
+ nodeoff = fdt_path_offset(blob, ep1);
+ if (nodeoff) {
+ lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
+ nodeoff = fdt_path_offset(blob, ep2);
+
+ if (nodeoff > 0 && nodeoff == lookup_node)
+ return true;
+ }
+
+ return false;
+}
+
+int disable_dsi_lcdif_nodes(void *blob)
+{
+ int ret;
+
+ static const char * const dsi_path_8mp[] = {
+ "/soc@0/bus@32c00000/mipi_dsi@32e60000"
+ };
+
+ static const char * const lcdif_path_8mp[] = {
+ "/soc@0/bus@32c00000/lcd-controller@32e80000"
+ };
+
+ static const char * const lcdif_ep_path_8mp[] = {
+ "/soc@0/bus@32c00000/lcd-controller@32e80000/port@0/endpoint"
+ };
+ static const char * const dsi_ep_path_8mp[] = {
+ "/soc@0/bus@32c00000/mipi_dsi@32e60000/port@0/endpoint"
+ };
+
+ ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
+ if (ret)
+ return ret;
+
+ if (check_remote_endpoint(blob, dsi_ep_path_8mp[0], lcdif_ep_path_8mp[0])) {
+ /* Disable lcdif node */
+ return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
+ }
+
+ return 0;
+}
+
+int disable_lvds_lcdif_nodes(void *blob)
+{
+ int ret, i;
+
+ static const char * const ldb_path_8mp[] = {
+ "/soc@0/bus@32c00000/ldb@32ec005c",
+ "/soc@0/bus@32c00000/phy@32ec0128"
+ };
+
+ static const char * const lcdif_path_8mp[] = {
+ "/soc@0/bus@32c00000/lcd-controller@32e90000"
+ };
+
+ static const char * const lcdif_ep_path_8mp[] = {
+ "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@0",
+ "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@1"
+ };
+ static const char * const ldb_ep_path_8mp[] = {
+ "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
+ "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
+ };
+
+ ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
+ if (check_remote_endpoint(blob, ldb_ep_path_8mp[i], lcdif_ep_path_8mp[i])) {
+ /* Disable lcdif node */
+ return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
+ }
+ }
+
+ return 0;
+}
+
int disable_gpu_nodes(void *blob)
{
static const char * const nodes_path_8mn[] = {
"/soc@/gpu@38000000"
};
- return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
+ static const char * const nodes_path_8mp[] = {
+ "/gpu3d@38000000",
+ "/gpu2d@38008000"
+ };
+
+ if (is_imx8mp())
+ return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
+ else
+ return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
}
int disable_npu_nodes(void *blob)
return 0;
}
+static int cleanup_nodes_for_efi(void *blob)
+{
+ static const char * const path[][2] = {
+ { "/soc@0/bus@32c00000/usb@32e40000", "extcon" },
+ { "/soc@0/bus@32c00000/usb@32e50000", "extcon" },
+ { "/soc@0/bus@30800000/ethernet@30be0000", "phy-reset-gpios" },
+ { "/soc@0/bus@30800000/ethernet@30bf0000", "phy-reset-gpios" }
+ };
+ int nodeoff, i, rc;
+
+ for (i = 0; i < ARRAY_SIZE(path); i++) {
+ nodeoff = fdt_path_offset(blob, path[i][0]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+ debug("Found %s node\n", path[i][0]);
+
+ rc = fdt_delprop(blob, nodeoff, path[i][1]);
+ if (rc == -FDT_ERR_NOTFOUND)
+ continue;
+ if (rc) {
+ printf("Unable to update property %s:%s, err=%s\n",
+ path[i][0], path[i][1], fdt_strerror(rc));
+ return rc;
+ }
+
+ printf("Remove %s:%s\n", path[i][0], path[i][1]);
+ }
+
+ return 0;
+}
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
#ifdef CONFIG_IMX8MQ
disable_cpu_nodes(blob, 3);
#elif defined(CONFIG_IMX8MP)
- if (is_imx8mpl())
+ if (is_imx8mpul()) {
+ /* Disable GPU */
+ disable_gpu_nodes(blob);
+
+ /* Disable DSI */
+ disable_dsi_lcdif_nodes(blob);
+
+ /* Disable LVDS */
+ disable_lvds_lcdif_nodes(blob);
+ }
+
+ if (is_imx8mpul() || is_imx8mpl())
disable_vpu_nodes(blob);
- if (is_imx8mpl() || is_imx8mp6())
+ if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
disable_npu_nodes(blob);
- if (is_imx8mpl())
+ if (is_imx8mpul() || is_imx8mpl())
disable_isp_nodes(blob);
- if (is_imx8mpl() || is_imx8mp6())
+ if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
disable_dsp_nodes(blob);
if (is_imx8mpd())
disable_cpu_nodes(blob, 2);
#endif
+ cleanup_nodes_for_efi(blob);
return 0;
}
#endif
+#ifdef CONFIG_OF_BOARD_FIXUP
+#ifndef CONFIG_SPL_BUILD
+int board_fix_fdt(void *fdt)
+{
+ if (is_imx8mpul()) {
+ int i = 0;
+ int nodeoff, ret;
+ const char *status = "disabled";
+ static const char * const dsi_nodes[] = {
+ "/soc@0/bus@32c00000/mipi_dsi@32e60000",
+ "/soc@0/bus@32c00000/lcd-controller@32e80000",
+ "/dsi-host"
+ };
+
+ for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) {
+ nodeoff = fdt_path_offset(fdt, dsi_nodes[i]);
+ if (nodeoff > 0) {
+set_status:
+ ret = fdt_setprop(fdt, nodeoff, "status", status,
+ strlen(status) + 1);
+ if (ret == -FDT_ERR_NOSPACE) {
+ ret = fdt_increase_size(fdt, 512);
+ if (!ret)
+ goto set_status;
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+#endif
+#endif
+
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
#endif
#if defined(CONFIG_ARCH_MISC_INIT)
-static void acquire_buildinfo(void)
-{
- u64 atf_commit = 0;
- struct arm_smccc_res res;
-
- /* Get ARM Trusted Firmware commit id */
- arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
- 0, 0, 0, 0, 0, 0, &res);
- atf_commit = res.a0;
- if (atf_commit == 0xffffffff) {
- debug("ATF does not support build info\n");
- atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
- }
-
- printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
-}
-
int arch_misc_init(void)
{
- acquire_buildinfo();
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
return 0;
}
switch (dev) {
case QSPI_BOOT:
+ case SPI_NOR_BOOT:
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
return ENVL_SPI_FLASH;
return ENVL_NOWHERE;
config IMX8ULP
bool
- select ARMV8_SPL_EXCEPTION_VECTORS
config SYS_SOC
default "imx8ulp"
+config IMX8ULP_LD_MODE
+ bool
+
+config IMX8ULP_ND_MODE
+ bool "i.MX8ULP Low Driver Mode"
+
choice
prompt "i.MX8ULP board select"
optional
#include <errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/cgc.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <linux/delay.h>
+#include <hang.h>
DECLARE_GLOBAL_DATA_PTR;
clrbits_le32(&cgc1_regs->frodiv, BIT(7));
}
-void cgc1_pll2_init(void)
+void cgc1_pll2_init(ulong freq)
{
u32 reg;
while ((readl(&cgc1_regs->pll2csr) & BIT(24)))
;
- /* Select SOSC as source, freq = 31 * 24 =744mhz */
- reg = 31 << 16;
+ /* Select SOSC as source */
+ reg = (freq / MHZ(24)) << 16;
writel(reg, &cgc1_regs->pll2cfg);
/* Enable PLL2 */
;
}
-void cgc1_init_core_clk(void)
+void cgc1_init_core_clk(ulong freq)
{
u32 reg = readl(&cgc1_regs->ca35clk);
if (((reg >> 28) & 0x3) == 0x1)
cgc1_set_a35_clk(0, 1);
- /* Set pll2 to 750Mhz for 1V */
- cgc1_pll2_init();
+ cgc1_pll2_init(freq);
/* Set A35 clock to pll2 */
cgc1_set_a35_clk(1, 1);
writel((clk_src & 0x7) << 24, &cgc1_regs->enetstamp);
}
-void cgc1_pll3_init(void)
+void cgc1_pll3_init(ulong freq)
{
/* Gate off VCO */
setbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
/* Select SOSC as source */
clrbits_le32(&cgc1_regs->pll3cfg, BIT(0));
- //setbits_le32(&cgc1_regs->pll3cfg, 22 << 16);
- writel(22 << 16, &cgc1_regs->pll3cfg);
-
- writel(578, &cgc1_regs->pll3num);
- writel(1000, &cgc1_regs->pll3denom);
+ switch (freq) {
+ case 540672000:
+ writel(0x16 << 16, &cgc1_regs->pll3cfg);
+ writel(0x16e3600, &cgc1_regs->pll3denom);
+ writel(0xc15c00, &cgc1_regs->pll3num);
+ break;
+ default:
+ hang();
+ }
/* Enable PLL3 */
setbits_le32(&cgc1_regs->pll3csr, BIT(0));
/* Gate on VCO */
clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
- /*
- * PFD0: 380MHz/396/396/328
- */
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F);
- setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
+
+ if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+ setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
+ clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 3 << 21); /* 195M */
+ } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+ setbits_le32(&cgc1_regs->pll3pfdcfg, 21 << 0);
+ clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); /* 231M */
+ } else {
+ setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* 324M */
+ }
+
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8);
- setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 8);
+ setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8);
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16);
- setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 16);
+ setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 16);
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22)))
;
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(15));
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23));
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31));
+
+ if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+ /* nicclk select pll3 pfd0 */
+ clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(29, 28), BIT(28));
+ while (!(readl(&cgc1_regs->nicclk) & BIT(27)))
+ ;
+ }
}
-void cgc2_pll4_init(void)
+void cgc2_pll4_init(bool pll4_reset)
{
+ /* Check the NICLPAV first to ensure not from PLL4 PFD1 clock */
+ if ((readl(&cgc2_regs->niclpavclk) & GENMASK(29, 28)) == BIT(28)) {
+ /* switch to FRO 192 first */
+ clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28));
+ while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
+ ;
+ }
+
/* Disable PFD DIV and clear DIV */
writel(0x80808080, &cgc2_regs->pll4div_pfd0);
writel(0x80808080, &cgc2_regs->pll4div_pfd1);
/* Gate off and clear PFD */
writel(0x80808080, &cgc2_regs->pll4pfdcfg);
- /* Disable PLL4 */
- writel(0x0, &cgc2_regs->pll4csr);
+ if (pll4_reset) {
+ /* Disable PLL4 */
+ writel(0x0, &cgc2_regs->pll4csr);
- /* Configure PLL4 to 528Mhz and clock source from SOSC */
- writel(22 << 16, &cgc2_regs->pll4cfg);
- writel(0x1, &cgc2_regs->pll4csr);
+ /* Configure PLL4 to 528Mhz and clock source from SOSC */
+ writel(22 << 16, &cgc2_regs->pll4cfg);
+ writel(0x1, &cgc2_regs->pll4csr);
- /* wait for PLL4 output valid */
- while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
- ;
+ /* wait for PLL4 output valid */
+ while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
+ ;
+ }
/* Enable all 4 PFDs */
- setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0);
- setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
- setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16);
- setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24);
+ setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */
+ if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+ setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
+ /* 99Mhz for NIC_LPAV */
+ clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 3 << 21);
+ } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+ setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
+ /* 198Mhz for NIC_LPAV */
+ clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21);
+ } else {
+ setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
+ clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21));
+ }
+ setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); /* 792 */
+ setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396 */
clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31));
/* Enable PFD DIV */
clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
+
+ clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28));
+ while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
+ ;
}
void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd)
writel(0xc0000000, PCC5_LPDDR4_ADDR);
/* enable pll4 and ddrclk*/
- cgc2_pll4_init();
- cgc2_ddrclk_config(1, 1);
+ cgc2_pll4_init(true);
+ cgc2_ddrclk_config(4, 1);
/* enable ddr pcc */
writel(0xd0000000, PCC5_LPDDR4_ADDR);
return 0;
}
-void clock_init(void)
+void clock_init_early(void)
{
cgc1_soscdiv_init();
- cgc1_init_core_clk();
init_clk_lpuart();
- pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
- pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
- pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
- pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+ /* Enable upower mu1 clk */
+ pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
+}
- pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
- pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
- pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
- pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+/* This will be invoked after pmic voltage setting */
+void clock_init_late(void)
+{
- pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
- pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
- pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
- pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+ if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE))
+ cgc1_init_core_clk(MHZ(500));
+ else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE))
+ cgc1_init_core_clk(MHZ(750));
+ else
+ cgc1_init_core_clk(MHZ(960));
- /* Enable upower mu1 clk */
- pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
+ /*
+ * Audio use this frequency in kernel dts,
+ * however nic use pll3 pfd0, we have to
+ * make the freqency same as kernel to make nic
+ * not being disabled
+ */
+ cgc1_pll3_init(540672000);
+
+ if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+ pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2);
+ pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+
+ pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2);
+ pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+
+ pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2);
+ pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+ } else {
+ pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
+ pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+
+ pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
+ pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+
+ pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
+ pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+ }
+
+ /* enable MU0_MUB clock before access the register of MU0_MUB */
+ pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
/*
* Enable clock division
}
#endif
+#if IS_ENABLED(CONFIG_SYS_I2C_IMX_I3C)
+int enable_i3c_clk(unsigned char enable, u32 i3c_num)
+{
+ if (enable) {
+ pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
+ pcc_clock_sel(3, I3C2_PCC3_SLOT, SOSC_DIV2);
+ pcc_clock_enable(3, I3C2_PCC3_SLOT, true);
+ pcc_reset_peripheral(3, I3C2_PCC3_SLOT, false);
+ } else {
+ pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
+ }
+ return 0;
+}
+
+u32 imx_get_i3cclk(u32 i3c_num)
+{
+ return pcc_clock_get_rate(3, I3C2_PCC3_SLOT);
+}
+#endif
+
void enable_usboh3_clk(unsigned char enable)
{
if (enable) {
{PCC3_RBASE, UPOWER_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
{PCC3_RBASE, WDOG3_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B},
{PCC3_RBASE, WDOG4_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B},
+ {PCC3_RBASE, CAAM_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B},
{PCC3_RBASE, XRDC_MGR_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
{PCC3_RBASE, SEMA42_1_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV, PCC_NO_RST_B},
{PCC3_RBASE, ROMCP1_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
#include <dm/uclass-internal.h>
#include <fuse.h>
#include <thermal.h>
+#include <linux/iopoll.h>
+#include <env.h>
+#include <env_internal.h>
DECLARE_GLOBAL_DATA_PTR;
return LOW_POWER_BOOT;
}
+bool m33_image_booted(void)
+{
+ u32 gp6;
+
+ /* DGO_GP6 */
+ gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
+ if (gp6 & BIT(5))
+ return true;
+
+ return false;
+}
+
+int m33_image_handshake(ulong timeout_ms)
+{
+ u32 fsr;
+ int ret;
+ ulong timeout_us = timeout_ms * 1000;
+
+ /* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */
+ setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */
+
+ /*
+ * Wait m33 to set FCR F0 flag of MU0_MUA
+ * Clear FCR F0 flag of MU0_MUB after m33 has set FCR F0 flag of MU0_MUA
+ */
+ ret = readl_poll_sleep_timeout(MU0_B_BASE_ADDR + 0x104, fsr, fsr & BIT(0), 10, timeout_us);
+ if (!ret)
+ clrbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0));
+
+ return ret;
+}
+
#define CMC_SRS_TAMPER BIT(31)
#define CMC_SRS_SECURITY BIT(30)
#define CMC_SRS_TZWDG BIT(29)
struct mm_region *mem_map = imx8ulp_arm64_mem_map;
+static unsigned int imx8ulp_find_dram_entry_in_mem_map(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
+ if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+ return i;
+
+ hang(); /* Entry not found, this must never happen. */
+}
+
/* simplify the page table size to enhance boot speed */
#define MAX_PTE_ENTRIES 512
#define MAX_MEM_MAP_REGIONS 16
void enable_caches(void)
{
- /* TODO: add TEE memmap region */
+ /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
+ if (rom_pointer[1]) {
+ /*
+ * TEE are loaded, So the ddr bank structures
+ * have been modified update mmu table accordingly
+ */
+ int i = 0;
+ int entry = imx8ulp_find_dram_entry_in_mem_map();
+ u64 attrs = imx8ulp_arm64_mem_map[entry].attrs;
+
+ while (i < CONFIG_NR_DRAM_BANKS &&
+ entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) {
+ if (gd->bd->bi_dram[i].start == 0)
+ break;
+ imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+ imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+ imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size;
+ imx8ulp_arm64_mem_map[entry].attrs = attrs;
+ debug("Added memory mapping (%d): %llx %llx\n", entry,
+ imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size);
+ i++; entry++;
+ }
+ }
icache_enable();
dcache_enable();
}
+__weak int board_phys_sdram_size(phys_size_t *size)
+{
+ if (!size)
+ return -EINVAL;
+
+ *size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_SIZE;
+ unsigned int entry = imx8ulp_find_dram_entry_in_mem_map();
+ phys_size_t sdram_size;
+ int ret;
+
+ ret = board_phys_sdram_size(&sdram_size);
+ if (ret)
+ return ret;
+
+ /* rom_pointer[1] contains the size of TEE occupies */
+ if (rom_pointer[1])
+ gd->ram_size = sdram_size - rom_pointer[1];
+ else
+ gd->ram_size = sdram_size;
+ /* also update the SDRAM size in the mem_map used externally */
+ imx8ulp_arm64_mem_map[entry].size = sdram_size;
return 0;
}
+int dram_init_banksize(void)
+{
+ int bank = 0;
+ int ret;
+ phys_size_t sdram_size;
+
+ ret = board_phys_sdram_size(&sdram_size);
+ if (ret)
+ return ret;
+
+ gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+ if (rom_pointer[1]) {
+ phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
+ phys_size_t optee_size = (size_t)rom_pointer[1];
+
+ gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+ if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
+ if (++bank >= CONFIG_NR_DRAM_BANKS) {
+ puts("CONFIG_NR_DRAM_BANKS is not enough\n");
+ return -1;
+ }
+
+ gd->bd->bi_dram[bank].start = optee_start + optee_size;
+ gd->bd->bi_dram[bank].size = PHYS_SDRAM +
+ sdram_size - gd->bd->bi_dram[bank].start;
+ }
+ } else {
+ gd->bd->bi_dram[bank].size = sdram_size;
+ }
+
+ return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ /* return the first bank as effective memory */
+ if (rom_pointer[1])
+ return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
+
+ return gd->ram_size;
+}
+
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
void get_board_serial(struct tag_serialnr *serialnr)
{
return 0;
}
-void lpav_configure(void)
+void lpav_configure(bool lpav_to_m33)
{
- /* LPAV to APD */
- setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7));
+ if (!lpav_to_m33)
+ setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7)); /* LPAV to APD */
/* PXP/GPU 2D/3D/DCNANO/MIPI_DSI/EPDC/HIFI4 to APD */
setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, 0x7F);
int ret;
bool rdc_en = true; /* Default assume DBD_EN is set */
+ /* Enable System Reset Interrupt using WDOG_AD */
+ setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
+ /* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
+ setbits_le32(CMC1_BASE_ADDR + 0x70, BIT(4));
+
+ if (readl(CMC1_BASE_ADDR + 0x90) & BIT(13)) {
+ /* Clear System Reset Interrupt Flag Register of WDOG_AD */
+ setbits_le32(CMC1_BASE_ADDR + 0x90, BIT(13));
+ /* Reset WDOG to clear reset request */
+ pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, true);
+ pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, false);
+ }
+
/* Disable wdog */
init_wdog();
release_rdc(RDC_TRDC);
trdc_set_access();
-
- lpav_configure();
+ lpav_configure(false);
+ } else {
+ lpav_configure(true);
}
/* Release xrdc, then allow A35 to write SRAM2 */
xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
- clock_init();
+ clock_init_early();
} else {
/* reconfigure core0 reset vector to ROM */
set_core0_reset_vector(0x1000);
return image_offset;
}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ switch (dev) {
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ case QSPI_BOOT:
+ env_loc = ENVL_SPI_FLASH;
+ break;
+#endif
+#ifdef CONFIG_ENV_IS_IN_MMC
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+#endif
+ default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+ env_loc = ENVL_NOWHERE;
+#endif
+ break;
+ }
+
+ return env_loc;
+}
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6SABRESD
bool "mx6sabresd"
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6SLEVK
bool "mx6slevk"
select DM
select DM_THERMAL
select SUPPORT_SPL
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6SXSABREAUTO
bool "mx6sxsabreauto"
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
- u32 esdmisc_val, zq_val;
+ u32 esdmisc_val, zq_val, mdmisc_val;
u32 errors = 0;
u32 ldectrl[4] = {0};
u32 ddr_mr1 = 0x4;
/* disable Adopt power down timer */
setbits_le32(&mmdc0->mapsr, 0x1);
+ /* Save old RALAT and WALAT values */
+ mdmisc_val = readl(&mmdc0->mdmisc);
+
debug("Starting write leveling calibration.\n");
/*
writel(esdmisc_val, &mmdc0->mdref);
writel(zq_val, &mmdc0->mpzqhwctrl);
+ /* restore WALAT/RALAT */
+ writel(mdmisc_val, &mmdc0->mdmisc);
+
debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
readl(&mmdc0->mpwldectrl0));
debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
/* Step 8: Write Mode Registers to Init DDR3 devices */
+ mdelay(1); /* Wait before issuing the first MRS command.
+ * Minimum wait time is (tXPR + 500us),
+ * with max tXPR value 360ns, and 500us wait required after
+ * RESET_n is de-asserted.
+ */
for (cs = 0; cs < sysinfo->ncs; cs++) {
/* MR2 */
val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
-#include <fsl_sec.h>
#include <imx_thermal.h>
#include <mmc.h>
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
setup_serial_number();
return 0;
}
select DM_THERMAL
select MX7D
imply CMD_DM
+ select FSL_CAAM
config TARGET_PICO_IMX7D
bool "pico-imx7d"
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <dm.h>
#include <env.h>
#include <imx_thermal.h>
-#include <fsl_sec.h>
#include <asm/setup.h>
#include <linux/delay.h>
env_set("serial#", serial_string);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
return 0;
}
bool "Support mx7ulp EVK board"
select MX7ULP
select SYS_ARCH_TIMER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
endchoice
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/setup.h>
#include <linux/bitops.h>
+#include <dm.h>
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
return 0;
}
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
return -EIO;
if (container->tag != 0x87 && container->version != 0x0) {
- printf("Wrong container header");
+ printf("Wrong container header\n");
return -ENOENT;
}
if (!container->num_images) {
- printf("Wrong container, no image found");
+ printf("Wrong container, no image found\n");
return -ENOENT;
}
#if defined(CONFIG_SPL_MMC)
/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
switch (get_boot_device()) {
ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev)
{
- u32 offset;
-
- if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_FLEXSPINOR)
- offset = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512;
- else
- offset = image_offset + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;
-
- return offset;
+ return image_offset +
+ (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000);
}
static int is_boot_from_stream_device(u32 boot)
config CM926EJ_S
bool "Core Module for ARM926EJ-STM"
select CPU_ARM926EJS
+ select CM_TCRAM
config CM946ES
bool "Core Module for ARM946E-STM"
select CPU_ARM946ES
+ select CM_MULTIPLE_SSRAM
+ select CM_TCRAM
config CM1136
bool "Core Module for ARM1136JF-STM"
select CPU_ARM1136
+ select CM_TCRAM
endchoice
config SYS_MALLOC_F_LEN
default 0x2000
+config CM_INIT
+ def_bool y
+
+config CM_REMAP
+ def_bool y
+
+config CM_SPD_DETECT
+ def_bool y
+
+config CM_MULTIPLE_SSRAM
+ bool
+
+config CM_TCRAM
+ bool
+
endmenu
#include <dm/root.h>
#if defined(CONFIG_SPL_BUILD)
+#define MCU_CTRL_MMR0_BASE 0x04500000
+#define CTRLMMR_MCU_RST_CTRL 0x04518170
static void ctrl_mmr_unlock(void)
{
/* Unlock all PADCFG_MMR1 module registers */
mmr_unlock(PADCFG_MMR1_BASE, 1);
+ /* Unlock all MCU_CTRL_MMR0 module registers */
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
+
/* Unlock all CTRL_MMR0 module registers */
mmr_unlock(CTRL_MMR0_BASE, 0);
mmr_unlock(CTRL_MMR0_BASE, 1);
mmr_unlock(CTRL_MMR0_BASE, 3);
mmr_unlock(CTRL_MMR0_BASE, 5);
mmr_unlock(CTRL_MMR0_BASE, 6);
-
- /* Unlock all MCU_PADCFG_MMR1 module registers */
- mmr_unlock(MCU_PADCFG_MMR1_BASE, 1);
}
/*
}
#endif
+#if defined(CONFIG_ESM_K3)
+static void enable_mcu_esm_reset(void)
+{
+ /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */
+ u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
+
+ stat &= 0xFFFDFFFF;
+ writel(stat, CTRLMMR_MCU_RST_CTRL);
+}
+#endif
+
void board_init_f(ulong dummy)
{
-#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS)
+#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3)
struct udevice *dev;
int ret;
#endif
/* Output System Firmware version info */
k3_sysfw_print_ver();
+#if defined(CONFIG_ESM_K3)
+ /* Probe/configure ESM0 */
+ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
+ if (ret)
+ printf("esm main init failed: %d\n", ret);
+
+ /* Probe/configure MCUESM */
+ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
+ if (ret)
+ printf("esm mcu init failed: %d\n", ret);
+
+ enable_mcu_esm_reset();
+#endif
+
#if defined(CONFIG_K3_AM64_DDRSS)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
}
}
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
spl_enable_dcache();
}
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
#if defined(CONFIG_SUPPORT_EMMC_BOOT)
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
spl_enable_dcache();
}
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
spl_enable_dcache();
}
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
bool
select ARMADA_38X
+config CUSTOMER_BOARD_SUPPORT
+ bool
+
choice
prompt "Armada XP/375/38x/3700/7K/8K board select"
optional
config TARGET_CONTROLCENTERDC
bool "Support CONTROLCENTERDC"
select 88F6820
+ select CUSTOMER_BOARD_SUPPORT
config TARGET_X530
bool "Support Allied Telesis x530"
* be done, via the bootrom error register. Here the
* MSB marks if the UART mode is active.
*/
- val = readl(CONFIG_BOOTROM_ERR_REG);
+ val = readl(BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
if (boot_device == BOOTROM_ERR_MODE_UART)
#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
/* BootROM error register (also includes some status infos) */
-#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
+#define BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS 28
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
#define BOOTROM_ERR_MODE_UART 0x6
} __packed;
#ifdef CONFIG_SPL_MMC
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
return MMCSD_MODE_RAW;
}
return gd->arch.omap_boot_device;
}
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
return gd->arch.omap_boot_mode;
}
return boot_device;
}
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
return MMCSD_MODE_RAW;
}
#include <errno.h>
#include <init.h>
#include <log.h>
+#include <mach/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
~0);
/* Poll until all idleack to 0 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
- 300000);
+ read_poll_timeout(readl, reg, !reg, 1000, 300000,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK);
} else {
/* set idle request to all bridges */
writel(~0,
writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK, reg,
+ read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
- 1000, 300000);
+ 1000, 300000,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK);
/* Poll until all idlestatus to 1 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLESTATUS, reg,
+ read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
- 1000, 300000);
+ 1000, 300000,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLESTATUS);
/* Reset all bridges (except NOR DDR scheduler & F2S) */
setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
}
#ifdef CONFIG_SPL_MMC
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
}
#ifdef CONFIG_SPL_MMC
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
return BOOT_DEVICE_MMC1;
}
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
return MMCSD_MODE_RAW;
}
---help---
See I2C0_ENABLE help text.
-config I2C2_ENABLE
- bool "Enable I2C/TWI controller 2"
- select CMD_I2C
- ---help---
- See I2C0_ENABLE help text.
-
-if MACH_SUN6I || MACH_SUN7I
-config I2C3_ENABLE
- bool "Enable I2C/TWI controller 3"
- select CMD_I2C
- ---help---
- See I2C0_ENABLE help text.
-endif
-
if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
config R_I2C_ENABLE
bool "Enable the PRCM I2C/TWI controller"
Set this to y to enable the I2C controller which is part of the PRCM.
endif
-if MACH_SUN7I
-config I2C4_ENABLE
- bool "Enable I2C/TWI controller 4"
- select CMD_I2C
- ---help---
- See I2C0_ENABLE help text.
-endif
-
config AXP_GPIO
bool "Enable support for gpio-s on axp PMICs"
depends on AXP_PMIC_BUS
The used address is "bdaddr" if set, and "ethaddr" with the LSB
flipped elsewise.
+source "board/sunxi/Kconfig"
+
endif
config CHIP_DIP_SCAN
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
+ sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
return SUNXI_INVALID_BOOT_SOURCE;
}
+static int sunxi_egon_valid(struct boot_file_head *egon_head)
+{
+ return !memcmp(egon_head->magic, BOOT0_MAGIC, 8); /* eGON.BT0 */
+}
+
+static int sunxi_toc0_valid(struct toc0_main_info *toc0_info)
+{
+ return !memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8); /* TOC0.GLH */
+}
+
static int sunxi_get_boot_source(void)
{
+ struct boot_file_head *egon_head = (void *)SPL_ADDR;
+ struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
+
/*
* On the ARMv5 SoCs, the SPL header in SRAM is overwritten by the
* exception vectors in U-Boot proper, so we won't find any
!IS_ENABLED(CONFIG_SPL_BUILD))
return SUNXI_BOOTED_FROM_MMC0;
- if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
- return SUNXI_INVALID_BOOT_SOURCE;
-
if (IS_ENABLED(CONFIG_MACH_SUNIV))
return suniv_get_boot_source();
- else
- return readb(SPL_ADDR + 0x28);
+ if (sunxi_egon_valid(egon_head))
+ return readb(&egon_head->boot_media);
+ if (sunxi_toc0_valid(toc0_info))
+ return readb(&toc0_info->platform[0]);
+
+ /* Not a valid image, so we must have been booted via FEL. */
+ return SUNXI_INVALID_BOOT_SOURCE;
}
/* The sunxi internal brom will try to loader external bootloader
}
#ifdef CONFIG_SPL_BUILD
-static u32 sunxi_get_spl_size(void)
+uint32_t sunxi_get_spl_size(void)
{
- if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
- return 0;
+ struct boot_file_head *egon_head = (void *)SPL_ADDR;
+ struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
+
+ if (sunxi_egon_valid(egon_head))
+ return readl(&egon_head->length);
+ if (sunxi_toc0_valid(toc0_info))
+ return readl(&toc0_info->length);
- return readl(SPL_ADDR + 0x10);
+ /* Not a valid image, so use the default U-Boot offset. */
+ return 0;
}
/*
{
}
+/*
+ * When booting from an eMMC boot partition, the SPL puts the same boot
+ * source code into SRAM A1 as when loading the SPL from the normal
+ * eMMC user data partition: 0x2. So to know where we have been loaded
+ * from, we repeat the BROM algorithm here: checking for a valid eGON boot
+ * image at offset 0 of a (potentially) selected boot partition.
+ * If any of the conditions is not met, it must have been the eMMC user
+ * data partition.
+ */
+static bool sunxi_valid_emmc_boot(struct mmc *mmc)
+{
+ struct blk_desc *bd = mmc_get_blk_desc(mmc);
+ uint32_t *buffer = (void *)(uintptr_t)CONFIG_SYS_TEXT_BASE;
+ struct boot_file_head *egon_head = (void *)buffer;
+ int bootpart = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+ uint32_t spl_size, emmc_checksum, chksum = 0;
+ ulong count;
+
+ /* The BROM requires BOOT_ACK to be enabled. */
+ if (!EXT_CSD_EXTRACT_BOOT_ACK(mmc->part_config))
+ return false;
+
+ /*
+ * The BOOT_BUS_CONDITION register must be 4-bit SDR, with (0x09)
+ * or without (0x01) high speed timings.
+ */
+ if ((mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x01 &&
+ (mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x09)
+ return false;
+
+ /* Partition 0 is the user data partition, bootpart must be 1 or 2. */
+ if (bootpart != 1 && bootpart != 2)
+ return false;
+
+ /* Failure to switch to the boot partition is fatal. */
+ if (mmc_switch_part(mmc, bootpart))
+ return false;
+
+ /* Read the first block to do some sanity checks on the eGON header. */
+ count = blk_dread(bd, 0, 1, buffer);
+ if (count != 1 || !sunxi_egon_valid(egon_head))
+ return false;
+
+ /* Read the rest of the SPL now we know it's halfway sane. */
+ spl_size = buffer[4];
+ count = blk_dread(bd, 1, DIV_ROUND_UP(spl_size, bd->blksz) - 1,
+ buffer + bd->blksz / 4);
+
+ /* Save the checksum and replace it with the "stamp value". */
+ emmc_checksum = buffer[3];
+ buffer[3] = 0x5f0a6c39;
+
+ /* The checksum is a simple ignore-carry addition of all words. */
+ for (count = 0; count < spl_size / 4; count++)
+ chksum += buffer[count];
+
+ debug("eMMC boot part SPL checksum: stored: 0x%08x, computed: 0x%08x\n",
+ emmc_checksum, chksum);
+
+ return emmc_checksum == chksum;
+}
+
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
+{
+ static u32 result = ~0;
+
+ if (result != ~0)
+ return result;
+
+ result = MMCSD_MODE_RAW;
+ if (!IS_SD(mmc) && IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
+ if (sunxi_valid_emmc_boot(mmc))
+ result = MMCSD_MODE_EMMCBOOT;
+ else
+ mmc_switch_part(mmc, 0);
+ }
+
+ debug("%s(): %s part\n", __func__,
+ result == MMCSD_MODE_RAW ? "user" : "boot");
+
+ return result;
+}
+
void board_init_f(ulong dummy)
{
sunxi_sram_init();
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) {
+ /* this seems to enable PLLs on H616 */
+ setbits_le32(&prcm->sys_pwroff_gating, 0x10);
+ setbits_le32(&prcm->res_cal_ctrl, 2);
+ }
+
+ clrbits_le32(&prcm->res_cal_ctrl, 1);
+ setbits_le32(&prcm->res_cal_ctrl, 1);
- /* this seems to enable PLLs on H616 */
- if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
- setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
+ /* set key field for ldo enable */
+ setbits_le32(&prcm->pll_ldo_cfg, 0xA7000000);
+ /* set PLL VDD LDO output to 1.14 V */
+ setbits_le32(&prcm->pll_ldo_cfg, 0x60000);
+ }
clock_set_pll1(408000000);
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/kconfig.h>
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
unsigned long size;
- /* RES_CAL_CTRL_REG in BSP U-boot*/
- setbits_le32(0x7010310, BIT(8));
- clrbits_le32(0x7010318, 0x3f);
+ setbits_le32(&prcm->res_cal_ctrl, BIT(8));
+ clrbits_le32(&prcm->ohms240, 0x3f);
mctl_auto_detect_rank_width(¶);
mctl_auto_detect_dram_size(¶);
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/kconfig.h>
unsigned long sunxi_dram_init(void)
{
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
.type = SUNXI_DRAM_TYPE_DDR3,
};
unsigned long size;
- setbits_le32(0x7010310, BIT(8));
- clrbits_le32(0x7010318, 0x3f);
+ setbits_le32(&prcm->res_cal_ctrl, BIT(8));
+ clrbits_le32(&prcm->ohms240, 0x3f);
mctl_auto_detect_rank_width(¶);
mctl_auto_detect_dram_size(¶);
int ret = 0;
struct image_header *header;
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
- int load_offset = readl(SPL_ADDR + 0x10);
+ uint32_t load_offset = sunxi_get_spl_size();
- load_offset = max(load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS);
+ load_offset = max_t(uint32_t, load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS);
spi0_init();
USB controller when U-Boot boots to avoid leaving a stale USB device
present.
+config CI_UDC_HAS_HOSTPC
+ def_bool y
+ depends on CI_UDC && !TEGRA20
+
config SYS_MALLOC_F_LEN
default 0x1800
#include <mmc.h>
#include <spl.h>
-u32 spl_mmc_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
- struct mmc *mmc;
-
/*
* work around a bug in the Boot ROM of LD4, Pro4, and sLD8:
*
* Fixup mmc->part_config here because it is used to determine the
* partition which the U-Boot image is read from.
*/
- mmc = find_mmc_device(0);
mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK);
mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE;
endchoice
+config DCACHE
+ bool "Enable dcache support"
+ default y
+
+config ICACHE
+ bool "Enable icache support"
+ default y
+
source "board/xilinx/Kconfig"
source "board/xilinx/microblaze-generic/Kconfig"
/* External AHB slave2 (FUSBH200) */
#define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000
-/* DEBUG LED */
-#define CONFIG_DEBUG_LED 0x902FFFFC
-
/* APB Device definitions */
/* Power Management Unit */
/* PWM - Pulse Width Modulator Controller */
#define CONFIG_FTPWM010_BASE 0x94F00000
-/* Debug LED */
-#define CONFIG_DEBUG_LED 0x902FFFFC
/* Power Management Unit */
#define CONFIG_FTPMU010_BASE 0x98100000
menu "mpc83xx CPU"
depends on MPC83xx
+config DEFAULT_IMMR
+ hex
+ default 0xFF400000
+
config E300
def_bool y
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
#endif
+#include <dm.h>
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
#endif
#ifdef CONFIG_FSL_CAAM
- sec_init();
-
#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
return 0;
}
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
+
+ return 0;
+}
+#endif
+
void arch_preboot_os(void)
{
u32 msr;
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.2-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v5.2-rtic",
+ "fsl,sec-v5.0-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman3l-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-fman3l-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2021 NXP
+ *
+ * Gaurav Jain <gaurav.jain@nxp.com>
+ */
+
+#ifndef _U_BOOT_PPC_H_
+#define _U_BOOT_PPC_H_
+
+#ifndef __ASSEMBLY__
+
+int arch_misc_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _U_BOOT_PPC_H_ */
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
#include <asm/ppc.h>
+#include <asm/u-boot-ppc.h>
#endif /* __U_BOOT_H__ */
The Andes PLIC block holds memory-mapped claim and pending registers
associated with software interrupt.
-config SYS_MALLOC_F_LEN
- default 0x1000
-
config SMP
bool "Symmetric Multi-Processing"
depends on SBI_V01 || !RISCV_SMODE
SBI_EXT_RFENCE = 0x52464E43,
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
+ SBI_EXT_PMU = 0x504D55,
};
enum sbi_ext_base_fid {
int sbi_get_impl_id(void);
int sbi_get_impl_version(long *version);
int sbi_probe_extension(int ext);
+int sbi_get_mvendorid(long *mvendorid);
+int sbi_get_marchid(long *marchid);
+int sbi_get_mimpid(long *mimpid);
void sbi_srst_reset(unsigned long type, unsigned long reason);
#endif
return -ENOTSUPP;
}
+/**
+ * sbi_get_mvendorid() - get machine vendor ID
+ *
+ * @mimpid: on return machine vendor ID
+ * Return: 0 on success
+ */
+int sbi_get_mvendorid(long *mvendorid)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID,
+ 0, 0, 0, 0, 0, 0);
+ if (ret.error)
+ return -ENOTSUPP;
+
+ if (mvendorid)
+ *mvendorid = ret.value;
+
+ return 0;
+}
+
+/**
+ * sbi_get_marchid() - get machine architecture ID
+ *
+ * @mimpid: on return machine architecture ID
+ * Return: 0 on success
+ */
+int sbi_get_marchid(long *marchid)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID,
+ 0, 0, 0, 0, 0, 0);
+
+ if (ret.error)
+ return -ENOTSUPP;
+
+ if (marchid)
+ *marchid = ret.value;
+
+ return 0;
+}
+
+/**
+ * sbi_get_mimpid() - get machine implementation ID
+ *
+ * @mimpid: on return machine implementation ID
+ * Return: 0 on success
+ */
+int sbi_get_mimpid(long *mimpid)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID,
+ 0, 0, 0, 0, 0, 0);
+
+ if (ret.error)
+ return -ENOTSUPP;
+
+ if (mimpid)
+ *mimpid = ret.value;
+
+ return 0;
+}
+
/**
* sbi_srst_reset() - invoke system reset extension
*
int colour; /* Text colour to use for output, -1 for none */
};
+/**
+ * sandbox_serial_written() - Get the total number of characters written
+ *
+ * This returns the number of characters written by the sandbox serial
+ * device. It is intended for performing tests of the serial subsystem
+ * where a console buffer cannot be used. The absolute number should not be
+ * relied upon; call this function twice and compare the difference.
+ *
+ * Return: The number of characters written
+ */
+size_t sandbox_serial_written(void);
+
+/**
+ * sandbox_serial_endisable() - Enable or disable serial output
+ * @enabled: Whether serial output should be enabled or not
+ *
+ * This allows tests to enable or disable the sandbox serial output. All
+ * processes relating to writing output (except the actual writing) will be
+ * performed.
+ */
+void sandbox_serial_endisable(bool enabled);
+
/**
* struct sandbox_serial_priv - Private data for this driver
*
fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR;
}
-static int apl_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
{
- struct acpi_table_header *header;
- struct acpi_fadt *fadt;
+ struct acpi_table_header *header = &fadt->header;
- fadt = ctx->current;
- acpi_fadt_common(fadt, ctx->facs, ctx->dsdt);
+ acpi_fadt_common(fadt, facs, dsdt);
intel_acpi_fill_fadt(fadt);
fill_fadt(fadt);
- header = &fadt->header;
header->checksum = table_compute_checksum(fadt, header->length);
-
- acpi_add_table(ctx, fadt);
-
- acpi_inc(ctx, sizeof(struct acpi_fadt));
-
- return 0;
}
-ACPI_WRITER(5fadt, "FACS", apl_write_fadt, 0);
int apl_acpi_fill_dmar(struct acpi_ctx *ctx)
{
#include <asm/arch/iomap.h>
#include <dm/uclass-internal.h>
-static int baytrail_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
{
- struct acpi_table_header *header;
- struct acpi_fadt *fadt;
-
- fadt = ctx->current;
- header = &fadt->header;
+ struct acpi_table_header *header = &(fadt->header);
u16 pmbase = ACPI_BASE_ADDRESS;
- memset(fadt, '\0', sizeof(struct acpi_fadt));
+ memset((void *)fadt, 0, sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt);
header->revision = 4;
- fadt->firmware_ctrl = (u32)ctx->facs;
- fadt->dsdt = (u32)ctx->dsdt;
+ fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
fadt->preferred_pm_profile = ACPI_PM_MOBILE;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctl_l = (u32)ctx->facs;
+ fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)ctx->dsdt;
+ fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = table_compute_checksum(fadt, header->length);
-
- acpi_add_table(ctx, fadt);
-
- acpi_inc(ctx, sizeof(struct acpi_fadt));
-
- return 0;
}
-ACPI_WRITER(5fadt, "FACP", baytrail_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
-static int quark_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
{
+ struct acpi_table_header *header = &(fadt->header);
u16 pmbase = ACPI_PM1_BASE_ADDRESS;
- struct acpi_table_header *header;
- struct acpi_fadt *fadt;
- fadt = ctx->current;
- header = &fadt->header;
-
- memset(fadt, '\0', sizeof(struct acpi_fadt));
+ memset((void *)fadt, 0, sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt);
header->revision = 4;
- fadt->firmware_ctrl = (u32)ctx->facs;
- fadt->dsdt = (u32)ctx->dsdt;
+ fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctl_l = (u32)ctx->facs;
+ fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)ctx->dsdt;
+ fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = table_compute_checksum(fadt, header->length);
-
- acpi_add_table(ctx, fadt);
-
- acpi_inc(ctx, sizeof(struct acpi_fadt));
-
- return 0;
}
-ACPI_WRITER(5fadt, "FACP", quark_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
#include <asm/arch/iomap.h>
#include <dm/uclass-internal.h>
-static int tangier_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
{
- struct acpi_table_header *header;
- struct acpi_fadt *fadt;
+ struct acpi_table_header *header = &(fadt->header);
- fadt = ctx->current;
- header = &fadt->header;
-
- memset(fadt, '\0', sizeof(struct acpi_fadt));
+ memset((void *)fadt, 0, sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt);
header->revision = 6;
- fadt->firmware_ctrl = (u32)ctx->facs;
- fadt->dsdt = (u32)ctx->dsdt;
+ fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT |
fadt->minor_revision = 2;
- fadt->x_firmware_ctl_l = (u32)ctx->facs;
+ fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)ctx->dsdt;
+ fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
header->checksum = table_compute_checksum(fadt, header->length);
-
- acpi_inc(ctx, sizeof(struct acpi_fadt));
-
- return 0;
}
-ACPI_WRITER(5fadt, "FACP", tangier_write_fadt, 0);
u32 acpi_fill_madt(u32 current)
{
/* These can be used by the target port */
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt);
int acpi_create_madt_lapics(u32 current);
int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
u32 addr, u32 gsi_base);
/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
#define CB_TABLE_ADDR 0x800
-/**
- * table_compute_checksum() - Compute a table checksum
- *
- * This computes an 8-bit checksum for the configuration table.
- * All bytes in the configuration table, including checksum itself and
- * reserved bytes must add up to zero.
- *
- * @v: configuration table base address
- * @len: configuration table size
- * @return: the 8-bit checksum
- */
-u8 table_compute_checksum(void *v, int len);
-
/**
* table_fill_string() - Fill a string with pad in the configuration table
*
}
ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0);
+static int acpi_write_fadt(struct acpi_ctx *ctx,
+ const struct acpi_writer *entry)
+{
+ struct acpi_fadt *fadt;
+
+ fadt = ctx->current;
+ acpi_create_fadt(fadt, ctx->facs, ctx->dsdt);
+ acpi_add_table(ctx, fadt);
+
+ acpi_inc(ctx, sizeof(struct acpi_fadt));
+
+ return 0;
+}
+ACPI_WRITER(5fact, "FADT", acpi_write_fadt, 0);
+
/**
* acpi_write_hpet() - Write out a HPET table
*
if TARGET_ADP_AG101P
+config DEBUG_LED
+ hex
+ default 0x902FFFFC
+
config SYS_CPU
default "n1213"
#include <init.h>
#include <net.h>
#include <netdev.h>
+#include <armcoremodule.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/platform_data/serial_pl01x.h>
*/
#include <config.h>
+#include <armcoremodule.h>
/* Reset using CM control register */
.global reset_cpu
/* set the desired CM specific value */
mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
- orr r2,r2,#CMMASK_INIT_102
-#else
-
#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
!defined (CONFIG_CM940T)
#endif /* CMxx6 code */
-#endif /* ARM102xxE value */
-
/* read CM_INIT */
mov r0, #CM_BASE
ldr r1, [r0, #OS_INIT]
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9260ek.o
-obj-$(CONFIG_AT91_LED) += led.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-#include <status_led.h>
-
-void coloured_LED_init(void)
-{
- /* Clock is enabled in board_early_init_f() */
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
-
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
-}
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9261ek.o
-obj-$(CONFIG_AT91_LED) += led.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/arch/at91sam9261.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/clk.h>
-#include <asm/io.h>
-
-void coloured_LED_init(void)
-{
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_PIOA);
-
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
- at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
-
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
- at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
-}
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9263ek.o
-obj-$(CONFIG_AT91_LED) += led.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam9263.h>
-#include <asm/arch/clk.h>
-
-void coloured_LED_init(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
-
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
- at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
-
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
- at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
-}
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9m10g45ek.o
-obj-(CONFIG_AT91_LED) += led.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/io.h>
-#include <asm/arch/at91sam9g45.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-
-void coloured_LED_init(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIODE);
-
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
-
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
-}
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9rlek.o
-obj-$(CONFIG_AT91_LED) += led.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/arch/at91sam9rl.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-void coloured_LED_init(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOD);
-
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
- at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
-
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
- at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
-}
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2022 Logic PD, Inc. dba Beacon EmbeddedWorks
*/
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
#include <asm/global_data.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-
DECLARE_GLOBAL_DATA_PTR;
-#if IS_ENABLED(CONFIG_FEC_MXC)
-static int setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Use 125M anatop REF_CLK1 for ENET1, not from external */
- clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- /* enable rgmii rxc skew and phy mode select to RGMII copper */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
-
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
-}
-#endif
-
int board_init(void)
{
- if (IS_ENABLED(CONFIG_FEC_MXC))
- setup_fec();
-
return 0;
}
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2022 Logic PD, Inc. dba Beacon EmbeddedWorks
*/
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
-#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-#if IS_ENABLED(CONFIG_FEC_MXC)
-static int setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Use 125M anatop REF_CLK1 for ENET1, not from external */
- clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- /* enable rgmii rxc skew and phy mode select to RGMII copper */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
-
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
-}
-#endif
-
int board_init(void)
{
- if (IS_ENABLED(CONFIG_FEC_MXC))
- setup_fec();
-
return 0;
}
--- /dev/null
+config BSH_SMM_S2_DDR3L_256
+ bool "BSH SMM S2 DDR3L 256 MiB RAM support"
+
+config BSH_SMM_S2_DDR3L_512
+ bool "BSH SMM S2 DDR3L 512 MiB RAM support"
+
+if TARGET_IMX8MN_BSH_SMM_S2
+
+config SYS_BOARD
+ default "imx8mn_smm_s2"
+
+config SYS_VENDOR
+ default "bsh"
+
+config IMX_CONFIG
+ default "board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg"
+
+config SYS_CONFIG_NAME
+ default "imx8mn_bsh_smm_s2"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BSH_SMM_S2_DDR3L_256
+
+source "board/freescale/common/Kconfig"
+
+endif
+
+if TARGET_IMX8MN_BSH_SMM_S2PRO
+
+config SYS_BOARD
+ default "imx8mn_smm_s2"
+
+config SYS_VENDOR
+ default "bsh"
+
+config IMX_CONFIG
+ default "board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg"
+
+config SYS_CONFIG_NAME
+ default "imx8mn_bsh_smm_s2pro"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BSH_SMM_S2_DDR3L_512
+
+source "board/freescale/common/Kconfig"
+
+endif
--- /dev/null
+ARM i.MX8MN BSH SMM S2 BOARDS
+M: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
+M: Michael Trimarchi <michael@amarulasolutions.com>
+S: Maintained
+F: arch/arm/dts/imx8mn-bsh-smm-s2*
+F: board/bsh/imx8mn_smm_s2/
+F: configs/imx8mn_bsh_smm_s2*
+F: include/configs/imx8mn_bsh_smm_s2*
--- /dev/null
+#
+# Copyright 2021 Collabora Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mn_smm_s2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_BSH_SMM_S2_DDR3L_256) += ddr3l_timing_256m.o
+obj-$(CONFIG_BSH_SMM_S2_DDR3L_512) += ddr3l_timing_512m.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ * For imx_v2019.04_5.4.x and above version:
+ * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x20 },
+ { 0x3d400000, 0xa1040001 },
+ { 0x3d400064, 0x610040 },
+ { 0x3d4000d0, 0xc00200c5 },
+ { 0x3d4000d4, 0x1000b },
+ { 0x3d4000dc, 0x1d700004 },
+ { 0x3d4000e0, 0x180000 },
+ { 0x3d4000e4, 0x90000 },
+ { 0x3d4000f0, 0x0 },
+ { 0x3d4000f4, 0xee5 },
+ { 0x3d400100, 0xc101b0e },
+ { 0x3d400104, 0x30314 },
+ { 0x3d400108, 0x4060509 },
+ { 0x3d40010c, 0x2006 },
+ { 0x3d400110, 0x6020306 },
+ { 0x3d400114, 0x4040302 },
+ { 0x3d400120, 0x909 },
+ { 0x3d400180, 0x40800020 },
+ { 0x3d400184, 0xc350 },
+ { 0x3d400190, 0x3868203 },
+ { 0x3d400194, 0x20303 },
+ { 0x3d4001b4, 0x603 },
+ { 0x3d400198, 0x7000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001a0, 0x400018 },
+ { 0x3d4001a4, 0x5003c },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d400200, 0x1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400208, 0x0 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0xf0f0707 },
+ { 0x3d400240, 0x600060c },
+ { 0x3d400244, 0x1323 },
+ { 0x3d400400, 0x100 },
+ { 0x3d400250, 0x7ab50b07 },
+ { 0x3d400254, 0x22 },
+ { 0x3d40025c, 0x7b00665e },
+ { 0x3d400264, 0xb0000040 },
+ { 0x3d40026c, 0x50000a0c },
+ { 0x3d400300, 0x17 },
+ { 0x3d40036c, 0x10000 },
+ { 0x3d400404, 0x3051 },
+ { 0x3d400408, 0x61d2 },
+ { 0x3d400494, 0xe00 },
+ { 0x3d400498, 0x7ff },
+ { 0x3d40049c, 0xe00 },
+ { 0x3d4004a0, 0x7ff },
+ { 0x3d402064, 0x28001b },
+ { 0x3d4020dc, 0x12200004 },
+ { 0x3d4020e0, 0x0 },
+ { 0x3d402100, 0x7090b07 },
+ { 0x3d402104, 0x20209 },
+ { 0x3d402108, 0x3030407 },
+ { 0x3d40210c, 0x2006 },
+ { 0x3d402110, 0x3020203 },
+ { 0x3d402114, 0x3030202 },
+ { 0x3d402120, 0x909 },
+ { 0x3d402180, 0x40800020 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x20303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d402240, 0x6000604 },
+ { 0x3d4020f4, 0xee5 },
+ { 0x3d400028, 0x1 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x1005f, 0x3ff },
+ { 0x1015f, 0x3ff },
+ { 0x1105f, 0x3ff },
+ { 0x1115f, 0x3ff },
+ { 0x11005f, 0x3ff },
+ { 0x11015f, 0x3ff },
+ { 0x11105f, 0x3ff },
+ { 0x11115f, 0x3ff },
+ { 0x55, 0x3ff },
+ { 0x1055, 0x3ff },
+ { 0x2055, 0x3ff },
+ { 0x3055, 0x3ff },
+ { 0x4055, 0xff },
+ { 0x5055, 0xff },
+ { 0x6055, 0x3ff },
+ { 0x7055, 0x3ff },
+ { 0x8055, 0x3ff },
+ { 0x9055, 0x3ff },
+ { 0x200c5, 0xb },
+ { 0x1200c5, 0x7 },
+ { 0x2002e, 0x1 },
+ { 0x12002e, 0x1 },
+ { 0x20024, 0x0 },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x0 },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0xa },
+ { 0x120056, 0xa },
+ { 0x1004d, 0x208 },
+ { 0x1014d, 0x208 },
+ { 0x1104d, 0x208 },
+ { 0x1114d, 0x208 },
+ { 0x11004d, 0x208 },
+ { 0x11014d, 0x208 },
+ { 0x11104d, 0x208 },
+ { 0x11114d, 0x208 },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x0 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x190 },
+ { 0x120008, 0xa7 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x32c },
+ { 0x10043, 0x581 },
+ { 0x10143, 0x581 },
+ { 0x11043, 0x581 },
+ { 0x11143, 0x581 },
+ { 0x1200b2, 0x32c },
+ { 0x110043, 0x581 },
+ { 0x110143, 0x581 },
+ { 0x111043, 0x581 },
+ { 0x111143, 0x581 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x010082, 0x0},
+ {0x110082, 0x0},
+ {0x210082, 0x0},
+ {0x010182, 0x0},
+ {0x110182, 0x0},
+ {0x210182, 0x0},
+ {0x010083, 0x0},
+ {0x110083, 0x0},
+ {0x210083, 0x0},
+ {0x010183, 0x0},
+ {0x110183, 0x0},
+ {0x210183, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x011082, 0x0},
+ {0x111082, 0x0},
+ {0x211082, 0x0},
+ {0x011182, 0x0},
+ {0x111182, 0x0},
+ {0x211182, 0x0},
+ {0x011083, 0x0},
+ {0x111083, 0x0},
+ {0x211083, 0x0},
+ {0x011183, 0x0},
+ {0x111183, 0x0},
+ {0x211183, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0100d2, 0x0},
+ {0x1100d2, 0x0},
+ {0x2100d2, 0x0},
+ {0x0101d2, 0x0},
+ {0x1101d2, 0x0},
+ {0x2101d2, 0x0},
+ {0x0100d3, 0x0},
+ {0x1100d3, 0x0},
+ {0x2100d3, 0x0},
+ {0x0101d3, 0x0},
+ {0x1101d3, 0x0},
+ {0x2101d3, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x0110d2, 0x0},
+ {0x1110d2, 0x0},
+ {0x2110d2, 0x0},
+ {0x0111d2, 0x0},
+ {0x1111d2, 0x0},
+ {0x2111d2, 0x0},
+ {0x0110d3, 0x0},
+ {0x1110d3, 0x0},
+ {0x2110d3, 0x0},
+ {0x0111d3, 0x0},
+ {0x1111d3, 0x0},
+ {0x2111d3, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x01006a, 0x0},
+ {0x01016a, 0x0},
+ {0x01026a, 0x0},
+ {0x01036a, 0x0},
+ {0x01046a, 0x0},
+ {0x01056a, 0x0},
+ {0x01066a, 0x0},
+ {0x01076a, 0x0},
+ {0x01086a, 0x0},
+ {0x01006b, 0x0},
+ {0x01016b, 0x0},
+ {0x01026b, 0x0},
+ {0x01036b, 0x0},
+ {0x01046b, 0x0},
+ {0x01056b, 0x0},
+ {0x01066b, 0x0},
+ {0x01076b, 0x0},
+ {0x01086b, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01106a, 0x0},
+ {0x01116a, 0x0},
+ {0x01126a, 0x0},
+ {0x01136a, 0x0},
+ {0x01146a, 0x0},
+ {0x01156a, 0x0},
+ {0x01166a, 0x0},
+ {0x01176a, 0x0},
+ {0x01186a, 0x0},
+ {0x01106b, 0x0},
+ {0x01116b, 0x0},
+ {0x01126b, 0x0},
+ {0x01136b, 0x0},
+ {0x01146b, 0x0},
+ {0x01156b, 0x0},
+ {0x01166b, 0x0},
+ {0x01176b, 0x0},
+ {0x01186b, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01008e, 0x0},
+ {0x11008e, 0x0},
+ {0x21008e, 0x0},
+ {0x01018e, 0x0},
+ {0x11018e, 0x0},
+ {0x21018e, 0x0},
+ {0x01008f, 0x0},
+ {0x11008f, 0x0},
+ {0x21008f, 0x0},
+ {0x01018f, 0x0},
+ {0x11018f, 0x0},
+ {0x21018f, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x01108e, 0x0},
+ {0x11108e, 0x0},
+ {0x21108e, 0x0},
+ {0x01118e, 0x0},
+ {0x11118e, 0x0},
+ {0x21118e, 0x0},
+ {0x01108f, 0x0},
+ {0x11108f, 0x0},
+ {0x21108f, 0x0},
+ {0x01118f, 0x0},
+ {0x11118f, 0x0},
+ {0x21118f, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0100c2, 0x0},
+ {0x1100c2, 0x0},
+ {0x2100c2, 0x0},
+ {0x0101c2, 0x0},
+ {0x1101c2, 0x0},
+ {0x2101c2, 0x0},
+ {0x0102c2, 0x0},
+ {0x1102c2, 0x0},
+ {0x2102c2, 0x0},
+ {0x0103c2, 0x0},
+ {0x1103c2, 0x0},
+ {0x2103c2, 0x0},
+ {0x0104c2, 0x0},
+ {0x1104c2, 0x0},
+ {0x2104c2, 0x0},
+ {0x0105c2, 0x0},
+ {0x1105c2, 0x0},
+ {0x2105c2, 0x0},
+ {0x0106c2, 0x0},
+ {0x1106c2, 0x0},
+ {0x2106c2, 0x0},
+ {0x0107c2, 0x0},
+ {0x1107c2, 0x0},
+ {0x2107c2, 0x0},
+ {0x0108c2, 0x0},
+ {0x1108c2, 0x0},
+ {0x2108c2, 0x0},
+ {0x0100c3, 0x0},
+ {0x1100c3, 0x0},
+ {0x2100c3, 0x0},
+ {0x0101c3, 0x0},
+ {0x1101c3, 0x0},
+ {0x2101c3, 0x0},
+ {0x0102c3, 0x0},
+ {0x1102c3, 0x0},
+ {0x2102c3, 0x0},
+ {0x0103c3, 0x0},
+ {0x1103c3, 0x0},
+ {0x2103c3, 0x0},
+ {0x0104c3, 0x0},
+ {0x1104c3, 0x0},
+ {0x2104c3, 0x0},
+ {0x0105c3, 0x0},
+ {0x1105c3, 0x0},
+ {0x2105c3, 0x0},
+ {0x0106c3, 0x0},
+ {0x1106c3, 0x0},
+ {0x2106c3, 0x0},
+ {0x0107c3, 0x0},
+ {0x1107c3, 0x0},
+ {0x2107c3, 0x0},
+ {0x0108c3, 0x0},
+ {0x1108c3, 0x0},
+ {0x2108c3, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x0110c2, 0x0},
+ {0x1110c2, 0x0},
+ {0x2110c2, 0x0},
+ {0x0111c2, 0x0},
+ {0x1111c2, 0x0},
+ {0x2111c2, 0x0},
+ {0x0112c2, 0x0},
+ {0x1112c2, 0x0},
+ {0x2112c2, 0x0},
+ {0x0113c2, 0x0},
+ {0x1113c2, 0x0},
+ {0x2113c2, 0x0},
+ {0x0114c2, 0x0},
+ {0x1114c2, 0x0},
+ {0x2114c2, 0x0},
+ {0x0115c2, 0x0},
+ {0x1115c2, 0x0},
+ {0x2115c2, 0x0},
+ {0x0116c2, 0x0},
+ {0x1116c2, 0x0},
+ {0x2116c2, 0x0},
+ {0x0117c2, 0x0},
+ {0x1117c2, 0x0},
+ {0x2117c2, 0x0},
+ {0x0118c2, 0x0},
+ {0x1118c2, 0x0},
+ {0x2118c2, 0x0},
+ {0x0110c3, 0x0},
+ {0x1110c3, 0x0},
+ {0x2110c3, 0x0},
+ {0x0111c3, 0x0},
+ {0x1111c3, 0x0},
+ {0x2111c3, 0x0},
+ {0x0112c3, 0x0},
+ {0x1112c3, 0x0},
+ {0x2112c3, 0x0},
+ {0x0113c3, 0x0},
+ {0x1113c3, 0x0},
+ {0x2113c3, 0x0},
+ {0x0114c3, 0x0},
+ {0x1114c3, 0x0},
+ {0x2114c3, 0x0},
+ {0x0115c3, 0x0},
+ {0x1115c3, 0x0},
+ {0x2115c3, 0x0},
+ {0x0116c3, 0x0},
+ {0x1116c3, 0x0},
+ {0x2116c3, 0x0},
+ {0x0117c3, 0x0},
+ {0x1117c3, 0x0},
+ {0x2117c3, 0x0},
+ {0x0118c3, 0x0},
+ {0x1118c3, 0x0},
+ {0x2118c3, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x283c },
+ { 0x54006, 0x140 },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x1d70 },
+ { 0x54030, 0x4 },
+ { 0x54031, 0x18 },
+ { 0x5403a, 0x1323 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x29c },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x283c },
+ { 0x54006, 0x140 },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x1220 },
+ { 0x54030, 0x4 },
+ { 0x5403a, 0x1323 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x2 },
+ { 0x90033, 0x10 },
+ { 0x90034, 0x139 },
+ { 0x90035, 0xb },
+ { 0x90036, 0x7c0 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0x44 },
+ { 0x90039, 0x633 },
+ { 0x9003a, 0x159 },
+ { 0x9003b, 0x14f },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x47 },
+ { 0x9003f, 0x633 },
+ { 0x90040, 0x149 },
+ { 0x90041, 0x4f },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x179 },
+ { 0x90044, 0x8 },
+ { 0x90045, 0xe0 },
+ { 0x90046, 0x109 },
+ { 0x90047, 0x0 },
+ { 0x90048, 0x7c8 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x1 },
+ { 0x9004c, 0x8 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x45a },
+ { 0x9004f, 0x9 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x448 },
+ { 0x90052, 0x109 },
+ { 0x90053, 0x40 },
+ { 0x90054, 0x633 },
+ { 0x90055, 0x179 },
+ { 0x90056, 0x1 },
+ { 0x90057, 0x618 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40c0 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x149 },
+ { 0x9005c, 0x8 },
+ { 0x9005d, 0x4 },
+ { 0x9005e, 0x48 },
+ { 0x9005f, 0x4040 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x0 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x40 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x10 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x18 },
+ { 0x9006b, 0x0 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x78 },
+ { 0x9006e, 0x549 },
+ { 0x9006f, 0x633 },
+ { 0x90070, 0x159 },
+ { 0x90071, 0xd49 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0x94a },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x441 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x149 },
+ { 0x9007a, 0x42 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x1 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x0 },
+ { 0x90081, 0xe0 },
+ { 0x90082, 0x109 },
+ { 0x90083, 0xa },
+ { 0x90084, 0x10 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0x9 },
+ { 0x90087, 0x3c0 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x159 },
+ { 0x9008c, 0x18 },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x0 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x18 },
+ { 0x90093, 0x4 },
+ { 0x90094, 0x48 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x58 },
+ { 0x90098, 0xb },
+ { 0x90099, 0x10 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x1 },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x5 },
+ { 0x9009f, 0x7c0 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x0 },
+ { 0x900a2, 0x8140 },
+ { 0x900a3, 0x10c },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x8138 },
+ { 0x900a6, 0x10c },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7c8 },
+ { 0x900a9, 0x101 },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x448 },
+ { 0x900ac, 0x109 },
+ { 0x900ad, 0xf },
+ { 0x900ae, 0x7c0 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x47 },
+ { 0x900b1, 0x630 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x8 },
+ { 0x900b4, 0x618 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0xe0 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x0 },
+ { 0x900ba, 0x7c8 },
+ { 0x900bb, 0x109 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x8140 },
+ { 0x900be, 0x10c },
+ { 0x900bf, 0x0 },
+ { 0x900c0, 0x1 },
+ { 0x900c1, 0x8 },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x8 },
+ { 0x900c5, 0x8 },
+ { 0x900c6, 0x7c8 },
+ { 0x900c7, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x90026, 0x2b },
+ { 0x2000b, 0x32 },
+ { 0x2000c, 0x64 },
+ { 0x2000d, 0x3e8 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x14 },
+ { 0x12000c, 0x26 },
+ { 0x12000d, 0x1a1 },
+ { 0x12000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0xffff },
+ { 0x90013, 0x6152 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 667mts 1D */
+ .drate = 667,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 1600, 667, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ * For imx_v2019.04_5.4.x and above version:
+ * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x20 },
+ { 0x3d400000, 0xa1040001 },
+ { 0x3d400064, 0x610068 },
+ { 0x3d4000d0, 0xc00200c5 },
+ { 0x3d4000d4, 0x1000b },
+ { 0x3d4000dc, 0x1d700004 },
+ { 0x3d4000e0, 0x180000 },
+ { 0x3d4000e4, 0x90000 },
+ { 0x3d4000f0, 0x0 },
+ { 0x3d4000f4, 0xee5 },
+ { 0x3d400100, 0xc101b0e },
+ { 0x3d400104, 0x30314 },
+ { 0x3d400108, 0x4060509 },
+ { 0x3d40010c, 0x2006 },
+ { 0x3d400110, 0x6020306 },
+ { 0x3d400114, 0x4040302 },
+ { 0x3d400120, 0x909 },
+ { 0x3d400180, 0x40800020 },
+ { 0x3d400184, 0xc350 },
+ { 0x3d400190, 0x3868203 },
+ { 0x3d400194, 0x20303 },
+ { 0x3d4001b4, 0x603 },
+ { 0x3d400198, 0x7000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001a0, 0x400018 },
+ { 0x3d4001a4, 0x5003c },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d400200, 0x1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400208, 0x0 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0xf070707 },
+ { 0x3d400240, 0x600060c },
+ { 0x3d400244, 0x1323 },
+ { 0x3d400400, 0x100 },
+ { 0x3d400250, 0x7ab50b07 },
+ { 0x3d400254, 0x22 },
+ { 0x3d40025c, 0x7b00665e },
+ { 0x3d400264, 0xb0000040 },
+ { 0x3d40026c, 0x50000a0c },
+ { 0x3d400300, 0x17 },
+ { 0x3d40036c, 0x10000 },
+ { 0x3d400404, 0x3051 },
+ { 0x3d400408, 0x61d2 },
+ { 0x3d400494, 0xe00 },
+ { 0x3d400498, 0x7ff },
+ { 0x3d40049c, 0xe00 },
+ { 0x3d4004a0, 0x7ff },
+ { 0x3d402064, 0x28003c },
+ { 0x3d4020dc, 0x12200004 },
+ { 0x3d4020e0, 0x0 },
+ { 0x3d402100, 0x7090b07 },
+ { 0x3d402104, 0x20209 },
+ { 0x3d402108, 0x3030407 },
+ { 0x3d40210c, 0x2006 },
+ { 0x3d402110, 0x3020203 },
+ { 0x3d402114, 0x3030202 },
+ { 0x3d402120, 0x909 },
+ { 0x3d402180, 0x40800020 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x20303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d402240, 0x6000604 },
+ { 0x3d4020f4, 0xee5 },
+ { 0x3d400028, 0x1 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x1005f, 0x3ff },
+ { 0x1015f, 0x3ff },
+ { 0x1105f, 0x3ff },
+ { 0x1115f, 0x3ff },
+ { 0x11005f, 0x3ff },
+ { 0x11015f, 0x3ff },
+ { 0x11105f, 0x3ff },
+ { 0x11115f, 0x3ff },
+ { 0x55, 0x3ff },
+ { 0x1055, 0x3ff },
+ { 0x2055, 0x3ff },
+ { 0x3055, 0x3ff },
+ { 0x4055, 0xff },
+ { 0x5055, 0xff },
+ { 0x6055, 0x3ff },
+ { 0x7055, 0x3ff },
+ { 0x8055, 0x3ff },
+ { 0x9055, 0x3ff },
+ { 0x200c5, 0xb },
+ { 0x1200c5, 0x7 },
+ { 0x2002e, 0x1 },
+ { 0x12002e, 0x1 },
+ { 0x20024, 0x0 },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x0 },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0xa },
+ { 0x120056, 0xa },
+ { 0x1004d, 0x208 },
+ { 0x1014d, 0x208 },
+ { 0x1104d, 0x208 },
+ { 0x1114d, 0x208 },
+ { 0x11004d, 0x208 },
+ { 0x11014d, 0x208 },
+ { 0x11104d, 0x208 },
+ { 0x11114d, 0x208 },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x0 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x190 },
+ { 0x120008, 0xa7 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x32c },
+ { 0x10043, 0x581 },
+ { 0x10143, 0x581 },
+ { 0x11043, 0x581 },
+ { 0x11143, 0x581 },
+ { 0x1200b2, 0x32c },
+ { 0x110043, 0x581 },
+ { 0x110143, 0x581 },
+ { 0x111043, 0x581 },
+ { 0x111143, 0x581 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x010082, 0x0},
+ {0x110082, 0x0},
+ {0x210082, 0x0},
+ {0x010182, 0x0},
+ {0x110182, 0x0},
+ {0x210182, 0x0},
+ {0x010083, 0x0},
+ {0x110083, 0x0},
+ {0x210083, 0x0},
+ {0x010183, 0x0},
+ {0x110183, 0x0},
+ {0x210183, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x011082, 0x0},
+ {0x111082, 0x0},
+ {0x211082, 0x0},
+ {0x011182, 0x0},
+ {0x111182, 0x0},
+ {0x211182, 0x0},
+ {0x011083, 0x0},
+ {0x111083, 0x0},
+ {0x211083, 0x0},
+ {0x011183, 0x0},
+ {0x111183, 0x0},
+ {0x211183, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0100d2, 0x0},
+ {0x1100d2, 0x0},
+ {0x2100d2, 0x0},
+ {0x0101d2, 0x0},
+ {0x1101d2, 0x0},
+ {0x2101d2, 0x0},
+ {0x0100d3, 0x0},
+ {0x1100d3, 0x0},
+ {0x2100d3, 0x0},
+ {0x0101d3, 0x0},
+ {0x1101d3, 0x0},
+ {0x2101d3, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x0110d2, 0x0},
+ {0x1110d2, 0x0},
+ {0x2110d2, 0x0},
+ {0x0111d2, 0x0},
+ {0x1111d2, 0x0},
+ {0x2111d2, 0x0},
+ {0x0110d3, 0x0},
+ {0x1110d3, 0x0},
+ {0x2110d3, 0x0},
+ {0x0111d3, 0x0},
+ {0x1111d3, 0x0},
+ {0x2111d3, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x01006a, 0x0},
+ {0x01016a, 0x0},
+ {0x01026a, 0x0},
+ {0x01036a, 0x0},
+ {0x01046a, 0x0},
+ {0x01056a, 0x0},
+ {0x01066a, 0x0},
+ {0x01076a, 0x0},
+ {0x01086a, 0x0},
+ {0x01006b, 0x0},
+ {0x01016b, 0x0},
+ {0x01026b, 0x0},
+ {0x01036b, 0x0},
+ {0x01046b, 0x0},
+ {0x01056b, 0x0},
+ {0x01066b, 0x0},
+ {0x01076b, 0x0},
+ {0x01086b, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01106a, 0x0},
+ {0x01116a, 0x0},
+ {0x01126a, 0x0},
+ {0x01136a, 0x0},
+ {0x01146a, 0x0},
+ {0x01156a, 0x0},
+ {0x01166a, 0x0},
+ {0x01176a, 0x0},
+ {0x01186a, 0x0},
+ {0x01106b, 0x0},
+ {0x01116b, 0x0},
+ {0x01126b, 0x0},
+ {0x01136b, 0x0},
+ {0x01146b, 0x0},
+ {0x01156b, 0x0},
+ {0x01166b, 0x0},
+ {0x01176b, 0x0},
+ {0x01186b, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01008e, 0x0},
+ {0x11008e, 0x0},
+ {0x21008e, 0x0},
+ {0x01018e, 0x0},
+ {0x11018e, 0x0},
+ {0x21018e, 0x0},
+ {0x01008f, 0x0},
+ {0x11008f, 0x0},
+ {0x21008f, 0x0},
+ {0x01018f, 0x0},
+ {0x11018f, 0x0},
+ {0x21018f, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x01108e, 0x0},
+ {0x11108e, 0x0},
+ {0x21108e, 0x0},
+ {0x01118e, 0x0},
+ {0x11118e, 0x0},
+ {0x21118e, 0x0},
+ {0x01108f, 0x0},
+ {0x11108f, 0x0},
+ {0x21108f, 0x0},
+ {0x01118f, 0x0},
+ {0x11118f, 0x0},
+ {0x21118f, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0100c2, 0x0},
+ {0x1100c2, 0x0},
+ {0x2100c2, 0x0},
+ {0x0101c2, 0x0},
+ {0x1101c2, 0x0},
+ {0x2101c2, 0x0},
+ {0x0102c2, 0x0},
+ {0x1102c2, 0x0},
+ {0x2102c2, 0x0},
+ {0x0103c2, 0x0},
+ {0x1103c2, 0x0},
+ {0x2103c2, 0x0},
+ {0x0104c2, 0x0},
+ {0x1104c2, 0x0},
+ {0x2104c2, 0x0},
+ {0x0105c2, 0x0},
+ {0x1105c2, 0x0},
+ {0x2105c2, 0x0},
+ {0x0106c2, 0x0},
+ {0x1106c2, 0x0},
+ {0x2106c2, 0x0},
+ {0x0107c2, 0x0},
+ {0x1107c2, 0x0},
+ {0x2107c2, 0x0},
+ {0x0108c2, 0x0},
+ {0x1108c2, 0x0},
+ {0x2108c2, 0x0},
+ {0x0100c3, 0x0},
+ {0x1100c3, 0x0},
+ {0x2100c3, 0x0},
+ {0x0101c3, 0x0},
+ {0x1101c3, 0x0},
+ {0x2101c3, 0x0},
+ {0x0102c3, 0x0},
+ {0x1102c3, 0x0},
+ {0x2102c3, 0x0},
+ {0x0103c3, 0x0},
+ {0x1103c3, 0x0},
+ {0x2103c3, 0x0},
+ {0x0104c3, 0x0},
+ {0x1104c3, 0x0},
+ {0x2104c3, 0x0},
+ {0x0105c3, 0x0},
+ {0x1105c3, 0x0},
+ {0x2105c3, 0x0},
+ {0x0106c3, 0x0},
+ {0x1106c3, 0x0},
+ {0x2106c3, 0x0},
+ {0x0107c3, 0x0},
+ {0x1107c3, 0x0},
+ {0x2107c3, 0x0},
+ {0x0108c3, 0x0},
+ {0x1108c3, 0x0},
+ {0x2108c3, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x0110c2, 0x0},
+ {0x1110c2, 0x0},
+ {0x2110c2, 0x0},
+ {0x0111c2, 0x0},
+ {0x1111c2, 0x0},
+ {0x2111c2, 0x0},
+ {0x0112c2, 0x0},
+ {0x1112c2, 0x0},
+ {0x2112c2, 0x0},
+ {0x0113c2, 0x0},
+ {0x1113c2, 0x0},
+ {0x2113c2, 0x0},
+ {0x0114c2, 0x0},
+ {0x1114c2, 0x0},
+ {0x2114c2, 0x0},
+ {0x0115c2, 0x0},
+ {0x1115c2, 0x0},
+ {0x2115c2, 0x0},
+ {0x0116c2, 0x0},
+ {0x1116c2, 0x0},
+ {0x2116c2, 0x0},
+ {0x0117c2, 0x0},
+ {0x1117c2, 0x0},
+ {0x2117c2, 0x0},
+ {0x0118c2, 0x0},
+ {0x1118c2, 0x0},
+ {0x2118c2, 0x0},
+ {0x0110c3, 0x0},
+ {0x1110c3, 0x0},
+ {0x2110c3, 0x0},
+ {0x0111c3, 0x0},
+ {0x1111c3, 0x0},
+ {0x2111c3, 0x0},
+ {0x0112c3, 0x0},
+ {0x1112c3, 0x0},
+ {0x2112c3, 0x0},
+ {0x0113c3, 0x0},
+ {0x1113c3, 0x0},
+ {0x2113c3, 0x0},
+ {0x0114c3, 0x0},
+ {0x1114c3, 0x0},
+ {0x2114c3, 0x0},
+ {0x0115c3, 0x0},
+ {0x1115c3, 0x0},
+ {0x2115c3, 0x0},
+ {0x0116c3, 0x0},
+ {0x1116c3, 0x0},
+ {0x2116c3, 0x0},
+ {0x0117c3, 0x0},
+ {0x1117c3, 0x0},
+ {0x2117c3, 0x0},
+ {0x0118c3, 0x0},
+ {0x1118c3, 0x0},
+ {0x2118c3, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x283c },
+ { 0x54006, 0x140 },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x1d70 },
+ { 0x54030, 0x4 },
+ { 0x54031, 0x18 },
+ { 0x5403a, 0x1323 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x29c },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x283c },
+ { 0x54006, 0x140 },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x1220 },
+ { 0x54030, 0x4 },
+ { 0x5403a, 0x1323 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x2 },
+ { 0x90033, 0x10 },
+ { 0x90034, 0x139 },
+ { 0x90035, 0xb },
+ { 0x90036, 0x7c0 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0x44 },
+ { 0x90039, 0x633 },
+ { 0x9003a, 0x159 },
+ { 0x9003b, 0x14f },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x47 },
+ { 0x9003f, 0x633 },
+ { 0x90040, 0x149 },
+ { 0x90041, 0x4f },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x179 },
+ { 0x90044, 0x8 },
+ { 0x90045, 0xe0 },
+ { 0x90046, 0x109 },
+ { 0x90047, 0x0 },
+ { 0x90048, 0x7c8 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x1 },
+ { 0x9004c, 0x8 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x45a },
+ { 0x9004f, 0x9 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x448 },
+ { 0x90052, 0x109 },
+ { 0x90053, 0x40 },
+ { 0x90054, 0x633 },
+ { 0x90055, 0x179 },
+ { 0x90056, 0x1 },
+ { 0x90057, 0x618 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40c0 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x149 },
+ { 0x9005c, 0x8 },
+ { 0x9005d, 0x4 },
+ { 0x9005e, 0x48 },
+ { 0x9005f, 0x4040 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x0 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x40 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x10 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x18 },
+ { 0x9006b, 0x0 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x78 },
+ { 0x9006e, 0x549 },
+ { 0x9006f, 0x633 },
+ { 0x90070, 0x159 },
+ { 0x90071, 0xd49 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0x94a },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x441 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x149 },
+ { 0x9007a, 0x42 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x1 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x0 },
+ { 0x90081, 0xe0 },
+ { 0x90082, 0x109 },
+ { 0x90083, 0xa },
+ { 0x90084, 0x10 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0x9 },
+ { 0x90087, 0x3c0 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x159 },
+ { 0x9008c, 0x18 },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x0 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x18 },
+ { 0x90093, 0x4 },
+ { 0x90094, 0x48 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x58 },
+ { 0x90098, 0xb },
+ { 0x90099, 0x10 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x1 },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x5 },
+ { 0x9009f, 0x7c0 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x0 },
+ { 0x900a2, 0x8140 },
+ { 0x900a3, 0x10c },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x8138 },
+ { 0x900a6, 0x10c },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7c8 },
+ { 0x900a9, 0x101 },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x448 },
+ { 0x900ac, 0x109 },
+ { 0x900ad, 0xf },
+ { 0x900ae, 0x7c0 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x47 },
+ { 0x900b1, 0x630 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x8 },
+ { 0x900b4, 0x618 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0xe0 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x0 },
+ { 0x900ba, 0x7c8 },
+ { 0x900bb, 0x109 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x8140 },
+ { 0x900be, 0x10c },
+ { 0x900bf, 0x0 },
+ { 0x900c0, 0x1 },
+ { 0x900c1, 0x8 },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x8 },
+ { 0x900c5, 0x8 },
+ { 0x900c6, 0x7c8 },
+ { 0x900c7, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x90026, 0x2b },
+ { 0x2000b, 0x32 },
+ { 0x2000c, 0x64 },
+ { 0x2000d, 0x3e8 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x14 },
+ { 0x12000c, 0x26 },
+ { 0x12000d, 0x1a1 },
+ { 0x12000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0xffff },
+ { 0x90013, 0x6152 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 667mts 1D */
+ .drate = 667,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 1600, 667, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <env.h>
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (is_usb_boot()) {
+ env_set("bootcmd", "run bootcmd_mfg");
+ env_set("bootdelay", "0");
+ }
+
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x912000
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ *
+ */
+
+#include <hang.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ debug("Normal Boot\n");
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0)
+ puts("Failed to find clock node. Check device tree\n");
+}
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static const iomux_v3_cfg_t uart_pads[] = {
+ IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+ IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+ init_uart_clk(3);
+
+ if (IS_ENABLED(CONFIG_NAND_MXS)) {
+ init_nand_clk();
+ }
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
obj-y += imx8mm-cl-iot-gate.o
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o eeprom_spl.o
obj-y += ddr/
endif
#include <asm/mach-imx/gpio.h>
#include "ddr.h"
+#include <linux/delay.h>
+
static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
{
unsigned int tmp;
(struct lpddr4_tcm_desc *)SPL_TCM_DATA;
if (lpddr4_tcm_desc->sign != DEFAULT) {
- /* if not in tcm scan mode */
+ /* get ddr type from the eeprom if not in tcm scan mode */
+ ddr_info = cl_eeprom_get_ddrinfo();
for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) {
if (lpddr4_array[i].id == ddr_info &&
- lpddr4_array[i].subind == 0xff) {
+ lpddr4_array[i].subind == cl_eeprom_get_subind()) {
ddr_found = 1;
break;
}
SPL_TCM_FINI;
+ if (ddr_found == 0) {
+ /* Update eeprom */
+ cl_eeprom_set_ddrinfo(ddr_info_mrr);
+ mdelay(10);
+ ddr_info = cl_eeprom_get_ddrinfo();
+ mdelay(10);
+ cl_eeprom_set_subind(lpddr4_array[i].subind);
+ /* make sure that the ddr_info has reached the eeprom */
+ printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n", ddr_info);
+ if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind() != lpddr4_array[i].subind) {
+ printf("DDRINFO(EEPROM): make sure that the eeprom is accessible\n");
+ printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x51 0x40 0x50\n");
+ }
+ }
+
/* Pass the dram size to th U-Boot through the tcm memory */
{ /* To figure out what to store into the TCM buffer */
/* For debug purpouse only. To override the real memsize */
- unsigned int ddr_tcm_size = 0;
+ unsigned int ddr_tcm_size = cl_eeprom_get_osize();
if (ddr_tcm_size == 0 || ddr_tcm_size == -1)
ddr_tcm_size = lpddr4_array[i].size;
unsigned int count;
};
+u32 cl_eeprom_get_ddrinfo(void);
+u32 cl_eeprom_set_ddrinfo(u32 ddrinfo);
+u32 cl_eeprom_get_subind(void);
+u32 cl_eeprom_set_subind(u32 subind);
+u32 cl_eeprom_get_osize(void);
#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/* (C) Copyright 2019 CompuLab, Ltd. <www.compulab.co.il> */
+
+#include <common.h>
+#include <i2c.h>
+#include <linux/kernel.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm-generic/gpio.h>
+#include <asm/setup.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_SPL_BUILD
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_P1 0x51
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+static iomux_v3_cfg_t const eeprom_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define EEPROM_WP_GPIO IMX_GPIO_NR(1, 13)
+
+static void cl_eeprom_we(int enable)
+{
+ static int done;
+
+ if (done) {
+ gpio_direction_output(EEPROM_WP_GPIO, enable);
+ return;
+ }
+
+ imx_iomux_v3_setup_multiple_pads(eeprom_pads, ARRAY_SIZE(eeprom_pads));
+ gpio_request(EEPROM_WP_GPIO, "eeprom_wp");
+ gpio_direction_output(EEPROM_WP_GPIO, enable);
+ done = 1;
+}
+
+static int cl_eeprom_read(uint offset, uchar *buf, int len)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+ if (ret) {
+ printf("%s: Cannot find EEPROM: %d\n", __func__, ret);
+ return ret;
+ }
+
+ return dm_i2c_read(dev, offset, buf, len);
+}
+
+static int cl_eeprom_write(uint offset, uchar *buf, int len)
+{
+ struct udevice *dev;
+ int ret;
+
+ cl_eeprom_we(1);
+
+ ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+ if (ret) {
+ printf("%s: Cannot find EEPROM: %d\n", __func__, ret);
+ return ret;
+ }
+
+ return dm_i2c_write(dev, offset, buf, len);
+}
+
+/* Reserved for fututre use area */
+#define BOARD_DDRINFO_OFFSET 0x40
+#define BOARD_DDR_SIZE 4
+static u32 board_ddrinfo = 0xdeadbeef;
+
+#define BOARD_DDRSUBIND_OFFSET 0x44
+#define BOARD_DDRSUBIND_SIZE 1
+static u8 board_ddrsubind = 0xff;
+
+#define BOARD_OSIZE_OFFSET 0x80
+#define BOARD_OSIZE_SIZE 4
+static u32 board_osize = 0xdeadbeef;
+
+#define BOARD_DDRINFO_VALID(A) ((A) != 0xdeadbeef)
+
+u32 cl_eeprom_get_ddrinfo(void)
+{
+ if (!BOARD_DDRINFO_VALID(board_ddrinfo)) {
+ if (cl_eeprom_read(BOARD_DDRINFO_OFFSET, (uchar *)&board_ddrinfo, BOARD_DDR_SIZE))
+ return 0;
+ }
+ return board_ddrinfo;
+};
+
+u32 cl_eeprom_set_ddrinfo(u32 ddrinfo)
+{
+ if (cl_eeprom_write(BOARD_DDRINFO_OFFSET, (uchar *)&ddrinfo, BOARD_DDR_SIZE))
+ return 0;
+
+ board_ddrinfo = ddrinfo;
+
+ return board_ddrinfo;
+};
+
+u8 cl_eeprom_get_subind(void)
+{
+ if (cl_eeprom_read(BOARD_DDRSUBIND_OFFSET, (uchar *)&board_ddrsubind, BOARD_DDRSUBIND_SIZE))
+ return 0xff;
+
+ return board_ddrsubind;
+};
+
+u8 cl_eeprom_set_subind(u8 ddrsubind)
+{
+ if (cl_eeprom_write(BOARD_DDRSUBIND_OFFSET, (uchar *)&ddrsubind, BOARD_DDRSUBIND_SIZE))
+ return 0xff;
+ board_ddrsubind = ddrsubind;
+
+ return board_ddrsubind;
+};
+
+/* override-size ifaces */
+u32 cl_eeprom_get_osize(void)
+{
+ if (cl_eeprom_read(BOARD_OSIZE_OFFSET, (uchar *)&board_osize, BOARD_OSIZE_SIZE))
+ return 0;
+
+ return board_osize;
+};
+#endif
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
+#include <i2c_eeprom.h>
+#include <i2c.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mm_pins.h>
return ret;
}
+static int setup_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ struct udevice *dev;
+ int ret, off;
+
+ ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+ if (ret)
+ return 0;
+
+ off = fdt_path_offset(gd->fdt_blob, "eeprom1");
+ if (off < 0) {
+ printf("No eeprom0 path offset found in DT\n");
+ return off;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+ if (ret) {
+ printf("%s: Could not find EEPROM\n", __func__);
+ return ret;
+ }
+
+ ret = i2c_set_chip_offset_len(dev, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_eeprom_read(dev, 4, enetaddr, sizeof(enetaddr));
+ if (ret) {
+ printf("%s: Could not read EEPROM\n", __func__);
+ return ret;
+ }
+
+ ret = is_valid_ethaddr(enetaddr);
+ if (!ret)
+ return -EINVAL;
+
+ ret = eth_env_set_enetaddr("ethaddr", enetaddr);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int read_serial_number(void)
+{
+ unsigned char serialnumber[6];
+ unsigned char reversed[6];
+ char serial_string[12];
+ struct udevice *dev;
+ int ret, off, i;
+
+ off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+ if (off < 0) {
+ printf("No eeprom0 path offset found in DT\n");
+ return off;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+ if (ret) {
+ printf("%s: Could not find EEPROM\n", __func__);
+ return ret;
+ }
+
+ ret = i2c_set_chip_offset_len(dev, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_eeprom_read(dev, 0x14, serialnumber, sizeof(serialnumber));
+ if (ret) {
+ printf("%s: Could not read EEPROM\n", __func__);
+ return ret;
+ }
+
+ for (i = sizeof(serialnumber) - 1; i >= 0; i--)
+ reversed[i] = serialnumber[sizeof(serialnumber) - 1 - i];
+
+ for (i = 0; i < sizeof(reversed); i++) {
+ serial_string[i * 2] = (reversed[i] >> 4) & 0xf;
+ serial_string[i * 2 + 1] = reversed[i] & 0xf;
+ }
+
+ for (i = 0; i < sizeof(serial_string); i++)
+ serial_string[i] += '0';
+
+ env_set("serial#", serial_string);
+
+ return 0;
+}
+
int board_late_init(void)
{
+ int ret;
+
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
env_set("board_name", "IOT-GATE-IMX8");
env_set("board_rev", "SBC-IOTMX8");
}
+ ret = setup_mac_address();
+ if (ret < 0)
+ printf("Cannot set MAC address from EEPROM\n");
+
+ ret = read_serial_number();
+ if (ret < 0)
+ printf("Cannot read serial number from EEPROM\n");
+
return 0;
}
--- /dev/null
+if TARGET_IMX8MM_DATA_MODUL_EDM_SBC
+
+config SYS_BOARD
+ default "imx8mm_edm_sbc"
+
+config SYS_VENDOR
+ default "data_modul"
+
+config SYS_CONFIG_NAME
+ default "imx8mm_data_modul_edm_sbc"
+
+endif
--- /dev/null
+Data Modul eDM SBC i.MX8M Mini
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
+F: arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
+F: board/data_modul/imx8mm_data_modul_edm_sbc/
+F: configs/imx8mm_data_modul_edm_sbc_defconfig
+F: include/configs/imx8mm_data_modul_edm_sbc.h
--- /dev/null
+#
+# Copyright (C) 2022 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o
+else
+obj-y += imx8mm_data_modul_edm_sbc.o
+endif
+
+obj-y += common.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u8 dmo_get_memcfg(void)
+{
+ struct gpio_desc gpio[4];
+ u8 memcfg = 0;
+ ofnode node;
+ int i, ret;
+
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node)) {
+ printf("%s: no /config node?\n", __func__);
+ return BIT(2) | BIT(0);
+ }
+
+ ret = gpio_request_list_by_name_nodev(node,
+ "dmo,ram-coding-gpios",
+ gpio, ARRAY_SIZE(gpio),
+ GPIOD_IS_IN);
+ for (i = 0; i < ret; i++)
+ memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+ gpio_free_list_nodev(gpio, ret);
+
+ return memcfg;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <dm.h>
+#include <i2c_eeprom.h>
+#include <malloc.h>
+#include <net.h>
+#include <spl.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+ icache_enable();
+ return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ u8 memcfg = dmo_get_memcfg();
+
+ *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G;
+
+ return 0;
+}
+
+/* IMX8M SNVS registers needed for the bootcount functionality */
+#define SNVS_BASE_ADDR 0x30370000
+#define SNVS_LPSR 0x4c
+#define SNVS_LPLVDR 0x64
+#define SNVS_LPPGDR_INIT 0x41736166
+
+static void setup_snvs(void)
+{
+ /* Enable SNVS clock */
+ clock_enable(CCGR_SNVS, 1);
+ /* Initialize glitch detect */
+ writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
+ /* Clear interrupt status */
+ writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
+}
+
+static void setup_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ struct udevice *dev;
+ int off, ret;
+
+ ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+ if (ret) /* ethaddr is already set */
+ return;
+
+ off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+ if (off < 0) {
+ printf("%s: No eeprom0 path offset\n", __func__);
+ return;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+ if (ret) {
+ printf("Cannot find EEPROM!\n");
+ return;
+ }
+
+ ret = i2c_eeprom_read(dev, 0xb0, enetaddr, 0x6);
+ if (ret) {
+ printf("Error reading configuration EEPROM!\n");
+ return;
+ }
+
+ if (is_valid_ethaddr(enetaddr))
+ eth_env_set_enetaddr("ethaddr", enetaddr);
+}
+
+static void setup_boot_device(void)
+{
+ int boot_device = get_boot_device();
+ char *devnum;
+
+ devnum = env_get("devnum");
+ if (devnum) /* devnum is already set */
+ return;
+
+ if (boot_device == MMC3_BOOT) /* eMMC */
+ env_set_ulong("devnum", 0);
+ else
+ env_set_ulong("devnum", 1);
+}
+
+int board_init(void)
+{
+ setup_snvs();
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_boot_device();
+ setup_mac_address();
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+FIT
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x7E1000
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_16_32;
+extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_32_32;
+
+u8 dmo_get_memcfg(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x203 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b00d2 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xd8 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x6 },
+ { 0x100a1, 0x7 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x1 },
+ { 0x100a4, 0x3 },
+ { 0x100a5, 0x2 },
+ { 0x100a6, 0x4 },
+ { 0x100a7, 0x5 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x5 },
+ { 0x110a3, 0x3 },
+ { 0x110a4, 0x2 },
+ { 0x110a5, 0x4 },
+ { 0x110a6, 0x6 },
+ { 0x110a7, 0x7 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x5 },
+ { 0x120a3, 0x3 },
+ { 0x120a4, 0x2 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x6 },
+ { 0x120a7, 0x7 },
+ { 0x130a0, 0x6 },
+ { 0x130a1, 0x7 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x1 },
+ { 0x130a4, 0x3 },
+ { 0x130a5, 0x2 },
+ { 0x130a6, 0x4 },
+ { 0x130a7, 0x5 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x2200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
+ { 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
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+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x5d },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dmo_imx8mm_sbc_dram_timing_16_32 = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x203 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b00d2 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xd8 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x6 },
+ { 0x100a1, 0x7 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x1 },
+ { 0x100a4, 0x3 },
+ { 0x100a5, 0x2 },
+ { 0x100a6, 0x4 },
+ { 0x100a7, 0x5 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x5 },
+ { 0x110a3, 0x3 },
+ { 0x110a4, 0x2 },
+ { 0x110a5, 0x4 },
+ { 0x110a6, 0x6 },
+ { 0x110a7, 0x7 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x5 },
+ { 0x120a3, 0x3 },
+ { 0x120a4, 0x2 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x6 },
+ { 0x120a7, 0x7 },
+ { 0x130a0, 0x6 },
+ { 0x130a1, 0x7 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x1 },
+ { 0x130a4, 0x3 },
+ { 0x130a5, 0x2 },
+ { 0x130a6, 0x4 },
+ { 0x130a7, 0x5 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x2200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
+ { 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x5d },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dmo_imx8mm_sbc_dram_timing_32_32 = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/ddr.h>
+#include <asm/mach-imx/boot_mode.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/bd71837.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static const iomux_v3_cfg_t uart_pads[] = {
+ IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static void data_modul_imx8mm_edm_sbc_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static int data_modul_imx8mm_edm_sbc_board_power_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pmic@4b", &dev);
+ if (ret == -ENODEV) {
+ puts("Failed to get PMIC\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* Unlock the PMIC regs */
+ pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+ /* Increase VDD_SOC to typical value 0.85V before first DRAM access */
+ pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+ /* Increase VDD_DRAM to 0.975V for 3GHz DDR */
+ pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+ /* Lock the PMIC regs */
+ pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+ return 0;
+}
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ if (boot_dev_spl == MMC3_BOOT)
+ return BOOT_DEVICE_MMC2; /* eMMC */
+ else
+ return BOOT_DEVICE_MMC1; /* SD */
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ int boot_device = spl_boot_device();
+
+ spl_boot_list[0] = boot_device; /* 1:SD 2:eMMC */
+
+ if (boot_device == BOOT_DEVICE_MMC1)
+ spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */
+ else
+ spl_boot_list[1] = BOOT_DEVICE_MMC1; /* SD */
+
+ spl_boot_list[2] = BOOT_DEVICE_UART; /* YModem */
+ spl_boot_list[3] = BOOT_DEVICE_NONE;
+}
+
+static struct dram_timing_info *dram_timing_info[8] = {
+ &dmo_imx8mm_sbc_dram_timing_32_32, /* 32 Gbit x32 */
+ NULL, /* 32 Gbit x16 */
+ &dmo_imx8mm_sbc_dram_timing_16_32, /* 16 Gbit x32 */
+ NULL, /* 16 Gbit x16 */
+ NULL, /* 8 Gbit x32 */
+ NULL, /* 8 Gbit x16 */
+ NULL, /* INVALID */
+ NULL, /* INVALID */
+};
+
+static void spl_dram_init(void)
+{
+ u8 memcfg = dmo_get_memcfg();
+ int i;
+
+ printf("DDR: %d GiB x%d [0x%x]\n",
+ /* 0..4 GiB, 1..2 GiB, 0..1 GiB */
+ 4 >> ((memcfg >> 1) & 0x3),
+ /* 0..x32, 1..x16 */
+ 32 >> (memcfg & BIT(0)),
+ memcfg);
+
+ if (!dram_timing_info[memcfg]) {
+ printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
+ memcfg);
+ for (i = ARRAY_SIZE(dram_timing_info) - 1; i >= 0; i--)
+ if (dram_timing_info[i]) /* Configuration found */
+ break;
+ }
+
+ ddr_init(dram_timing_info[memcfg]);
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ icache_enable();
+
+ arch_cpu_init();
+
+ init_uart_clk(2);
+
+ data_modul_imx8mm_edm_sbc_early_init_f();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0) {
+ printf("Failed to find clock node. Check device tree\n");
+ hang();
+ }
+
+ enable_tzc380();
+
+ data_modul_imx8mm_edm_sbc_board_power_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
dcache_enable();
}
-#if defined(CONFIG_EFI_RNG_PROTOCOL)
-#include <efi_loader.h>
-#include <efi_rng.h>
-
-#include <dm/device-internal.h>
-
-efi_status_t platform_get_rng_device(struct udevice **dev)
-{
- int ret;
- efi_status_t status = EFI_DEVICE_ERROR;
- struct udevice *bus, *devp;
-
- for (uclass_first_device(UCLASS_VIRTIO, &bus); bus;
- uclass_next_device(&bus)) {
- for (device_find_first_child(bus, &devp); devp;
- device_find_next_child(&devp)) {
- if (device_get_uclass_id(devp) == UCLASS_RNG) {
- *dev = devp;
- status = EFI_SUCCESS;
- break;
- }
- }
- }
-
- if (status != EFI_SUCCESS) {
- debug("No rng device found\n");
- return EFI_DEVICE_ERROR;
- }
-
- if (*dev) {
- ret = device_probe(*dev);
- if (ret)
- return EFI_DEVICE_ERROR;
- } else {
- debug("Couldn't get child device\n");
- return EFI_DEVICE_ERROR;
- }
-
- return EFI_SUCCESS;
-}
-#endif /* CONFIG_EFI_RNG_PROTOCOL */
-
#ifdef CONFIG_ARM64
#define __W "w"
#else
imply SPL_RAM_DEVICE
imply CMD_PCI
imply CMD_POWEROFF
+ imply CMD_SBI
imply CMD_SCSI
imply CMD_PING
imply CMD_EXT2
functionality. It is used by the common VID driver.
endif
+
+config FSL_QIXIS
+ bool "Enable QIXIS support"
+
+config QIXIS_I2C_ACCESS
+ bool "Access to QIXIS is over i2c"
+ depends on FSL_QIXIS
+ default y
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
+ifneq (,$(filter $(SOC), imx8ulp))
+obj-y += mmc.o
+endif
obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018-2022 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <stdbool.h>
+#include <mmc.h>
+#include <env.h>
+
+static int check_mmc_autodetect(void)
+{
+ char *autodetect_str = env_get("mmcautodetect");
+
+ if (autodetect_str && !strcmp(autodetect_str, "yes"))
+ return 1;
+
+ return 0;
+}
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+ return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+ char cmd[32];
+ char mmcblk[32];
+ u32 dev_no = mmc_get_env_dev();
+
+ if (!check_mmc_autodetect())
+ return;
+
+ env_set_ulong("mmcdev", dev_no);
+
+ /* Set mmcblk env */
+ sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", mmc_map_to_kernel_blk(dev_no));
+ env_set("mmcroot", mmcblk);
+
+ sprintf(cmd, "mmc dev %d", dev_no);
+ run_command(cmd, 0);
+}
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
void spl_board_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
puts("Normal Boot\n");
}
clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
}
-int board_phy_config(struct phy_device *phydev)
-{
- /* enable rgmii rxc skew and phy mode select to RGMII copper */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
-
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
-}
-
int board_init(void)
{
setup_fec();
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
struct udevice *dev;
int ret;
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
puts("Normal Boot\n");
ret = uclass_get_device_by_name(UCLASS_CLK,
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
DECLARE_GLOBAL_DATA_PTR;
void spl_board_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
/*
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
* not allow to change it. Should set the clock after PMIC
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
+#include <fsl_sec.h>
#include <mmc.h>
#include <linux/delay.h>
#include <power/pmic.h>
void spl_board_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ if (sec_init())
+ printf("\nsec_init failed!\n");
+ }
puts("Normal Boot\n");
}
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
obj-y += imx8ulp_evk.o
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o ddr_init.o lpddr4_timing.o
+obj-y += spl.o ddr_init.o
+ifdef CONFIG_IMX8ULP_ND_MODE
+obj-y += lpddr4_timing_264.o
+else
+obj-y += lpddr4_timing.o
+endif
endif
int board_init(void)
{
+ int sync = -ENODEV;
+
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
- if (IS_ENABLED(CONFIG_DM_VIDEO)) {
+ if (m33_image_booted()) {
+ sync = m33_image_handshake(1000);
+ printf("M33 Sync: %s\n", sync ? "Timeout" : "OK");
+ }
+
+ /* When sync with M33 is failed, use local driver to set for video */
+ if (sync != 0 && IS_ENABLED(CONFIG_DM_VIDEO)) {
mipi_dsi_mux_panel();
mipi_dsi_panel_backlight();
}
int board_late_init(void)
{
+#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC)
+ board_late_mmc_env_init();
+#endif
return 0;
}
{ 0x2e064154, 0x2000000 }, /* 85 */
{ 0x2e064158, 0x51515042 }, /* 86 */
{ 0x2e06415c, 0x31c06000 }, /* 87 */
- { 0x2e064160, 0x9bf000a }, /* 88 */
+ { 0x2e064160, 0x6bf000a }, /* 88 */
{ 0x2e064164, 0xc0c000 }, /* 89 */
{ 0x2e064168, 0x1000000 }, /* 90 */
{ 0x2e06416c, 0x10001000 }, /* 91 */
{ 0x2e064554, 0x2000000 }, /* 341 */
{ 0x2e064558, 0x51515042 }, /* 342 */
{ 0x2e06455c, 0x31c06000 }, /* 343 */
- { 0x2e064560, 0x9bf000a }, /* 344 */
+ { 0x2e064560, 0x6bf000a }, /* 344 */
{ 0x2e064564, 0xc0c000 }, /* 345 */
{ 0x2e064568, 0x1000000 }, /* 346 */
{ 0x2e06456c, 0x10001000 }, /* 347 */
{ 0x2e064954, 0x2000000 }, /* 597 */
{ 0x2e064958, 0x51515042 }, /* 598 */
{ 0x2e06495c, 0x31c06000 }, /* 599 */
- { 0x2e064960, 0x9bf000a }, /* 600 */
+ { 0x2e064960, 0x6bf000a }, /* 600 */
{ 0x2e064964, 0xc0c000 }, /* 601 */
{ 0x2e064968, 0x1000000 }, /* 602 */
{ 0x2e06496c, 0x10001000 }, /* 603 */
{ 0x2e064d54, 0x2000000 }, /* 853 */
{ 0x2e064d58, 0x51515042 }, /* 854 */
{ 0x2e064d5c, 0x31c06000 }, /* 855 */
- { 0x2e064d60, 0x9bf000a }, /* 856 */
+ { 0x2e064d60, 0x6bf000a }, /* 856 */
{ 0x2e064d64, 0xc0c000 }, /* 857 */
{ 0x2e064d68, 0x1000000 }, /* 858 */
{ 0x2e064d6c, 0x10001000 }, /* 859 */
{ 0x2e065860, 0x8040201 }, /* 1560 */
{ 0x2e065864, 0x2010201 }, /* 1561 */
{ 0x2e065868, 0xf0f0f }, /* 1562 */
- { 0x2e06586c, 0x241b42 }, /* 1563 */
+ { 0x2e06586c, 0x241342 }, /* 1563 */
{ 0x2e065874, 0x1020000 }, /* 1565 */
{ 0x2e065878, 0x701 }, /* 1566 */
{ 0x2e06587c, 0x54 }, /* 1567 */
{ 0x2e0658a0, 0x4410 }, /* 1576 */
{ 0x2e0658a4, 0x4410 }, /* 1577 */
{ 0x2e0658b0, 0x60000 }, /* 1580 */
- { 0x2e0658b8, 0x96 }, /* 1582 */
+ { 0x2e0658b8, 0x66 }, /* 1582 */
{ 0x2e0658bc, 0x10000 }, /* 1583 */
{ 0x2e0658c0, 0x8 }, /* 1584 */
{ 0x2e0658d8, 0x3000000 }, /* 1590 */
{ 0x2e065980, 0x300 }, /* 1632 */
{ 0x2e065984, 0x300 }, /* 1633 */
{ 0x2e065988, 0x300 }, /* 1634 */
- { 0x2e06598c, 0x4bf77 }, /* 1635 */
- { 0x2e065990, 0x77 }, /* 1636 */
- { 0x2e065994, 0x27f }, /* 1637 */
- { 0x2e06599c, 0x27f }, /* 1639 */
- { 0x2e0659a4, 0x27f00 }, /* 1641 */
+ { 0x2e06598c, 0x337cc }, /* 1635 */
+ { 0x2e065990, 0x8 }, /* 1636 */
+ { 0x2e065994, 0x1b7 }, /* 1637 */
+ { 0x2e06599c, 0x1b7 }, /* 1639 */
+ { 0x2e0659a4, 0x1b700 }, /* 1641 */
{ 0x2e0659a8, 0x1980000 }, /* 1642 */
- { 0x2e0659ac, 0x27fcc }, /* 1643 */
- { 0x2e0659b4, 0x27f00 }, /* 1645 */
+ { 0x2e0659ac, 0x1b7cc }, /* 1643 */
+ { 0x2e0659b4, 0x1b700 }, /* 1645 */
{ 0x2e0659b8, 0x1980000 }, /* 1646 */
- { 0x2e0659bc, 0x27f00 }, /* 1647 */
+ { 0x2e0659bc, 0x1b700 }, /* 1647 */
{ 0x2e0659c0, 0x1980000 }, /* 1648 */
- { 0x2e0659c4, 0x27f00 }, /* 1649 */
+ { 0x2e0659c4, 0x1b700 }, /* 1649 */
{ 0x2e0659c8, 0x1980000 }, /* 1650 */
- { 0x2e0659cc, 0x27f00 }, /* 1651 */
+ { 0x2e0659cc, 0x1b700 }, /* 1651 */
{ 0x2e0659d0, 0x1980000 }, /* 1652 */
{ 0x2e0659d4, 0x20040003 }, /* 1653 */
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021 NXP
+ *
+ * Generated code from MX8ULP_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/** CTL settings **/
+struct dram_cfg_param ddr_ctl_cfg[] = {
+ { 0x2e060000, 0xb00 }, /* 0 */
+ { 0x2e060028, 0x258100 }, /* 10 */
+ { 0x2e06002c, 0x17702 }, /* 11 */
+ { 0x2e060030, 0x5 }, /* 12 */
+ { 0x2e060034, 0x61 }, /* 13 */
+ { 0x2e060038, 0xce3f }, /* 14 */
+ { 0x2e06003c, 0x80e70 }, /* 15 */
+ { 0x2e060040, 0x5 }, /* 16 */
+ { 0x2e060044, 0x210 }, /* 17 */
+ { 0x2e060048, 0x19c7d }, /* 18 */
+ { 0x2e06004c, 0x101cdf }, /* 19 */
+ { 0x2e060050, 0x5 }, /* 20 */
+ { 0x2e060054, 0x420 }, /* 21 */
+ { 0x2e060058, 0x1010000 }, /* 22 */
+ { 0x2e06005c, 0x1011001 }, /* 23 */
+ { 0x2e060060, 0x10000 }, /* 24 */
+ { 0x2e060064, 0x102 }, /* 25 */
+ { 0x2e060068, 0xa }, /* 26 */
+ { 0x2e06006c, 0x19 }, /* 27 */
+ { 0x2e060078, 0x2020200 }, /* 30 */
+ { 0x2e06007c, 0x160b }, /* 31 */
+ { 0x2e060090, 0x10 }, /* 36 */
+ { 0x2e0600a4, 0x40c040c }, /* 41 */
+ { 0x2e0600a8, 0x8040614 }, /* 42 */
+ { 0x2e0600ac, 0x604 }, /* 43 */
+ { 0x2e0600b0, 0x3090003 }, /* 44 */
+ { 0x2e0600b4, 0x40002 }, /* 45 */
+ { 0x2e0600b8, 0xc0011 }, /* 46 */
+ { 0x2e0600bc, 0xb0509 }, /* 47 */
+ { 0x2e0600c0, 0x2106 }, /* 48 */
+ { 0x2e0600c4, 0xa090017 }, /* 49 */
+ { 0x2e0600c8, 0x8200016 }, /* 50 */
+ { 0x2e0600cc, 0xa0a }, /* 51 */
+ { 0x2e0600d0, 0x4000694 }, /* 52 */
+ { 0x2e0600d4, 0xa0a0804 }, /* 53 */
+ { 0x2e0600d8, 0x4002432 }, /* 54 */
+ { 0x2e0600dc, 0xa0a0804 }, /* 55 */
+ { 0x2e0600e0, 0x4004864 }, /* 56 */
+ { 0x2e0600e4, 0x2030404 }, /* 57 */
+ { 0x2e0600e8, 0x5040400 }, /* 58 */
+ { 0x2e0600ec, 0x80b0a06 }, /* 59 */
+ { 0x2e0600f0, 0x7010100 }, /* 60 */
+ { 0x2e0600f4, 0x4150b }, /* 61 */
+ { 0x2e0600fc, 0x1010000 }, /* 63 */
+ { 0x2e060100, 0x1000000 }, /* 64 */
+ { 0x2e060104, 0xe0403 }, /* 65 */
+ { 0x2e060108, 0xb3 }, /* 66 */
+ { 0x2e06010c, 0x4a }, /* 67 */
+ { 0x2e060110, 0x3fd }, /* 68 */
+ { 0x2e060114, 0x94 }, /* 69 */
+ { 0x2e060118, 0x803 }, /* 70 */
+ { 0x2e06011c, 0x5 }, /* 71 */
+ { 0x2e060120, 0x70000 }, /* 72 */
+ { 0x2e060124, 0x25000f }, /* 73 */
+ { 0x2e060128, 0x4a0078 }, /* 74 */
+ { 0x2e06012c, 0x4000f9 }, /* 75 */
+ { 0x2e060130, 0x120103 }, /* 76 */
+ { 0x2e060134, 0x50005 }, /* 77 */
+ { 0x2e060138, 0x8070005 }, /* 78 */
+ { 0x2e06013c, 0x505010d }, /* 79 */
+ { 0x2e060140, 0x101030a }, /* 80 */
+ { 0x2e060144, 0x30a0505 }, /* 81 */
+ { 0x2e060148, 0x5050101 }, /* 82 */
+ { 0x2e06014c, 0x1030a }, /* 83 */
+ { 0x2e060150, 0xe000e }, /* 84 */
+ { 0x2e060154, 0x4c004c }, /* 85 */
+ { 0x2e060158, 0x980098 }, /* 86 */
+ { 0x2e06015c, 0x3050505 }, /* 87 */
+ { 0x2e060160, 0x3010403 }, /* 88 */
+ { 0x2e060164, 0x4050505 }, /* 89 */
+ { 0x2e060168, 0x3010403 }, /* 90 */
+ { 0x2e06016c, 0x8050505 }, /* 91 */
+ { 0x2e060170, 0x3010403 }, /* 92 */
+ { 0x2e060174, 0x3010000 }, /* 93 */
+ { 0x2e060178, 0x10000 }, /* 94 */
+ { 0x2e060180, 0x1000000 }, /* 96 */
+ { 0x2e060184, 0x80104002 }, /* 97 */
+ { 0x2e060188, 0x40003 }, /* 98 */
+ { 0x2e06018c, 0x40005 }, /* 99 */
+ { 0x2e060190, 0x30000 }, /* 100 */
+ { 0x2e060194, 0x50004 }, /* 101 */
+ { 0x2e060198, 0x4 }, /* 102 */
+ { 0x2e06019c, 0x40003 }, /* 103 */
+ { 0x2e0601a0, 0x40005 }, /* 104 */
+ { 0x2e0601a8, 0x2cc0 }, /* 106 */
+ { 0x2e0601ac, 0x2cc0 }, /* 107 */
+ { 0x2e0601b0, 0x2cc0 }, /* 108 */
+ { 0x2e0601b4, 0x2cc0 }, /* 109 */
+ { 0x2e0601b8, 0x2cc0 }, /* 110 */
+ { 0x2e0601c0, 0x4e5 }, /* 112 */
+ { 0x2e0601c4, 0xff40 }, /* 113 */
+ { 0x2e0601c8, 0xff40 }, /* 114 */
+ { 0x2e0601cc, 0xff40 }, /* 115 */
+ { 0x2e0601d0, 0xff40 }, /* 116 */
+ { 0x2e0601d4, 0xff40 }, /* 117 */
+ { 0x2e0601dc, 0x1beb }, /* 119 */
+ { 0x2e0601e0, 0x200c0 }, /* 120 */
+ { 0x2e0601e4, 0x200c0 }, /* 121 */
+ { 0x2e0601e8, 0x200c0 }, /* 122 */
+ { 0x2e0601ec, 0x200c0 }, /* 123 */
+ { 0x2e0601f0, 0x200c0 }, /* 124 */
+ { 0x2e0601f8, 0x3815 }, /* 126 */
+ { 0x2e06021c, 0x5000000 }, /* 135 */
+ { 0x2e060220, 0x5030503 }, /* 136 */
+ { 0x2e060224, 0x3 }, /* 137 */
+ { 0x2e060228, 0x7010a09 }, /* 138 */
+ { 0x2e06022c, 0xe0a09 }, /* 139 */
+ { 0x2e060230, 0x10a0900 }, /* 140 */
+ { 0x2e060234, 0xe0a0907 }, /* 141 */
+ { 0x2e060238, 0xa090000 }, /* 142 */
+ { 0x2e06023c, 0xa090701 }, /* 143 */
+ { 0x2e060240, 0x101000e }, /* 144 */
+ { 0x2e060244, 0x40003 }, /* 145 */
+ { 0x2e060248, 0x7 }, /* 146 */
+ { 0x2e060264, 0x4040100 }, /* 153 */
+ { 0x2e060268, 0x1000000 }, /* 154 */
+ { 0x2e06026c, 0x100000c0 }, /* 155 */
+ { 0x2e060270, 0x100000c0 }, /* 156 */
+ { 0x2e060274, 0x100000c0 }, /* 157 */
+ { 0x2e06027c, 0x1600 }, /* 159 */
+ { 0x2e060284, 0x1 }, /* 161 */
+ { 0x2e060288, 0x2 }, /* 162 */
+ { 0x2e06028c, 0x100e }, /* 163 */
+ { 0x2e0602a4, 0xa0000 }, /* 169 */
+ { 0x2e0602a8, 0xd0005 }, /* 170 */
+ { 0x2e0602ac, 0x404 }, /* 171 */
+ { 0x2e0602b0, 0xd }, /* 172 */
+ { 0x2e0602b4, 0x1b0035 }, /* 173 */
+ { 0x2e0602b8, 0x4040042 }, /* 174 */
+ { 0x2e0602bc, 0x42 }, /* 175 */
+ { 0x2e0602c0, 0x35006a }, /* 176 */
+ { 0x2e0602c4, 0x4040084 }, /* 177 */
+ { 0x2e0602c8, 0x84 }, /* 178 */
+ { 0x2e0602d8, 0x40004 }, /* 182 */
+ { 0x2e0602dc, 0x30000914 }, /* 183 */
+ { 0x2e0602e0, 0x3030 }, /* 184 */
+ { 0x2e0602e4, 0x44440000 }, /* 185 */
+ { 0x2e0602e8, 0x19191944 }, /* 186 */
+ { 0x2e0602ec, 0x19191908 }, /* 187 */
+ { 0x2e0602f0, 0x4000000 }, /* 188 */
+ { 0x2e0602f4, 0x40404 }, /* 189 */
+ { 0x2e0602f8, 0x9140004 }, /* 190 */
+ { 0x2e0602fc, 0x30303000 }, /* 191 */
+ { 0x2e060304, 0x19444444 }, /* 193 */
+ { 0x2e060308, 0x19081919 }, /* 194 */
+ { 0x2e06030c, 0x1919 }, /* 195 */
+ { 0x2e060310, 0x4040400 }, /* 196 */
+ { 0x2e060314, 0x1010120 }, /* 197 */
+ { 0x2e060318, 0x1000100 }, /* 198 */
+ { 0x2e06031c, 0x1 }, /* 199 */
+ { 0x2e060324, 0x1000000 }, /* 201 */
+ { 0x2e060328, 0x1 }, /* 202 */
+ { 0x2e060354, 0x11000000 }, /* 213 */
+ { 0x2e060358, 0x40c1815 }, /* 214 */
+ { 0x2e060390, 0x30000 }, /* 228 */
+ { 0x2e060394, 0x1000200 }, /* 229 */
+ { 0x2e060398, 0x310040 }, /* 230 */
+ { 0x2e06039c, 0x20002 }, /* 231 */
+ { 0x2e0603a0, 0x400100 }, /* 232 */
+ { 0x2e0603a4, 0x80108 }, /* 233 */
+ { 0x2e0603a8, 0x1000200 }, /* 234 */
+ { 0x2e0603ac, 0x2100040 }, /* 235 */
+ { 0x2e0603b0, 0x10 }, /* 236 */
+ { 0x2e0603b4, 0xe0003 }, /* 237 */
+ { 0x2e0603b8, 0x100001b }, /* 238 */
+ { 0x2e0603d8, 0xffff0b00 }, /* 246 */
+ { 0x2e0603dc, 0x1010001 }, /* 247 */
+ { 0x2e0603e0, 0x1010101 }, /* 248 */
+ { 0x2e0603e4, 0x10b0101 }, /* 249 */
+ { 0x2e0603e8, 0x10000 }, /* 250 */
+ { 0x2e0603ec, 0x4010101 }, /* 251 */
+ { 0x2e0603f0, 0x1010000 }, /* 252 */
+ { 0x2e0603f4, 0x4 }, /* 253 */
+ { 0x2e0603fc, 0x3030101 }, /* 255 */
+ { 0x2e060400, 0x103 }, /* 256 */
+ { 0x2e0604a4, 0x2020101 }, /* 297 */
+ { 0x2e0604a8, 0x10100 }, /* 298 */
+ { 0x2e0604ac, 0x1000101 }, /* 299 */
+ { 0x2e0604b0, 0x1010101 }, /* 300 */
+ { 0x2e0604b4, 0x4030300 }, /* 301 */
+ { 0x2e0604b8, 0x8080505 }, /* 302 */
+ { 0x2e0604bc, 0x8020808 }, /* 303 */
+ { 0x2e0604c0, 0x8020e00 }, /* 304 */
+ { 0x2e0604c4, 0xa020e00 }, /* 305 */
+ { 0x2e0604c8, 0x8000f00 }, /* 306 */
+ { 0x2e0604cc, 0xa08 }, /* 307 */
+ { 0x2e0604d0, 0x1010101 }, /* 308 */
+ { 0x2e0604d4, 0x102 }, /* 309 */
+ { 0x2e0604d8, 0x404 }, /* 310 */
+ { 0x2e0604dc, 0x40400 }, /* 311 */
+ { 0x2e0604e0, 0x4040000 }, /* 312 */
+ { 0x2e0604e4, 0x4000000 }, /* 313 */
+ { 0x2e0604e8, 0x10004 }, /* 314 */
+ { 0x2e0604f0, 0xfffff }, /* 316 */
+ { 0x2e0604f8, 0xfffff }, /* 318 */
+ { 0x2e060500, 0xfffff }, /* 320 */
+ { 0x2e060508, 0xfffff }, /* 322 */
+ { 0x2e060510, 0xfffff }, /* 324 */
+ { 0x2e060518, 0xfffff }, /* 326 */
+ { 0x2e060520, 0xfffff }, /* 328 */
+ { 0x2e060528, 0xfffff }, /* 330 */
+ { 0x2e060530, 0xfffff }, /* 332 */
+ { 0x2e060538, 0xfffff }, /* 334 */
+ { 0x2e060540, 0xfffff }, /* 336 */
+ { 0x2e060548, 0xfffff }, /* 338 */
+ { 0x2e060550, 0xfffff }, /* 340 */
+ { 0x2e060558, 0xfffff }, /* 342 */
+ { 0x2e060560, 0xfffff }, /* 344 */
+ { 0x2e060568, 0xfffff }, /* 346 */
+ { 0x2e060570, 0xfffff }, /* 348 */
+ { 0x2e060578, 0xfffff }, /* 350 */
+ { 0x2e060580, 0xfffff }, /* 352 */
+ { 0x2e060588, 0xfffff }, /* 354 */
+ { 0x2e060590, 0xfffff }, /* 356 */
+ { 0x2e060598, 0xfffff }, /* 358 */
+ { 0x2e0605a0, 0xfffff }, /* 360 */
+ { 0x2e0605a8, 0xfffff }, /* 362 */
+ { 0x2e0605b0, 0xfffff }, /* 364 */
+ { 0x2e0605b8, 0xfffff }, /* 366 */
+ { 0x2e0605c0, 0xfffff }, /* 368 */
+ { 0x2e0605c8, 0xfffff }, /* 370 */
+ { 0x2e0605d0, 0xfffff }, /* 372 */
+ { 0x2e0605d8, 0xfffff }, /* 374 */
+ { 0x2e0605e0, 0xfffff }, /* 376 */
+ { 0x2e0605e8, 0xfffff }, /* 378 */
+ { 0x2e0605f0, 0xfffff }, /* 380 */
+ { 0x2e0605f8, 0xfffff }, /* 382 */
+ { 0x2e060600, 0xfffff }, /* 384 */
+ { 0x2e060608, 0xfffff }, /* 386 */
+ { 0x2e060610, 0xfffff }, /* 388 */
+ { 0x2e060618, 0xfffff }, /* 390 */
+ { 0x2e060620, 0xfffff }, /* 392 */
+ { 0x2e060628, 0xfffff }, /* 394 */
+ { 0x2e060630, 0xfffff }, /* 396 */
+ { 0x2e060638, 0xfffff }, /* 398 */
+ { 0x2e060640, 0xfffff }, /* 400 */
+ { 0x2e060648, 0xfffff }, /* 402 */
+ { 0x2e060650, 0xfffff }, /* 404 */
+ { 0x2e060658, 0xfffff }, /* 406 */
+ { 0x2e060660, 0xfffff }, /* 408 */
+ { 0x2e060668, 0xfffff }, /* 410 */
+ { 0x2e060670, 0xfffff }, /* 412 */
+ { 0x2e060678, 0xfffff }, /* 414 */
+ { 0x2e060680, 0xfffff }, /* 416 */
+ { 0x2e060688, 0xfffff }, /* 418 */
+ { 0x2e060690, 0xfffff }, /* 420 */
+ { 0x2e060698, 0xfffff }, /* 422 */
+ { 0x2e0606a0, 0xfffff }, /* 424 */
+ { 0x2e0606a8, 0xfffff }, /* 426 */
+ { 0x2e0606b0, 0xfffff }, /* 428 */
+ { 0x2e0606b8, 0xfffff }, /* 430 */
+ { 0x2e0606c0, 0xfffff }, /* 432 */
+ { 0x2e0606c8, 0xfffff }, /* 434 */
+ { 0x2e0606d0, 0xfffff }, /* 436 */
+ { 0x2e0606d8, 0xfffff }, /* 438 */
+ { 0x2e0606e0, 0xfffff }, /* 440 */
+ { 0x2e0606e8, 0x30fffff }, /* 442 */
+ { 0x2e0606ec, 0xffffffff }, /* 443 */
+ { 0x2e0606f0, 0x30f0f }, /* 444 */
+ { 0x2e0606f4, 0xffffffff }, /* 445 */
+ { 0x2e0606f8, 0x30f0f }, /* 446 */
+ { 0x2e0606fc, 0xffffffff }, /* 447 */
+ { 0x2e060700, 0x30f0f }, /* 448 */
+ { 0x2e060704, 0xffffffff }, /* 449 */
+ { 0x2e060708, 0x30f0f }, /* 450 */
+ { 0x2e06070c, 0xffffffff }, /* 451 */
+ { 0x2e060710, 0x30f0f }, /* 452 */
+ { 0x2e060714, 0xffffffff }, /* 453 */
+ { 0x2e060718, 0x30f0f }, /* 454 */
+ { 0x2e06071c, 0xffffffff }, /* 455 */
+ { 0x2e060720, 0x30f0f }, /* 456 */
+ { 0x2e060724, 0xffffffff }, /* 457 */
+ { 0x2e060728, 0x30f0f }, /* 458 */
+ { 0x2e06072c, 0xffffffff }, /* 459 */
+ { 0x2e060730, 0x30f0f }, /* 460 */
+ { 0x2e060734, 0xffffffff }, /* 461 */
+ { 0x2e060738, 0x30f0f }, /* 462 */
+ { 0x2e06073c, 0xffffffff }, /* 463 */
+ { 0x2e060740, 0x30f0f }, /* 464 */
+ { 0x2e060744, 0xffffffff }, /* 465 */
+ { 0x2e060748, 0x30f0f }, /* 466 */
+ { 0x2e06074c, 0xffffffff }, /* 467 */
+ { 0x2e060750, 0x30f0f }, /* 468 */
+ { 0x2e060754, 0xffffffff }, /* 469 */
+ { 0x2e060758, 0x30f0f }, /* 470 */
+ { 0x2e06075c, 0xffffffff }, /* 471 */
+ { 0x2e060760, 0x30f0f }, /* 472 */
+ { 0x2e060764, 0xffffffff }, /* 473 */
+ { 0x2e060768, 0x30f0f }, /* 474 */
+ { 0x2e06076c, 0xffffffff }, /* 475 */
+ { 0x2e060770, 0x30f0f }, /* 476 */
+ { 0x2e060774, 0xffffffff }, /* 477 */
+ { 0x2e060778, 0x30f0f }, /* 478 */
+ { 0x2e06077c, 0xffffffff }, /* 479 */
+ { 0x2e060780, 0x30f0f }, /* 480 */
+ { 0x2e060784, 0xffffffff }, /* 481 */
+ { 0x2e060788, 0x30f0f }, /* 482 */
+ { 0x2e06078c, 0xffffffff }, /* 483 */
+ { 0x2e060790, 0x30f0f }, /* 484 */
+ { 0x2e060794, 0xffffffff }, /* 485 */
+ { 0x2e060798, 0x30f0f }, /* 486 */
+ { 0x2e06079c, 0xffffffff }, /* 487 */
+ { 0x2e0607a0, 0x30f0f }, /* 488 */
+ { 0x2e0607a4, 0xffffffff }, /* 489 */
+ { 0x2e0607a8, 0x30f0f }, /* 490 */
+ { 0x2e0607ac, 0xffffffff }, /* 491 */
+ { 0x2e0607b0, 0x30f0f }, /* 492 */
+ { 0x2e0607b4, 0xffffffff }, /* 493 */
+ { 0x2e0607b8, 0x30f0f }, /* 494 */
+ { 0x2e0607bc, 0xffffffff }, /* 495 */
+ { 0x2e0607c0, 0x30f0f }, /* 496 */
+ { 0x2e0607c4, 0xffffffff }, /* 497 */
+ { 0x2e0607c8, 0x30f0f }, /* 498 */
+ { 0x2e0607cc, 0xffffffff }, /* 499 */
+ { 0x2e0607d0, 0x30f0f }, /* 500 */
+ { 0x2e0607d4, 0xffffffff }, /* 501 */
+ { 0x2e0607d8, 0x30f0f }, /* 502 */
+ { 0x2e0607dc, 0xffffffff }, /* 503 */
+ { 0x2e0607e0, 0x30f0f }, /* 504 */
+ { 0x2e0607e4, 0xffffffff }, /* 505 */
+ { 0x2e0607e8, 0x30f0f }, /* 506 */
+ { 0x2e0607ec, 0xffffffff }, /* 507 */
+ { 0x2e0607f0, 0x30f0f }, /* 508 */
+ { 0x2e0607f4, 0xffffffff }, /* 509 */
+ { 0x2e0607f8, 0x30f0f }, /* 510 */
+ { 0x2e0607fc, 0xffffffff }, /* 511 */
+ { 0x2e060800, 0x30f0f }, /* 512 */
+ { 0x2e060804, 0xffffffff }, /* 513 */
+ { 0x2e060808, 0x30f0f }, /* 514 */
+ { 0x2e06080c, 0xffffffff }, /* 515 */
+ { 0x2e060810, 0x30f0f }, /* 516 */
+ { 0x2e060814, 0xffffffff }, /* 517 */
+ { 0x2e060818, 0x30f0f }, /* 518 */
+ { 0x2e06081c, 0xffffffff }, /* 519 */
+ { 0x2e060820, 0x30f0f }, /* 520 */
+ { 0x2e060824, 0xffffffff }, /* 521 */
+ { 0x2e060828, 0x30f0f }, /* 522 */
+ { 0x2e06082c, 0xffffffff }, /* 523 */
+ { 0x2e060830, 0x30f0f }, /* 524 */
+ { 0x2e060834, 0xffffffff }, /* 525 */
+ { 0x2e060838, 0x30f0f }, /* 526 */
+ { 0x2e06083c, 0xffffffff }, /* 527 */
+ { 0x2e060840, 0x30f0f }, /* 528 */
+ { 0x2e060844, 0xffffffff }, /* 529 */
+ { 0x2e060848, 0x30f0f }, /* 530 */
+ { 0x2e06084c, 0xffffffff }, /* 531 */
+ { 0x2e060850, 0x30f0f }, /* 532 */
+ { 0x2e060854, 0xffffffff }, /* 533 */
+ { 0x2e060858, 0x30f0f }, /* 534 */
+ { 0x2e06085c, 0xffffffff }, /* 535 */
+ { 0x2e060860, 0x30f0f }, /* 536 */
+ { 0x2e060864, 0xffffffff }, /* 537 */
+ { 0x2e060868, 0x30f0f }, /* 538 */
+ { 0x2e06086c, 0xffffffff }, /* 539 */
+ { 0x2e060870, 0x30f0f }, /* 540 */
+ { 0x2e060874, 0xffffffff }, /* 541 */
+ { 0x2e060878, 0x30f0f }, /* 542 */
+ { 0x2e06087c, 0xffffffff }, /* 543 */
+ { 0x2e060880, 0x30f0f }, /* 544 */
+ { 0x2e060884, 0xffffffff }, /* 545 */
+ { 0x2e060888, 0x30f0f }, /* 546 */
+ { 0x2e06088c, 0xffffffff }, /* 547 */
+ { 0x2e060890, 0x30f0f }, /* 548 */
+ { 0x2e060894, 0xffffffff }, /* 549 */
+ { 0x2e060898, 0x30f0f }, /* 550 */
+ { 0x2e06089c, 0xffffffff }, /* 551 */
+ { 0x2e0608a0, 0x30f0f }, /* 552 */
+ { 0x2e0608a4, 0xffffffff }, /* 553 */
+ { 0x2e0608a8, 0x30f0f }, /* 554 */
+ { 0x2e0608ac, 0xffffffff }, /* 555 */
+ { 0x2e0608b0, 0x30f0f }, /* 556 */
+ { 0x2e0608b4, 0xffffffff }, /* 557 */
+ { 0x2e0608b8, 0x30f0f }, /* 558 */
+ { 0x2e0608bc, 0xffffffff }, /* 559 */
+ { 0x2e0608c0, 0x30f0f }, /* 560 */
+ { 0x2e0608c4, 0xffffffff }, /* 561 */
+ { 0x2e0608c8, 0x30f0f }, /* 562 */
+ { 0x2e0608cc, 0xffffffff }, /* 563 */
+ { 0x2e0608d0, 0x30f0f }, /* 564 */
+ { 0x2e0608d4, 0xffffffff }, /* 565 */
+ { 0x2e0608d8, 0x30f0f }, /* 566 */
+ { 0x2e0608dc, 0xffffffff }, /* 567 */
+ { 0x2e0608e0, 0x30f0f }, /* 568 */
+ { 0x2e0608e4, 0xffffffff }, /* 569 */
+ { 0x2e0608e8, 0x32070f0f }, /* 570 */
+ { 0x2e0608ec, 0x1320001 }, /* 571 */
+ { 0x2e0608f0, 0x13200 }, /* 572 */
+ { 0x2e0608f4, 0x132 }, /* 573 */
+ { 0x2e0608fc, 0x1d1b0000 }, /* 575 */
+ { 0x2e060900, 0x21 }, /* 576 */
+ { 0x2e060904, 0xa }, /* 577 */
+ { 0x2e060908, 0x166 }, /* 578 */
+ { 0x2e06090c, 0x200 }, /* 579 */
+ { 0x2e060910, 0x200 }, /* 580 */
+ { 0x2e060914, 0x200 }, /* 581 */
+ { 0x2e060918, 0x200 }, /* 582 */
+ { 0x2e06091c, 0x432 }, /* 583 */
+ { 0x2e060920, 0xdfc }, /* 584 */
+ { 0x2e060924, 0x204 }, /* 585 */
+ { 0x2e060928, 0x7fa }, /* 586 */
+ { 0x2e06092c, 0x200 }, /* 587 */
+ { 0x2e060930, 0x200 }, /* 588 */
+ { 0x2e060934, 0x200 }, /* 589 */
+ { 0x2e060938, 0x200 }, /* 590 */
+ { 0x2e06093c, 0x17ee }, /* 591 */
+ { 0x2e060940, 0x4fc4 }, /* 592 */
+ { 0x2e060944, 0x204 }, /* 593 */
+ { 0x2e060948, 0x1006 }, /* 594 */
+ { 0x2e06094c, 0x200 }, /* 595 */
+ { 0x2e060950, 0x200 }, /* 596 */
+ { 0x2e060954, 0x200 }, /* 597 */
+ { 0x2e060958, 0x200 }, /* 598 */
+ { 0x2e06095c, 0x3012 }, /* 599 */
+ { 0x2e060960, 0xa03c }, /* 600 */
+ { 0x2e060964, 0x2020406 }, /* 601 */
+ { 0x2e060968, 0x2030202 }, /* 602 */
+ { 0x2e06096c, 0x1000202 }, /* 603 */
+ { 0x2e060970, 0x3040100 }, /* 604 */
+ { 0x2e060974, 0x10105 }, /* 605 */
+ { 0x2e060978, 0x10101 }, /* 606 */
+ { 0x2e06097c, 0x10101 }, /* 607 */
+ { 0x2e060980, 0x10001 }, /* 608 */
+ { 0x2e060984, 0x101 }, /* 609 */
+ { 0x2e060988, 0x2000201 }, /* 610 */
+ { 0x2e06098c, 0x2010000 }, /* 611 */
+ { 0x2e060990, 0x6000200 }, /* 612 */
+ { 0x2e060994, 0x3000a06 }, /* 613 */
+ { 0x2e060998, 0x2000c06 }, /* 614 */
+};
+
+/** PI settings **/
+struct dram_cfg_param ddr_pi_cfg[] = {
+ { 0x2e062000, 0xb00 }, /* 0 */
+ { 0x2e062004, 0xbeedb66f }, /* 1 */
+ { 0x2e062008, 0xabef6bd }, /* 2 */
+ { 0x2e06200c, 0x1001387 }, /* 3 */
+ { 0x2e062010, 0x1 }, /* 4 */
+ { 0x2e062014, 0x10064 }, /* 5 */
+ { 0x2e06202c, 0x101 }, /* 11 */
+ { 0x2e062030, 0x3 }, /* 12 */
+ { 0x2e062034, 0x50001 }, /* 13 */
+ { 0x2e062038, 0x3030800 }, /* 14 */
+ { 0x2e06203c, 0x1 }, /* 15 */
+ { 0x2e062040, 0x5 }, /* 16 */
+ { 0x2e062064, 0x1000000 }, /* 25 */
+ { 0x2e062068, 0xa000001 }, /* 26 */
+ { 0x2e06206c, 0x28 }, /* 27 */
+ { 0x2e062070, 0x1 }, /* 28 */
+ { 0x2e062074, 0x320005 }, /* 29 */
+ { 0x2e062080, 0x10102 }, /* 32 */
+ { 0x2e062084, 0x1 }, /* 33 */
+ { 0x2e062088, 0xaa }, /* 34 */
+ { 0x2e06208c, 0x55 }, /* 35 */
+ { 0x2e062090, 0xb5 }, /* 36 */
+ { 0x2e062094, 0x4a }, /* 37 */
+ { 0x2e062098, 0x56 }, /* 38 */
+ { 0x2e06209c, 0xa9 }, /* 39 */
+ { 0x2e0620a0, 0xa9 }, /* 40 */
+ { 0x2e0620a4, 0xb5 }, /* 41 */
+ { 0x2e0620a8, 0x10000 }, /* 42 */
+ { 0x2e0620ac, 0x100 }, /* 43 */
+ { 0x2e0620b0, 0x5050000 }, /* 44 */
+ { 0x2e0620b4, 0x13 }, /* 45 */
+ { 0x2e0620b8, 0x7d0 }, /* 46 */
+ { 0x2e0620bc, 0x300 }, /* 47 */
+ { 0x2e0620c8, 0x1000000 }, /* 50 */
+ { 0x2e0620cc, 0x10101 }, /* 51 */
+ { 0x2e0620d8, 0x10003 }, /* 54 */
+ { 0x2e0620dc, 0x170500 }, /* 55 */
+ { 0x2e0620ec, 0xa140a01 }, /* 59 */
+ { 0x2e0620f0, 0x204010a }, /* 60 */
+ { 0x2e0620f4, 0x21010 }, /* 61 */
+ { 0x2e0620f8, 0x40401 }, /* 62 */
+ { 0x2e0620fc, 0x10e0005 }, /* 63 */
+ { 0x2e062100, 0x5000001 }, /* 64 */
+ { 0x2e062104, 0x204 }, /* 65 */
+ { 0x2e062108, 0x34 }, /* 66 */
+ { 0x2e062114, 0x1000000 }, /* 69 */
+ { 0x2e062118, 0x1000000 }, /* 70 */
+ { 0x2e06211c, 0x80200 }, /* 71 */
+ { 0x2e062120, 0x2000200 }, /* 72 */
+ { 0x2e062124, 0x1000100 }, /* 73 */
+ { 0x2e062128, 0x1000000 }, /* 74 */
+ { 0x2e06212c, 0x2000200 }, /* 75 */
+ { 0x2e062130, 0x200 }, /* 76 */
+ { 0x2e062164, 0x400 }, /* 89 */
+ { 0x2e062168, 0x2010000 }, /* 90 */
+ { 0x2e06216c, 0x80103 }, /* 91 */
+ { 0x2e062174, 0x10008 }, /* 93 */
+ { 0x2e06217c, 0xaa00 }, /* 95 */
+ { 0x2e062188, 0x10000 }, /* 98 */
+ { 0x2e0621ec, 0x8 }, /* 123 */
+ { 0x2e062218, 0xf0000 }, /* 134 */
+ { 0x2e06221c, 0xa }, /* 135 */
+ { 0x2e062220, 0x19 }, /* 136 */
+ { 0x2e062224, 0x100 }, /* 137 */
+ { 0x2e062228, 0x100 }, /* 138 */
+ { 0x2e062238, 0x1000000 }, /* 142 */
+ { 0x2e06223c, 0x10003 }, /* 143 */
+ { 0x2e062240, 0x2000101 }, /* 144 */
+ { 0x2e062244, 0x1030001 }, /* 145 */
+ { 0x2e062248, 0x10400 }, /* 146 */
+ { 0x2e06224c, 0x6000105 }, /* 147 */
+ { 0x2e062250, 0x1070001 }, /* 148 */
+ { 0x2e062260, 0x10001 }, /* 152 */
+ { 0x2e062274, 0x401 }, /* 157 */
+ { 0x2e06227c, 0x10000 }, /* 159 */
+ { 0x2e062284, 0x6010000 }, /* 161 */
+ { 0x2e062288, 0xb }, /* 162 */
+ { 0x2e06228c, 0x34 }, /* 163 */
+ { 0x2e062290, 0x36 }, /* 164 */
+ { 0x2e062294, 0x2003c }, /* 165 */
+ { 0x2e062298, 0x2000200 }, /* 166 */
+ { 0x2e06229c, 0xc040c04 }, /* 167 */
+ { 0x2e0622a0, 0xe1406 }, /* 168 */
+ { 0x2e0622a4, 0xb3 }, /* 169 */
+ { 0x2e0622a8, 0x4a }, /* 170 */
+ { 0x2e0622ac, 0x3fd }, /* 171 */
+ { 0x2e0622b0, 0x94 }, /* 172 */
+ { 0x2e0622b4, 0x4000803 }, /* 173 */
+ { 0x2e0622b8, 0x1010404 }, /* 174 */
+ { 0x2e0622bc, 0x1501 }, /* 175 */
+ { 0x2e0622c0, 0x1a0018 }, /* 176 */
+ { 0x2e0622c4, 0x1000100 }, /* 177 */
+ { 0x2e0622c8, 0x100 }, /* 178 */
+ { 0x2e0622d0, 0x5040303 }, /* 180 */
+ { 0x2e0622d4, 0x1010805 }, /* 181 */
+ { 0x2e0622d8, 0x1010101 }, /* 182 */
+ { 0x2e0622e8, 0x2060404 }, /* 186 */
+ { 0x2e0622ec, 0x2020402 }, /* 187 */
+ { 0x2e0622f0, 0x3102 }, /* 188 */
+ { 0x2e0622f4, 0x340009 }, /* 189 */
+ { 0x2e0622f8, 0x36000c }, /* 190 */
+ { 0x2e0622fc, 0x101000e }, /* 191 */
+ { 0x2e062300, 0xd0101 }, /* 192 */
+ { 0x2e062304, 0x1004201 }, /* 193 */
+ { 0x2e062308, 0x1000084 }, /* 194 */
+ { 0x2e06230c, 0xe000e }, /* 195 */
+ { 0x2e062310, 0x430100 }, /* 196 */
+ { 0x2e062314, 0x1000043 }, /* 197 */
+ { 0x2e062318, 0x850085 }, /* 198 */
+ { 0x2e06231c, 0x220f220f }, /* 199 */
+ { 0x2e062320, 0x101220f }, /* 200 */
+ { 0x2e062324, 0xa070601 }, /* 201 */
+ { 0x2e062328, 0xa07060d }, /* 202 */
+ { 0x2e06232c, 0xa07070d }, /* 203 */
+ { 0x2e062330, 0xc00d }, /* 204 */
+ { 0x2e062334, 0xc01000 }, /* 205 */
+ { 0x2e062338, 0xc01000 }, /* 206 */
+ { 0x2e06233c, 0x21000 }, /* 207 */
+ { 0x2e062340, 0x11000d }, /* 208 */
+ { 0x2e062344, 0x140042 }, /* 209 */
+ { 0x2e062348, 0x190084 }, /* 210 */
+ { 0x2e06234c, 0x220f0056 }, /* 211 */
+ { 0x2e062350, 0x101 }, /* 212 */
+ { 0x2e062354, 0x560019 }, /* 213 */
+ { 0x2e062358, 0x101220f }, /* 214 */
+ { 0x2e06235c, 0x1b00 }, /* 215 */
+ { 0x2e062360, 0x220f0056 }, /* 216 */
+ { 0x2e062364, 0x8000101 }, /* 217 */
+ { 0x2e062368, 0x4090403 }, /* 218 */
+ { 0x2e06236c, 0x5eb }, /* 219 */
+ { 0x2e062370, 0x20010003 }, /* 220 */
+ { 0x2e062374, 0x80a0a03 }, /* 221 */
+ { 0x2e062378, 0x6090506 }, /* 222 */
+ { 0x2e06237c, 0x2093 }, /* 223 */
+ { 0x2e062380, 0x2001000c }, /* 224 */
+ { 0x2e062384, 0x80a0a04 }, /* 225 */
+ { 0x2e062388, 0xb090a0c }, /* 226 */
+ { 0x2e06238c, 0x4126 }, /* 227 */
+ { 0x2e062390, 0x20020017 }, /* 228 */
+ { 0x2e062394, 0xa0a08 }, /* 229 */
+ { 0x2e062398, 0x166 }, /* 230 */
+ { 0x2e06239c, 0xdfc }, /* 231 */
+ { 0x2e0623a0, 0x7fa }, /* 232 */
+ { 0x2e0623a4, 0x4fc4 }, /* 233 */
+ { 0x2e0623a8, 0x1006 }, /* 234 */
+ { 0x2e0623ac, 0xa03c }, /* 235 */
+ { 0x2e0623b0, 0x4c000e }, /* 236 */
+ { 0x2e0623b4, 0x3030098 }, /* 237 */
+ { 0x2e0623b8, 0x258103 }, /* 238 */
+ { 0x2e0623bc, 0x17702 }, /* 239 */
+ { 0x2e0623c0, 0x5 }, /* 240 */
+ { 0x2e0623c4, 0x61 }, /* 241 */
+ { 0x2e0623c8, 0xe }, /* 242 */
+ { 0x2e0623cc, 0xce3f }, /* 243 */
+ { 0x2e0623d0, 0x80e70 }, /* 244 */
+ { 0x2e0623d4, 0x5 }, /* 245 */
+ { 0x2e0623d8, 0x210 }, /* 246 */
+ { 0x2e0623dc, 0x4c }, /* 247 */
+ { 0x2e0623e0, 0x19c7d }, /* 248 */
+ { 0x2e0623e4, 0x101cdf }, /* 249 */
+ { 0x2e0623e8, 0x5 }, /* 250 */
+ { 0x2e0623ec, 0x420 }, /* 251 */
+ { 0x2e0623f0, 0x1000098 }, /* 252 */
+ { 0x2e0623f4, 0x310040 }, /* 253 */
+ { 0x2e0623f8, 0x10002 }, /* 254 */
+ { 0x2e0623fc, 0x1080040 }, /* 255 */
+ { 0x2e062400, 0x10008 }, /* 256 */
+ { 0x2e062404, 0x2100040 }, /* 257 */
+ { 0x2e062408, 0x310 }, /* 258 */
+ { 0x2e06240c, 0x1b000e }, /* 259 */
+ { 0x2e062410, 0x1010101 }, /* 260 */
+ { 0x2e062414, 0x2020101 }, /* 261 */
+ { 0x2e062418, 0x8080404 }, /* 262 */
+ { 0x2e06241c, 0x5508 }, /* 263 */
+ { 0x2e062420, 0x83c5a00 }, /* 264 */
+ { 0x2e062424, 0x55 }, /* 265 */
+ { 0x2e062428, 0x55083c5a }, /* 266 */
+ { 0x2e06242c, 0x5a000000 }, /* 267 */
+ { 0x2e062430, 0x55083c }, /* 268 */
+ { 0x2e062434, 0x3c5a0000 }, /* 269 */
+ { 0x2e062438, 0xf0e0d0c }, /* 270 */
+ { 0x2e06243c, 0xb0a0908 }, /* 271 */
+ { 0x2e062440, 0x7060504 }, /* 272 */
+ { 0x2e062444, 0x3020100 }, /* 273 */
+ { 0x2e06244c, 0x2020101 }, /* 275 */
+ { 0x2e062450, 0x8080404 }, /* 276 */
+ { 0x2e062454, 0x44300004 }, /* 277 */
+ { 0x2e062458, 0x4041919 }, /* 278 */
+ { 0x2e06245c, 0x19443000 }, /* 279 */
+ { 0x2e062460, 0x9140419 }, /* 280 */
+ { 0x2e062464, 0x19194430 }, /* 281 */
+ { 0x2e062468, 0x30000404 }, /* 282 */
+ { 0x2e06246c, 0x4191944 }, /* 283 */
+ { 0x2e062470, 0x44300004 }, /* 284 */
+ { 0x2e062474, 0x14041919 }, /* 285 */
+ { 0x2e062478, 0x19443009 }, /* 286 */
+ { 0x2e06247c, 0x40419 }, /* 287 */
+ { 0x2e062480, 0x19194430 }, /* 288 */
+ { 0x2e062484, 0x30000404 }, /* 289 */
+ { 0x2e062488, 0x4191944 }, /* 290 */
+ { 0x2e06248c, 0x44300914 }, /* 291 */
+ { 0x2e062490, 0x44041919 }, /* 292 */
+ { 0x2e062494, 0x19443000 }, /* 293 */
+ { 0x2e062498, 0x40419 }, /* 294 */
+ { 0x2e06249c, 0x19194430 }, /* 295 */
+ { 0x2e0624a0, 0x30091404 }, /* 296 */
+ { 0x2e0624a4, 0x4191944 }, /* 297 */
+};
+
+/** PHY_F1 settings **/
+struct dram_cfg_param ddr_phy_f1_cfg[] = {
+ { 0x2e064000, 0x4f0 }, /* 0 */
+ { 0x2e064008, 0x1030200 }, /* 2 */
+ { 0x2e064014, 0x3000000 }, /* 5 */
+ { 0x2e064018, 0x1000001 }, /* 6 */
+ { 0x2e06401c, 0x3000400 }, /* 7 */
+ { 0x2e064020, 0x1 }, /* 8 */
+ { 0x2e064024, 0x1 }, /* 9 */
+ { 0x2e064030, 0x10000 }, /* 12 */
+ { 0x2e064038, 0xc00004 }, /* 14 */
+ { 0x2e06403c, 0xcc0008 }, /* 15 */
+ { 0x2e064040, 0x660601 }, /* 16 */
+ { 0x2e064044, 0x3 }, /* 17 */
+ { 0x2e06404c, 0x1 }, /* 19 */
+ { 0x2e064050, 0xaaaa }, /* 20 */
+ { 0x2e064054, 0x5555 }, /* 21 */
+ { 0x2e064058, 0xb5b5 }, /* 22 */
+ { 0x2e06405c, 0x4a4a }, /* 23 */
+ { 0x2e064060, 0x5656 }, /* 24 */
+ { 0x2e064064, 0xa9a9 }, /* 25 */
+ { 0x2e064068, 0xb7b7 }, /* 26 */
+ { 0x2e06406c, 0x4848 }, /* 27 */
+ { 0x2e064078, 0x8000000 }, /* 30 */
+ { 0x2e06407c, 0x4010008 }, /* 31 */
+ { 0x2e064080, 0x408 }, /* 32 */
+ { 0x2e064084, 0x3102000 }, /* 33 */
+ { 0x2e064088, 0xc0020 }, /* 34 */
+ { 0x2e06408c, 0x10000 }, /* 35 */
+ { 0x2e064090, 0x55555555 }, /* 36 */
+ { 0x2e064094, 0xaaaaaaaa }, /* 37 */
+ { 0x2e064098, 0x55555555 }, /* 38 */
+ { 0x2e06409c, 0xaaaaaaaa }, /* 39 */
+ { 0x2e0640a0, 0x5555 }, /* 40 */
+ { 0x2e0640a4, 0x1000100 }, /* 41 */
+ { 0x2e0640a8, 0x800180 }, /* 42 */
+ { 0x2e0640ac, 0x1 }, /* 43 */
+ { 0x2e064100, 0x4 }, /* 64 */
+ { 0x2e06411c, 0x41f07ff }, /* 71 */
+ { 0x2e064120, 0x1 }, /* 72 */
+ { 0x2e064124, 0x1cc0800 }, /* 73 */
+ { 0x2e064128, 0x3003cc08 }, /* 74 */
+ { 0x2e06412c, 0x2000014e }, /* 75 */
+ { 0x2e064130, 0x7ff0200 }, /* 76 */
+ { 0x2e064134, 0x301 }, /* 77 */
+ { 0x2e064140, 0x30000 }, /* 80 */
+ { 0x2e064154, 0x2000000 }, /* 85 */
+ { 0x2e064158, 0x51515042 }, /* 86 */
+ { 0x2e06415c, 0x31c06000 }, /* 87 */
+ { 0x2e064160, 0x6bf000a }, /* 88 */
+ { 0x2e064164, 0xc0c000 }, /* 89 */
+ { 0x2e064168, 0x1000000 }, /* 90 */
+ { 0x2e06416c, 0x10001000 }, /* 91 */
+ { 0x2e064170, 0xc043242 }, /* 92 */
+ { 0x2e064174, 0xf0c1201 }, /* 93 */
+ { 0x2e064178, 0x1000140 }, /* 94 */
+ { 0x2e06417c, 0xc000120 }, /* 95 */
+ { 0x2e064180, 0x143 }, /* 96 */
+ { 0x2e064184, 0x1000203 }, /* 97 */
+ { 0x2e064188, 0x56417032 }, /* 98 */
+ { 0x2e06418c, 0x8 }, /* 99 */
+ { 0x2e064190, 0x2c302c3 }, /* 100 */
+ { 0x2e064194, 0x2c302c3 }, /* 101 */
+ { 0x2e064198, 0x2c302c3 }, /* 102 */
+ { 0x2e06419c, 0x2c302c3 }, /* 103 */
+ { 0x2e0641a0, 0x2c3 }, /* 104 */
+ { 0x2e0641a4, 0x8000 }, /* 105 */
+ { 0x2e0641a8, 0x800080 }, /* 106 */
+ { 0x2e0641ac, 0x800080 }, /* 107 */
+ { 0x2e0641b0, 0x800080 }, /* 108 */
+ { 0x2e0641b4, 0x800080 }, /* 109 */
+ { 0x2e0641b8, 0x800080 }, /* 110 */
+ { 0x2e0641bc, 0x800080 }, /* 111 */
+ { 0x2e0641c0, 0x800080 }, /* 112 */
+ { 0x2e0641c4, 0x800080 }, /* 113 */
+ { 0x2e0641c8, 0x6b0080 }, /* 114 */
+ { 0x2e0641cc, 0x1a00001 }, /* 115 */
+ { 0x2e0641d4, 0x10000 }, /* 117 */
+ { 0x2e0641d8, 0x80200 }, /* 118 */
+ { 0x2e064400, 0x4f0 }, /* 256 */
+ { 0x2e064408, 0x1030200 }, /* 258 */
+ { 0x2e064414, 0x3000000 }, /* 261 */
+ { 0x2e064418, 0x1000001 }, /* 262 */
+ { 0x2e06441c, 0x3000400 }, /* 263 */
+ { 0x2e064420, 0x1 }, /* 264 */
+ { 0x2e064424, 0x1 }, /* 265 */
+ { 0x2e064430, 0x10000 }, /* 268 */
+ { 0x2e064438, 0xc00004 }, /* 270 */
+ { 0x2e06443c, 0xcc0008 }, /* 271 */
+ { 0x2e064440, 0x660601 }, /* 272 */
+ { 0x2e064444, 0x3 }, /* 273 */
+ { 0x2e06444c, 0x1 }, /* 275 */
+ { 0x2e064450, 0xaaaa }, /* 276 */
+ { 0x2e064454, 0x5555 }, /* 277 */
+ { 0x2e064458, 0xb5b5 }, /* 278 */
+ { 0x2e06445c, 0x4a4a }, /* 279 */
+ { 0x2e064460, 0x5656 }, /* 280 */
+ { 0x2e064464, 0xa9a9 }, /* 281 */
+ { 0x2e064468, 0xb7b7 }, /* 282 */
+ { 0x2e06446c, 0x4848 }, /* 283 */
+ { 0x2e064478, 0x8000000 }, /* 286 */
+ { 0x2e06447c, 0x4010008 }, /* 287 */
+ { 0x2e064480, 0x408 }, /* 288 */
+ { 0x2e064484, 0x3102000 }, /* 289 */
+ { 0x2e064488, 0xc0020 }, /* 290 */
+ { 0x2e06448c, 0x10000 }, /* 291 */
+ { 0x2e064490, 0x55555555 }, /* 292 */
+ { 0x2e064494, 0xaaaaaaaa }, /* 293 */
+ { 0x2e064498, 0x55555555 }, /* 294 */
+ { 0x2e06449c, 0xaaaaaaaa }, /* 295 */
+ { 0x2e0644a0, 0x5555 }, /* 296 */
+ { 0x2e0644a4, 0x1000100 }, /* 297 */
+ { 0x2e0644a8, 0x800180 }, /* 298 */
+ { 0x2e064500, 0x4 }, /* 320 */
+ { 0x2e06451c, 0x41f07ff }, /* 327 */
+ { 0x2e064520, 0x1 }, /* 328 */
+ { 0x2e064524, 0x1cc0800 }, /* 329 */
+ { 0x2e064528, 0x3003cc08 }, /* 330 */
+ { 0x2e06452c, 0x2000014e }, /* 331 */
+ { 0x2e064530, 0x7ff0200 }, /* 332 */
+ { 0x2e064534, 0x301 }, /* 333 */
+ { 0x2e064540, 0x30000 }, /* 336 */
+ { 0x2e064554, 0x2000000 }, /* 341 */
+ { 0x2e064558, 0x51515042 }, /* 342 */
+ { 0x2e06455c, 0x31c06000 }, /* 343 */
+ { 0x2e064560, 0x6bf000a }, /* 344 */
+ { 0x2e064564, 0xc0c000 }, /* 345 */
+ { 0x2e064568, 0x1000000 }, /* 346 */
+ { 0x2e06456c, 0x10001000 }, /* 347 */
+ { 0x2e064570, 0xc043242 }, /* 348 */
+ { 0x2e064574, 0xf0c1201 }, /* 349 */
+ { 0x2e064578, 0x1000140 }, /* 350 */
+ { 0x2e06457c, 0xc000120 }, /* 351 */
+ { 0x2e064580, 0x143 }, /* 352 */
+ { 0x2e064584, 0x1000203 }, /* 353 */
+ { 0x2e064588, 0x30217465 }, /* 354 */
+ { 0x2e06458c, 0x8 }, /* 355 */
+ { 0x2e064590, 0x2c302c3 }, /* 356 */
+ { 0x2e064594, 0x2c302c3 }, /* 357 */
+ { 0x2e064598, 0x2c302c3 }, /* 358 */
+ { 0x2e06459c, 0x2c302c3 }, /* 359 */
+ { 0x2e0645a0, 0x2c3 }, /* 360 */
+ { 0x2e0645a4, 0x8000 }, /* 361 */
+ { 0x2e0645a8, 0x800080 }, /* 362 */
+ { 0x2e0645ac, 0x800080 }, /* 363 */
+ { 0x2e0645b0, 0x800080 }, /* 364 */
+ { 0x2e0645b4, 0x800080 }, /* 365 */
+ { 0x2e0645b8, 0x800080 }, /* 366 */
+ { 0x2e0645bc, 0x800080 }, /* 367 */
+ { 0x2e0645c0, 0x800080 }, /* 368 */
+ { 0x2e0645c4, 0x800080 }, /* 369 */
+ { 0x2e0645c8, 0x6b0080 }, /* 370 */
+ { 0x2e0645cc, 0x1a00001 }, /* 371 */
+ { 0x2e0645d4, 0x10000 }, /* 373 */
+ { 0x2e0645d8, 0x80200 }, /* 374 */
+ { 0x2e064800, 0x4f0 }, /* 512 */
+ { 0x2e064808, 0x1030200 }, /* 514 */
+ { 0x2e064814, 0x3000000 }, /* 517 */
+ { 0x2e064818, 0x1000001 }, /* 518 */
+ { 0x2e06481c, 0x3000400 }, /* 519 */
+ { 0x2e064820, 0x1 }, /* 520 */
+ { 0x2e064824, 0x1 }, /* 521 */
+ { 0x2e064830, 0x10000 }, /* 524 */
+ { 0x2e064838, 0xc00004 }, /* 526 */
+ { 0x2e06483c, 0xcc0008 }, /* 527 */
+ { 0x2e064840, 0x660601 }, /* 528 */
+ { 0x2e064844, 0x3 }, /* 529 */
+ { 0x2e06484c, 0x1 }, /* 531 */
+ { 0x2e064850, 0xaaaa }, /* 532 */
+ { 0x2e064854, 0x5555 }, /* 533 */
+ { 0x2e064858, 0xb5b5 }, /* 534 */
+ { 0x2e06485c, 0x4a4a }, /* 535 */
+ { 0x2e064860, 0x5656 }, /* 536 */
+ { 0x2e064864, 0xa9a9 }, /* 537 */
+ { 0x2e064868, 0xb7b7 }, /* 538 */
+ { 0x2e06486c, 0x4848 }, /* 539 */
+ { 0x2e064878, 0x8000000 }, /* 542 */
+ { 0x2e06487c, 0x4010008 }, /* 543 */
+ { 0x2e064880, 0x408 }, /* 544 */
+ { 0x2e064884, 0x3102000 }, /* 545 */
+ { 0x2e064888, 0xc0020 }, /* 546 */
+ { 0x2e06488c, 0x10000 }, /* 547 */
+ { 0x2e064890, 0x55555555 }, /* 548 */
+ { 0x2e064894, 0xaaaaaaaa }, /* 549 */
+ { 0x2e064898, 0x55555555 }, /* 550 */
+ { 0x2e06489c, 0xaaaaaaaa }, /* 551 */
+ { 0x2e0648a0, 0x5555 }, /* 552 */
+ { 0x2e0648a4, 0x1000100 }, /* 553 */
+ { 0x2e0648a8, 0x800180 }, /* 554 */
+ { 0x2e0648ac, 0x1 }, /* 555 */
+ { 0x2e064900, 0x4 }, /* 576 */
+ { 0x2e06491c, 0x41f07ff }, /* 583 */
+ { 0x2e064920, 0x1 }, /* 584 */
+ { 0x2e064924, 0x1cc0800 }, /* 585 */
+ { 0x2e064928, 0x3003cc08 }, /* 586 */
+ { 0x2e06492c, 0x2000014e }, /* 587 */
+ { 0x2e064930, 0x7ff0200 }, /* 588 */
+ { 0x2e064934, 0x301 }, /* 589 */
+ { 0x2e064940, 0x30000 }, /* 592 */
+ { 0x2e064954, 0x2000000 }, /* 597 */
+ { 0x2e064958, 0x51515042 }, /* 598 */
+ { 0x2e06495c, 0x31c06000 }, /* 599 */
+ { 0x2e064960, 0x6bf000a }, /* 600 */
+ { 0x2e064964, 0xc0c000 }, /* 601 */
+ { 0x2e064968, 0x1000000 }, /* 602 */
+ { 0x2e06496c, 0x10001000 }, /* 603 */
+ { 0x2e064970, 0xc043242 }, /* 604 */
+ { 0x2e064974, 0xf0c1201 }, /* 605 */
+ { 0x2e064978, 0x1000140 }, /* 606 */
+ { 0x2e06497c, 0xc000120 }, /* 607 */
+ { 0x2e064980, 0x143 }, /* 608 */
+ { 0x2e064984, 0x1000203 }, /* 609 */
+ { 0x2e064988, 0x75436012 }, /* 610 */
+ { 0x2e06498c, 0x8 }, /* 611 */
+ { 0x2e064990, 0x2c302c3 }, /* 612 */
+ { 0x2e064994, 0x2c302c3 }, /* 613 */
+ { 0x2e064998, 0x2c302c3 }, /* 614 */
+ { 0x2e06499c, 0x2c302c3 }, /* 615 */
+ { 0x2e0649a0, 0x2c3 }, /* 616 */
+ { 0x2e0649a4, 0x8000 }, /* 617 */
+ { 0x2e0649a8, 0x800080 }, /* 618 */
+ { 0x2e0649ac, 0x800080 }, /* 619 */
+ { 0x2e0649b0, 0x800080 }, /* 620 */
+ { 0x2e0649b4, 0x800080 }, /* 621 */
+ { 0x2e0649b8, 0x800080 }, /* 622 */
+ { 0x2e0649bc, 0x800080 }, /* 623 */
+ { 0x2e0649c0, 0x800080 }, /* 624 */
+ { 0x2e0649c4, 0x800080 }, /* 625 */
+ { 0x2e0649c8, 0x6b0080 }, /* 626 */
+ { 0x2e0649cc, 0x1a00001 }, /* 627 */
+ { 0x2e0649d4, 0x10000 }, /* 629 */
+ { 0x2e0649d8, 0x80200 }, /* 630 */
+ { 0x2e064c00, 0x4f0 }, /* 768 */
+ { 0x2e064c08, 0x1030200 }, /* 770 */
+ { 0x2e064c14, 0x3000000 }, /* 773 */
+ { 0x2e064c18, 0x1000001 }, /* 774 */
+ { 0x2e064c1c, 0x3000400 }, /* 775 */
+ { 0x2e064c20, 0x1 }, /* 776 */
+ { 0x2e064c24, 0x1 }, /* 777 */
+ { 0x2e064c30, 0x10000 }, /* 780 */
+ { 0x2e064c38, 0xc00004 }, /* 782 */
+ { 0x2e064c3c, 0xcc0008 }, /* 783 */
+ { 0x2e064c40, 0x660601 }, /* 784 */
+ { 0x2e064c44, 0x3 }, /* 785 */
+ { 0x2e064c4c, 0x1 }, /* 787 */
+ { 0x2e064c50, 0xaaaa }, /* 788 */
+ { 0x2e064c54, 0x5555 }, /* 789 */
+ { 0x2e064c58, 0xb5b5 }, /* 790 */
+ { 0x2e064c5c, 0x4a4a }, /* 791 */
+ { 0x2e064c60, 0x5656 }, /* 792 */
+ { 0x2e064c64, 0xa9a9 }, /* 793 */
+ { 0x2e064c68, 0xb7b7 }, /* 794 */
+ { 0x2e064c6c, 0x4848 }, /* 795 */
+ { 0x2e064c78, 0x8000000 }, /* 798 */
+ { 0x2e064c7c, 0x4010008 }, /* 799 */
+ { 0x2e064c80, 0x408 }, /* 800 */
+ { 0x2e064c84, 0x3102000 }, /* 801 */
+ { 0x2e064c88, 0xc0020 }, /* 802 */
+ { 0x2e064c8c, 0x10000 }, /* 803 */
+ { 0x2e064c90, 0x55555555 }, /* 804 */
+ { 0x2e064c94, 0xaaaaaaaa }, /* 805 */
+ { 0x2e064c98, 0x55555555 }, /* 806 */
+ { 0x2e064c9c, 0xaaaaaaaa }, /* 807 */
+ { 0x2e064ca0, 0x5555 }, /* 808 */
+ { 0x2e064ca4, 0x1000100 }, /* 809 */
+ { 0x2e064ca8, 0x800180 }, /* 810 */
+ { 0x2e064d00, 0x4 }, /* 832 */
+ { 0x2e064d1c, 0x41f07ff }, /* 839 */
+ { 0x2e064d20, 0x1 }, /* 840 */
+ { 0x2e064d24, 0x1cc0800 }, /* 841 */
+ { 0x2e064d28, 0x3003cc08 }, /* 842 */
+ { 0x2e064d2c, 0x2000014e }, /* 843 */
+ { 0x2e064d30, 0x7ff0200 }, /* 844 */
+ { 0x2e064d34, 0x301 }, /* 845 */
+ { 0x2e064d40, 0x30000 }, /* 848 */
+ { 0x2e064d54, 0x2000000 }, /* 853 */
+ { 0x2e064d58, 0x51515042 }, /* 854 */
+ { 0x2e064d5c, 0x31c06000 }, /* 855 */
+ { 0x2e064d60, 0x6bf000a }, /* 856 */
+ { 0x2e064d64, 0xc0c000 }, /* 857 */
+ { 0x2e064d68, 0x1000000 }, /* 858 */
+ { 0x2e064d6c, 0x10001000 }, /* 859 */
+ { 0x2e064d70, 0xc043242 }, /* 860 */
+ { 0x2e064d74, 0xf0c1201 }, /* 861 */
+ { 0x2e064d78, 0x1000140 }, /* 862 */
+ { 0x2e064d7c, 0xc000120 }, /* 863 */
+ { 0x2e064d80, 0x143 }, /* 864 */
+ { 0x2e064d84, 0x1000203 }, /* 865 */
+ { 0x2e064d88, 0x32017465 }, /* 866 */
+ { 0x2e064d8c, 0x8 }, /* 867 */
+ { 0x2e064d90, 0x2c302c3 }, /* 868 */
+ { 0x2e064d94, 0x2c302c3 }, /* 869 */
+ { 0x2e064d98, 0x2c302c3 }, /* 870 */
+ { 0x2e064d9c, 0x2c302c3 }, /* 871 */
+ { 0x2e064da0, 0x2c3 }, /* 872 */
+ { 0x2e064da4, 0x8000 }, /* 873 */
+ { 0x2e064da8, 0x800080 }, /* 874 */
+ { 0x2e064dac, 0x800080 }, /* 875 */
+ { 0x2e064db0, 0x800080 }, /* 876 */
+ { 0x2e064db4, 0x800080 }, /* 877 */
+ { 0x2e064db8, 0x800080 }, /* 878 */
+ { 0x2e064dbc, 0x800080 }, /* 879 */
+ { 0x2e064dc0, 0x800080 }, /* 880 */
+ { 0x2e064dc4, 0x800080 }, /* 881 */
+ { 0x2e064dc8, 0x6b0080 }, /* 882 */
+ { 0x2e064dcc, 0x1a00001 }, /* 883 */
+ { 0x2e064dd4, 0x10000 }, /* 885 */
+ { 0x2e064dd8, 0x80200 }, /* 886 */
+ { 0x2e065014, 0x100 }, /* 1029 */
+ { 0x2e065018, 0x201 }, /* 1030 */
+ { 0x2e06502c, 0x400000 }, /* 1035 */
+ { 0x2e065030, 0x80 }, /* 1036 */
+ { 0x2e065034, 0xdcba98 }, /* 1037 */
+ { 0x2e065038, 0x3000000 }, /* 1038 */
+ { 0x2e06504c, 0x2a }, /* 1043 */
+ { 0x2e065050, 0x15 }, /* 1044 */
+ { 0x2e065054, 0x15 }, /* 1045 */
+ { 0x2e065058, 0x2a }, /* 1046 */
+ { 0x2e06505c, 0x33 }, /* 1047 */
+ { 0x2e065060, 0xc }, /* 1048 */
+ { 0x2e065064, 0xc }, /* 1049 */
+ { 0x2e065068, 0x33 }, /* 1050 */
+ { 0x2e06506c, 0x543210 }, /* 1051 */
+ { 0x2e065070, 0x3f0000 }, /* 1052 */
+ { 0x2e065074, 0xf013f }, /* 1053 */
+ { 0x2e065078, 0xf }, /* 1054 */
+ { 0x2e06507c, 0x3cc }, /* 1055 */
+ { 0x2e065080, 0x30000 }, /* 1056 */
+ { 0x2e065084, 0x300 }, /* 1057 */
+ { 0x2e065088, 0x300 }, /* 1058 */
+ { 0x2e06508c, 0x300 }, /* 1059 */
+ { 0x2e065090, 0x300 }, /* 1060 */
+ { 0x2e065094, 0x300 }, /* 1061 */
+ { 0x2e065098, 0x42080010 }, /* 1062 */
+ { 0x2e06509c, 0x332 }, /* 1063 */
+ { 0x2e0650a0, 0x2 }, /* 1064 */
+ { 0x2e065414, 0x100 }, /* 1285 */
+ { 0x2e065418, 0x201 }, /* 1286 */
+ { 0x2e06542c, 0x400000 }, /* 1291 */
+ { 0x2e065430, 0x80 }, /* 1292 */
+ { 0x2e065434, 0xdcba98 }, /* 1293 */
+ { 0x2e065438, 0x3000000 }, /* 1294 */
+ { 0x2e06544c, 0x2a }, /* 1299 */
+ { 0x2e065450, 0x15 }, /* 1300 */
+ { 0x2e065454, 0x15 }, /* 1301 */
+ { 0x2e065458, 0x2a }, /* 1302 */
+ { 0x2e06545c, 0x33 }, /* 1303 */
+ { 0x2e065460, 0xc }, /* 1304 */
+ { 0x2e065464, 0xc }, /* 1305 */
+ { 0x2e065468, 0x33 }, /* 1306 */
+ { 0x2e06546c, 0x543210 }, /* 1307 */
+ { 0x2e065470, 0x3f0000 }, /* 1308 */
+ { 0x2e065474, 0xf013f }, /* 1309 */
+ { 0x2e065478, 0xf }, /* 1310 */
+ { 0x2e06547c, 0x3cc }, /* 1311 */
+ { 0x2e065480, 0x30000 }, /* 1312 */
+ { 0x2e065484, 0x300 }, /* 1313 */
+ { 0x2e065488, 0x300 }, /* 1314 */
+ { 0x2e06548c, 0x300 }, /* 1315 */
+ { 0x2e065490, 0x300 }, /* 1316 */
+ { 0x2e065494, 0x300 }, /* 1317 */
+ { 0x2e065498, 0x42080010 }, /* 1318 */
+ { 0x2e06549c, 0x332 }, /* 1319 */
+ { 0x2e0654a0, 0x2 }, /* 1320 */
+ { 0x2e065804, 0x100 }, /* 1537 */
+ { 0x2e065814, 0x50000 }, /* 1541 */
+ { 0x2e065818, 0x4000100 }, /* 1542 */
+ { 0x2e06581c, 0x55 }, /* 1543 */
+ { 0x2e06582c, 0xf0001 }, /* 1547 */
+ { 0x2e065830, 0x280040 }, /* 1548 */
+ { 0x2e065834, 0x5002 }, /* 1549 */
+ { 0x2e065838, 0x10101 }, /* 1550 */
+ { 0x2e065840, 0x90e0000 }, /* 1552 */
+ { 0x2e065844, 0x101010f }, /* 1553 */
+ { 0x2e065848, 0x10f0004 }, /* 1554 */
+ { 0x2e065854, 0x64 }, /* 1557 */
+ { 0x2e06585c, 0x1000000 }, /* 1559 */
+ { 0x2e065860, 0x8040201 }, /* 1560 */
+ { 0x2e065864, 0x2010201 }, /* 1561 */
+ { 0x2e065868, 0xf0f0f }, /* 1562 */
+ { 0x2e06586c, 0x241342 }, /* 1563 */
+ { 0x2e065874, 0x1020000 }, /* 1565 */
+ { 0x2e065878, 0x701 }, /* 1566 */
+ { 0x2e06587c, 0x54 }, /* 1567 */
+ { 0x2e065880, 0x4102000 }, /* 1568 */
+ { 0x2e065884, 0x24410 }, /* 1569 */
+ { 0x2e065888, 0x4410 }, /* 1570 */
+ { 0x2e06588c, 0x4410 }, /* 1571 */
+ { 0x2e065890, 0x4410 }, /* 1572 */
+ { 0x2e065894, 0x4410 }, /* 1573 */
+ { 0x2e065898, 0x4410 }, /* 1574 */
+ { 0x2e06589c, 0x4410 }, /* 1575 */
+ { 0x2e0658a0, 0x4410 }, /* 1576 */
+ { 0x2e0658a4, 0x4410 }, /* 1577 */
+ { 0x2e0658b0, 0x60000 }, /* 1580 */
+ { 0x2e0658b8, 0x66 }, /* 1582 */
+ { 0x2e0658bc, 0x10000 }, /* 1583 */
+ { 0x2e0658c0, 0x8 }, /* 1584 */
+ { 0x2e0658d8, 0x3000000 }, /* 1590 */
+ { 0x2e0658e8, 0x4102006 }, /* 1594 */
+ { 0x2e0658ec, 0x41020 }, /* 1595 */
+ { 0x2e0658f0, 0x1c98c98 }, /* 1596 */
+ { 0x2e0658f4, 0x3f400000 }, /* 1597 */
+ { 0x2e0658f8, 0x3f3f1f3f }, /* 1598 */
+ { 0x2e0658fc, 0x1f }, /* 1599 */
+ { 0x2e06590c, 0x1 }, /* 1603 */
+ { 0x2e06591c, 0x1 }, /* 1607 */
+ { 0x2e065920, 0x76543210 }, /* 1608 */
+ { 0x2e065924, 0x10198 }, /* 1609 */
+ { 0x2e065934, 0x40700 }, /* 1613 */
+ { 0x2e06594c, 0x2 }, /* 1619 */
+ { 0x2e065958, 0xf3c3 }, /* 1622 */
+ { 0x2e065964, 0x11542 }, /* 1625 */
+ { 0x2e065968, 0x30209bf }, /* 1626 */
+ { 0x2e06596c, 0x30000 }, /* 1627 */
+ { 0x2e065970, 0x3000300 }, /* 1628 */
+ { 0x2e065974, 0x3000300 }, /* 1629 */
+ { 0x2e065978, 0x3000300 }, /* 1630 */
+ { 0x2e06597c, 0x3000300 }, /* 1631 */
+ { 0x2e065980, 0x300 }, /* 1632 */
+ { 0x2e065984, 0x300 }, /* 1633 */
+ { 0x2e065988, 0x300 }, /* 1634 */
+ { 0x2e06598c, 0x337cc }, /* 1635 */
+ { 0x2e065990, 0x8 }, /* 1636 */
+ { 0x2e065994, 0x1b7 }, /* 1637 */
+ { 0x2e06599c, 0x1b7 }, /* 1639 */
+ { 0x2e0659a4, 0x1b700 }, /* 1641 */
+ { 0x2e0659a8, 0x1980000 }, /* 1642 */
+ { 0x2e0659ac, 0x1b7cc }, /* 1643 */
+ { 0x2e0659b4, 0x1b700 }, /* 1645 */
+ { 0x2e0659b8, 0x1980000 }, /* 1646 */
+ { 0x2e0659bc, 0x1b700 }, /* 1647 */
+ { 0x2e0659c0, 0x1980000 }, /* 1648 */
+ { 0x2e0659c4, 0x1b700 }, /* 1649 */
+ { 0x2e0659c8, 0x1980000 }, /* 1650 */
+ { 0x2e0659cc, 0x1b700 }, /* 1651 */
+ { 0x2e0659d0, 0x1980000 }, /* 1652 */
+ { 0x2e0659d4, 0x20040003 }, /* 1653 */
+};
+
+/** PHY_F2 settings **/
+struct dram_cfg_param ddr_phy_f2_cfg[] = {
+};
+
+/* ddr timing config params */
+struct dram_timing_info2 dram_timing = {
+ .ctl_cfg = ddr_ctl_cfg,
+ .ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg),
+ .pi_cfg = ddr_pi_cfg,
+ .pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg),
+ .phy_f1_cfg = ddr_phy_f1_cfg,
+ .phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg),
+ .phy_f2_cfg = ddr_phy_f2_cfg,
+ .phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg),
+ .fsp_table = { 96, 528 },
+};
#include <asm/arch/ddr.h>
#include <asm/arch/rdc.h>
#include <asm/arch/upower.h>
+#include <asm/arch/s400_api.h>
DECLARE_GLOBAL_DATA_PTR;
void spl_dram_init(void)
{
- init_clk_ddr();
- ddr_init(&dram_timing);
+ /* Reboot in dual boot setting no need to init ddr again */
+ bool ddr_enable = pcc_clock_is_enable(5, LPDDR4_PCC5_SLOT);
+
+ if (!ddr_enable) {
+ init_clk_ddr();
+ ddr_init(&dram_timing);
+ } else {
+ /* reinit pfd/pfddiv and lpavnic except pll4*/
+ cgc2_pll4_init(false);
+ }
}
u32 spl_boot_device(void)
int power_init_board(void)
{
- u32 pmic_reg;
-
- /* PMIC set bucks1-4 to PWM mode */
- upower_pmic_i2c_read(0x10, &pmic_reg);
- upower_pmic_i2c_read(0x14, &pmic_reg);
- upower_pmic_i2c_read(0x21, &pmic_reg);
- upower_pmic_i2c_read(0x2e, &pmic_reg);
-
- upower_pmic_i2c_write(0x10, 0x3d);
- upower_pmic_i2c_write(0x14, 0x7d);
- upower_pmic_i2c_write(0x21, 0x7d);
- upower_pmic_i2c_write(0x2e, 0x3d);
-
- upower_pmic_i2c_read(0x10, &pmic_reg);
- upower_pmic_i2c_read(0x14, &pmic_reg);
- upower_pmic_i2c_read(0x21, &pmic_reg);
- upower_pmic_i2c_read(0x2e, &pmic_reg);
-
- /* Set buck3 to 1.1v OD */
- upower_pmic_i2c_write(0x22, 0x28);
+ if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+ /* Set buck3 to 0.9v LD */
+ upower_pmic_i2c_write(0x22, 0x18);
+ } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+ /* Set buck3 to 1.0v ND */
+ upower_pmic_i2c_write(0x22, 0x20);
+ } else {
+ /* Set buck3 to 1.1v OD */
+ upower_pmic_i2c_write(0x22, 0x28);
+ }
+
return 0;
}
void spl_board_init(void)
{
struct udevice *dev;
+ u32 res;
+ int ret;
uclass_find_first_device(UCLASS_MISC, &dev);
/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
- /* Load the lposc fuse for single boot to work around ROM issue,
- * The fuse depends on S400 to read.
- */
- if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT)
+ /* Load the lposc fuse to work around ROM issue. The fuse depends on S400 to read. */
+ if (is_soc_rev(CHIP_REV_1_0))
load_lposc_fuse();
upower_init();
power_init_board();
+ clock_init_late();
+
/* DDR initialization */
spl_dram_init();
/* Call it after PS16 power up */
set_lpav_qos();
+
+ /* Enable A35 access to the CAAM */
+ ret = ahab_release_caam(0x7, &res);
+ if (ret)
+ printf("ahab release caam failed %d, 0x%x\n", ret, res);
}
void board_init_f(ulong dummy)
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv7m.h>
+#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv7m.h>
+#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
*/
#include <common.h>
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include <fsl_devdis.h>
#include <fsl_validate.h>
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-#endif
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
#endif
return 0;
}
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP
+/* Copyright 2016-2019, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
-#include <fsl_sec.h>
#include <fsl_devdis.h>
#include <spl.h>
#include <linux/delay.h>
in_8(&cpld_data->pcba_ver) & VERSION_MASK,
in_8(&cpld_data->vbank) & BANK_MASK);
-#ifdef CONFIG_DEBUG
+#ifdef DEBUG
printf("soft_mux_on =%x\n",
in_8(&cpld_data->soft_mux_on));
printf("cfg_rcw_src1 =%x\n",
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux();
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
int board_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <fm_eth.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
-#include <fsl_sec.h>
#include <fsl_dspi.h>
#include "../common/i2c_mux.h"
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*/
#include <common.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include "../common/i2c_mux.h"
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
return 0;
}
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <fsl_esdhc.h>
#include <power/mc34vr500_pmic.h>
#include "cpld.h"
-#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR;
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
-#include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
#endif
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
- * Copyright 2017 NXP
+ * Copyright 2017, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
-#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#include <errno.h>
#include <netdev.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/bitops.h>
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
#include <fsl_esdhc_imx.h>
#include <hwconfig.h>
#include <linux/delay.h>
-#include <power/pmic.h>
-#include <power/ltc3676_pmic.h>
-#include <power/pfuze100_pmic.h>
-#include <power/mp5416.h>
#include "common.h"
-/* UART2: Serial Console */
-static iomux_v3_cfg_t const uart2_pads[] = {
- IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart2_pads);
-}
-
/* MMC */
static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
-/*
- * I2C pad configs:
- * I2C1: GSC
- * I2C2: PMIC,PCIe Switch,Clock,Mezz
- * I2C3: Multimedia/Expansion
- */
-static struct i2c_pads_info mx6q_i2c_pad_info[] = {
- {
- .scl = {
- .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
- }, {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
- }, {
- .scl = {
- .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
- }
-};
-
-static struct i2c_pads_info mx6dl_i2c_pad_info[] = {
- {
- .scl = {
- .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
- }, {
- .scl = {
- .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
- }, {
- .scl = {
- .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
- }
-};
-
-void setup_ventana_i2c(int i2c)
-{
- struct i2c_pads_info *p;
-
- if (is_cpu_type(MXC_CPU_MX6Q))
- p = &mx6q_i2c_pad_info[i2c];
- else
- p = &mx6dl_i2c_pad_info[i2c];
-
- setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p);
-}
-
/*
* Baseboard specific GPIO
*/
}
}
-/* setup GPIO pinmux and default configuration per baseboard and env */
-void setup_board_gpio(int board, struct ventana_board_info *info)
-{
- const char *s;
- char arg[10];
- size_t len;
- int i;
- int quiet = simple_strtol(env_get("quiet"), NULL, 10);
-
- if (board >= GW_UNKNOWN)
- return;
-
- /* RS232_EN# */
- if (gpio_cfg[board].rs232_en) {
- gpio_direction_output(gpio_cfg[board].rs232_en,
- (hwconfig("rs232")) ? 0 : 1);
- }
-
- /* MSATA Enable */
- if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
- gpio_direction_output(GP_MSATA_SEL,
- (hwconfig("msata")) ? 1 : 0);
- }
-
- /* USBOTG Select (PCISKT or FrontPanel) */
- if (gpio_cfg[board].usb_sel) {
- gpio_direction_output(gpio_cfg[board].usb_sel,
- (hwconfig("usb_pcisel")) ? 1 : 0);
- }
-
- /*
- * Configure DIO pinmux/padctl registers
- * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
- */
- for (i = 0; i < gpio_cfg[board].dio_num; i++) {
- struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
- iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
- unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
-
- if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
- continue;
- sprintf(arg, "dio%d", i);
- if (!hwconfig(arg))
- continue;
- s = hwconfig_subarg(arg, "padctrl", &len);
- if (s) {
- ctrl = MUX_PAD_CTRL(hextoul(s, NULL)
- & 0x1ffff) | MUX_MODE_SION;
- }
- if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
- if (!quiet) {
- printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
- (cfg->gpio_param/32)+1,
- cfg->gpio_param%32,
- cfg->gpio_param);
- }
- imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
- ctrl);
- gpio_requestf(cfg->gpio_param, "dio%d", i);
- gpio_direction_input(cfg->gpio_param);
- } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
- cfg->pwm_padmux) {
- if (!cfg->pwm_param) {
- printf("DIO%d: Error: pwm config invalid\n",
- i);
- continue;
- }
- if (!quiet)
- printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
- imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
- MUX_PAD_CTRL(ctrl));
- }
- }
-
- if (!quiet) {
- if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
- printf("MSATA: %s\n", (hwconfig("msata") ?
- "enabled" : "disabled"));
- }
- if (gpio_cfg[board].rs232_en) {
- printf("RS232: %s\n", (hwconfig("rs232")) ?
- "enabled" : "disabled");
- }
- }
-}
-
-/* setup board specific PMIC */
-void setup_pmic(void)
-{
- struct pmic *p;
- struct ventana_board_info ventana_info;
- int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
- const int i2c_pmic = 1;
- u32 reg;
- char rev;
- int i;
-
- /* determine board revision */
- rev = 'A';
- for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
- if (ventana_info.model[i] >= 'A') {
- rev = ventana_info.model[i];
- break;
- }
- }
-
- i2c_set_bus_num(i2c_pmic);
-
- /* configure PFUZE100 PMIC */
- if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
- debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
- power_pfuze100_init(i2c_pmic);
- p = pmic_get("PFUZE100");
- if (p && !pmic_probe(p)) {
- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
-
- /* Set VGEN1 to 1.5V and enable */
- pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
- reg &= ~(LDO_VOL_MASK);
- reg |= (LDOA_1_50V | LDO_EN);
- pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
-
- /* Set SWBST to 5.0V and enable */
- pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
- reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
- reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
- pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
-
- if (board == GW54xx && (rev == 'G')) {
- /* Disable VGEN5 */
- pmic_reg_write(p, PFUZE100_VGEN5VOL, 0);
-
- /* Set VGEN6 to 2.5V and enable */
- pmic_reg_read(p, PFUZE100_VGEN6VOL, ®);
- reg &= ~(LDO_VOL_MASK);
- reg |= (LDOB_2_50V | LDO_EN);
- pmic_reg_write(p, PFUZE100_VGEN6VOL, reg);
- }
- }
-
- /* put all switchers in continuous mode */
- pmic_reg_read(p, PFUZE100_SW1ABMODE, ®);
- reg &= ~(SW_MODE_MASK);
- reg |= PWM_PWM;
- pmic_reg_write(p, PFUZE100_SW1ABMODE, reg);
-
- pmic_reg_read(p, PFUZE100_SW2MODE, ®);
- reg &= ~(SW_MODE_MASK);
- reg |= PWM_PWM;
- pmic_reg_write(p, PFUZE100_SW2MODE, reg);
-
- pmic_reg_read(p, PFUZE100_SW3AMODE, ®);
- reg &= ~(SW_MODE_MASK);
- reg |= PWM_PWM;
- pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
-
- pmic_reg_read(p, PFUZE100_SW3BMODE, ®);
- reg &= ~(SW_MODE_MASK);
- reg |= PWM_PWM;
- pmic_reg_write(p, PFUZE100_SW3BMODE, reg);
-
- pmic_reg_read(p, PFUZE100_SW4MODE, ®);
- reg &= ~(SW_MODE_MASK);
- reg |= PWM_PWM;
- pmic_reg_write(p, PFUZE100_SW4MODE, reg);
- }
-
- /* configure LTC3676 PMIC */
- else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
- debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
- power_ltc3676_init(i2c_pmic);
- p = pmic_get("LTC3676_PMIC");
- if (!p || pmic_probe(p))
- return;
- puts("PMIC: LTC3676\n");
- /*
- * set board-specific scalar for max CPU frequency
- * per CPU based on the LDO enabled Operating Ranges
- * defined in the respective IMX6DQ and IMX6SDL
- * datasheets. The voltage resulting from the R1/R2
- * feedback inputs on Ventana is 1308mV. Note that this
- * is a bit shy of the Vmin of 1350mV in the datasheet
- * for LDO enabled mode but is as high as we can go.
- */
- switch (board) {
- case GW560x:
- /* mask PGOOD during SW3 transition */
- pmic_reg_write(p, LTC3676_DVB3B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW3 (VDD_ARM) */
- pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
- break;
- case GW5903:
- /* mask PGOOD during SW3 transition */
- pmic_reg_write(p, LTC3676_DVB3B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW3 (VDD_ARM) */
- pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
-
- /* mask PGOOD during SW4 transition */
- pmic_reg_write(p, LTC3676_DVB4B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW4 (VDD_SOC) */
- pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
- break;
- case GW5905:
- /* mask PGOOD during SW1 transition */
- pmic_reg_write(p, LTC3676_DVB1B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW1 (VDD_ARM) */
- pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
-
- /* mask PGOOD during SW3 transition */
- pmic_reg_write(p, LTC3676_DVB3B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW3 (VDD_SOC) */
- pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
- break;
- default:
- /* mask PGOOD during SW1 transition */
- pmic_reg_write(p, LTC3676_DVB1B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW1 (VDD_SOC) */
- pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
-
- /* mask PGOOD during SW3 transition */
- pmic_reg_write(p, LTC3676_DVB3B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW3 (VDD_ARM) */
- pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
- }
-
- /* put all switchers in continuous mode */
- pmic_reg_write(p, LTC3676_BUCK1, 0xc0);
- pmic_reg_write(p, LTC3676_BUCK2, 0xc0);
- pmic_reg_write(p, LTC3676_BUCK3, 0xc0);
- pmic_reg_write(p, LTC3676_BUCK4, 0xc0);
- }
-
- /* configure MP5416 PMIC */
- else if (!i2c_probe(0x69)) {
- puts("PMIC: MP5416\n");
- switch (board) {
- case GW5910:
- /* SW1: VDD_ARM 1.2V -> (1.275 to 1.475) */
- reg = MP5416_VSET_EN | MP5416_VSET_SW1_SVAL(1475000);
- i2c_write(0x69, MP5416_VSET_SW1, 1, (uint8_t *)®, 1);
- /* SW4: VDD_SOC 1.2V -> (1.350 to 1.475) */
- reg = MP5416_VSET_EN | MP5416_VSET_SW4_SVAL(1475000);
- i2c_write(0x69, MP5416_VSET_SW4, 1, (uint8_t *)®, 1);
- break;
- }
- }
-}
-
-#include <fdt_support.h>
-#define WDOG1_ADDR 0x20bc000
-#define WDOG2_ADDR 0x20c0000
-#define GPIO3_ADDR 0x20a4000
-#define USDHC3_ADDR 0x2198000
-
-static void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
-{
- int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
-
- if (off) {
- fdt_delprop(blob, off, "ext-reset-output");
- fdt_delprop(blob, off, "fsl,ext-reset-output");
- }
-}
-
-void ft_early_fixup(void *blob, int board_type)
-{
- struct ventana_board_info *info = &ventana_info;
- char rev = 0;
- int i;
-
- /* determine board revision */
- for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
- if (ventana_info.model[i] >= 'A') {
- rev = ventana_info.model[i];
- break;
- }
- }
-
- /*
- * Board model specific fixups
- */
- switch (board_type) {
- case GW51xx:
- /*
- * disable wdog node for GW51xx-A/B to work around
- * errata causing wdog timer to be unreliable.
- */
- if (rev >= 'A' && rev < 'C') {
- i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
- WDOG1_ADDR);
- if (i)
- fdt_status_disabled(blob, i);
- }
-
- /* GW51xx-E adds WDOG1_B external reset */
- if (rev < 'E')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- break;
-
- case GW52xx:
- /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
- if (info->model[4] == '2') {
- u32 handle = 0;
- u32 *range = NULL;
-
- i = fdt_node_offset_by_compatible(blob, -1,
- "fsl,imx6q-pcie");
- if (i)
- range = (u32 *)fdt_getprop(blob, i,
- "reset-gpio", NULL);
-
- if (range) {
- i = fdt_node_offset_by_compat_reg(blob,
- "fsl,imx6q-gpio", GPIO3_ADDR);
- if (i)
- handle = fdt_get_phandle(blob, i);
- if (handle) {
- range[0] = cpu_to_fdt32(handle);
- range[1] = cpu_to_fdt32(23);
- }
- }
-
- /* these have broken usd_vsel */
- if (strstr((const char *)info->model, "SP318-B") ||
- strstr((const char *)info->model, "SP331-B"))
- gpio_cfg[board_type].usd_vsel = 0;
-
- /* GW522x-B adds WDOG1_B external reset */
- if (rev < 'B')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- }
-
- /* GW520x-E adds WDOG1_B external reset */
- else if (info->model[4] == '0' && rev < 'E')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- break;
-
- case GW53xx:
- /* GW53xx-E adds WDOG1_B external reset */
- if (rev < 'E')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
-
- /* GW53xx-G has an adv7280 instead of an adv7180 */
- else if (rev > 'F') {
- i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
- if (i) {
- fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
- fdt_setprop_empty(blob, i, "adv,force-bt656-4");
- }
- }
- break;
-
- case GW54xx:
- /*
- * disable serial2 node for GW54xx for compatibility with older
- * 3.10.x kernel that improperly had this node enabled in the DT
- */
- fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED);
-
- /* GW54xx-E adds WDOG2_B external reset */
- if (rev < 'E')
- ft_board_wdog_fixup(blob, WDOG2_ADDR);
-
- /* GW54xx-G has an adv7280 instead of an adv7180 */
- else if (rev > 'F') {
- i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
- if (i) {
- fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
- fdt_setprop_empty(blob, i, "adv,force-bt656-4");
- }
- }
- break;
-
- case GW551x:
- /* GW551x-C adds WDOG1_B external reset */
- if (rev < 'C')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- break;
- case GW5901:
- case GW5902:
- /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
- if (rev < 'B')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- break;
- }
-
- /* remove no-1-8-v if UHS-I support is present */
- if (gpio_cfg[board_type].usd_vsel) {
- debug("Enabling UHS-I support\n");
- i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
- USDHC3_ADDR);
- if (i)
- fdt_delprop(blob, i, "no-1-8-v");
- }
-}
-
#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[2];
extern struct ventana gpio_cfg[GW_UNKNOWN];
-/* configure i2c iomux */
-void setup_ventana_i2c(int);
-/* configure uart iomux */
-void setup_iomux_uart(void);
-/* conifgure PMIC */
-void setup_pmic(void);
/* configure gpio iomux/defaults */
void setup_iomux_gpio(int board, struct ventana_board_info *);
-/* late setup of GPIO (configuration per baseboard and env) */
-void setup_board_gpio(int board, struct ventana_board_info *);
-/* early model/revision ft fixups */
-void ft_early_fixup(void *fdt, int board_type);
#endif /* #ifndef _GWVENTANA_COMMON_H_ */
#include <malloc.h>
#include <asm/bitops.h>
#include <linux/delay.h>
+#include <dm/uclass.h>
#include "gsc.h"
#include "ventana_eeprom.h"
* board may be ready to probe the GSC before its firmware is
* running. We will wait here indefinately for the GSC/EEPROM.
*/
+#if CONFIG_IS_ENABLED(DM_I2C)
+ while (1) {
+ if (i2c_get_dev(bus, GSC_EEPROM_ADDR))
+ break;
+ mdelay(1);
+ }
+#else
while (1) {
if (0 == i2c_set_bus_num(bus) &&
0 == i2c_probe(GSC_EEPROM_ADDR))
break;
mdelay(1);
}
+#endif
/* read eeprom config section */
mdelay(10);
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
#include "ventana_eeprom.h"
#include "gsc.h"
DECLARE_GLOBAL_DATA_PTR;
+#if CONFIG_IS_ENABLED(DM_I2C)
+struct udevice *i2c_get_dev(int busno, int slave)
+{
+ struct udevice *dev, *bus;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
+ if (ret)
+ return NULL;
+ ret = dm_i2c_probe(bus, slave, 0, &dev);
+ if (ret)
+ return NULL;
+
+ return dev;
+}
+#endif
+
/*
* The Gateworks System Controller will fail to ACK a master transaction if
* it is busy, which can occur during its 1HZ timer tick while reading ADC's.
int retry = 3;
int n = 0;
int ret;
+#if CONFIG_IS_ENABLED(DM_I2C)
+ struct udevice *dev;
+
+ dev = i2c_get_dev(CONFIG_I2C_GSC, chip);
+ if (!dev)
+ return -ENODEV;
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret) {
+ puts("EEPROM: Failed to set alen\n");
+ return ret;
+ }
+#else
+ i2c_set_bus_num(CONFIG_I2C_GSC);
+#endif
while (n++ < retry) {
+#if CONFIG_IS_ENABLED(DM_I2C)
+ ret = dm_i2c_read(dev, addr, buf, len);
+#else
ret = i2c_read(chip, addr, alen, buf, len);
+#endif
if (!ret)
break;
debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
n, ret);
- if (ret != -ENODEV)
+ if (ret != -EREMOTEIO)
break;
mdelay(10);
}
int retry = 3;
int n = 0;
int ret;
+#if CONFIG_IS_ENABLED(DM_I2C)
+ struct udevice *dev;
+
+ dev = i2c_get_dev(CONFIG_I2C_GSC, chip);
+ if (!dev)
+ return -ENODEV;
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret) {
+ puts("EEPROM: Failed to set alen\n");
+ return ret;
+ }
+#endif
while (n++ < retry) {
+#if CONFIG_IS_ENABLED(DM_I2C)
+ ret = dm_i2c_write(dev, addr, buf, len);
+#else
ret = i2c_write(chip, addr, alen, buf, len);
+#endif
if (!ret)
break;
debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
n, ret);
- if (ret != -ENODEV)
+ if (ret != -EREMOTEIO)
break;
mdelay(10);
}
node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
if (node <= 0)
return node;
- i2c_set_bus_num(0);
/* iterate over hwmon nodes */
node = fdt_first_subnode(fdt, node);
node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
if (node <= 0)
return node;
- i2c_set_bus_num(0);
/* iterate over hwmon nodes */
node = fdt_first_subnode(fdt, node);
{
unsigned char buf[16];
- i2c_set_bus_num(0);
if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
return CMD_RET_FAILURE;
{
u8 reg;
- i2c_set_bus_num(CONFIG_I2C_GSC);
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
reg |= (1 << GSC_SC_CTRL1_WDDIS);
if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
secs = dectoul(argv[1], NULL);
printf("GSC Sleeping for %ld seconds\n", secs);
- i2c_set_bus_num(0);
reg = (secs >> 24) & 0xff;
if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1))
goto error;
if (argc > 2)
timeout = dectoul(argv[2], NULL);
- i2c_set_bus_num(0);
if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
return CMD_RET_FAILURE;
reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
printf("GSC Watchdog enabled with timeout=%d seconds\n",
timeout);
} else if (strcasecmp(argv[1], "disable") == 0) {
- i2c_set_bus_num(0);
if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
return CMD_RET_FAILURE;
reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
int gsc_info(int verbose);
int gsc_boot_wd_disable(void);
const char *gsc_get_dtb_name(int level, char *buf, int sz);
+struct udevice *i2c_get_dev(int busno, int slave);
#endif
return 0;
}
- return i2c_set_bus_num(dev->bus) == 0 &&
- i2c_probe(dev->addr) == 0;
+ return (i2c_get_dev(dev->bus, dev->addr) ? 1 : 0);
}
static void enable_lvds(struct display_info_t const *dev)
}
#endif /* CONFIG_VIDEO_IPUV3 */
-/* setup board specific PMIC */
-int power_init_board(void)
-{
- setup_pmic();
- return 0;
-}
-
/*
* Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
* GPIO's as PERST# signals for its downstream ports - configure the GPIO's
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/* read Gateworks EEPROM into global struct (used later) */
- setup_ventana_i2c(0);
board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
- setup_ventana_i2c(1);
- setup_ventana_i2c(2);
-
setup_iomux_gpio(board_type, &ventana_info);
return 0;
};
#endif
+/* setup GPIO pinmux and default configuration per baseboard and env */
+void setup_board_gpio(int board, struct ventana_board_info *info)
+{
+ const char *s;
+ char arg[10];
+ size_t len;
+ int i;
+ int quiet = simple_strtol(env_get("quiet"), NULL, 10);
+
+ if (board >= GW_UNKNOWN)
+ return;
+
+ /* RS232_EN# */
+ if (gpio_cfg[board].rs232_en) {
+ gpio_direction_output(gpio_cfg[board].rs232_en,
+ (hwconfig("rs232")) ? 0 : 1);
+ }
+
+ /* MSATA Enable */
+ if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
+ gpio_direction_output(GP_MSATA_SEL,
+ (hwconfig("msata")) ? 1 : 0);
+ }
+
+ /* USBOTG Select (PCISKT or FrontPanel) */
+ if (gpio_cfg[board].usb_sel) {
+ gpio_direction_output(gpio_cfg[board].usb_sel,
+ (hwconfig("usb_pcisel")) ? 1 : 0);
+ }
+
+ /*
+ * Configure DIO pinmux/padctl registers
+ * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
+ */
+ for (i = 0; i < gpio_cfg[board].dio_num; i++) {
+ struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
+ iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
+ unsigned int cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
+
+ if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
+ continue;
+ sprintf(arg, "dio%d", i);
+ if (!hwconfig(arg))
+ continue;
+ s = hwconfig_subarg(arg, "padctrl", &len);
+ if (s) {
+ ctrl = MUX_PAD_CTRL(hextoul(s, NULL)
+ & 0x1ffff) | MUX_MODE_SION;
+ }
+ if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
+ if (!quiet) {
+ printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
+ (cfg->gpio_param / 32) + 1,
+ cfg->gpio_param % 32,
+ cfg->gpio_param);
+ }
+ imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
+ ctrl);
+ gpio_requestf(cfg->gpio_param, "dio%d", i);
+ gpio_direction_input(cfg->gpio_param);
+ } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
+ cfg->pwm_padmux) {
+ if (!cfg->pwm_param) {
+ printf("DIO%d: Error: pwm config invalid\n",
+ i);
+ continue;
+ }
+ if (!quiet)
+ printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
+ imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
+ MUX_PAD_CTRL(ctrl));
+ }
+ }
+
+ if (!quiet) {
+ if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
+ printf("MSATA: %s\n", (hwconfig("msata") ?
+ "enabled" : "disabled"));
+ }
+ if (gpio_cfg[board].rs232_en) {
+ printf("RS232: %s\n", (hwconfig("rs232")) ?
+ "enabled" : "disabled");
+ }
+ }
+}
/* late init */
int misc_init_r(void)
{
*/
if ((dev->vendor == PCI_VENDOR_ID_TI) &&
(dev->device == 0x8240) &&
- (i2c_set_bus_num(1) == 0) &&
- (i2c_probe(0x50) == 0))
+ i2c_get_dev(1, 0x50))
{
np = fdt_add_pci_path(blob, dev);
if (np > 0)
}
#endif /* if defined(CONFIG_CMD_PCI) */
+#define WDOG1_ADDR 0x20bc000
+#define WDOG2_ADDR 0x20c0000
+#define GPIO3_ADDR 0x20a4000
+#define USDHC3_ADDR 0x2198000
+static void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
+{
+ int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
+
+ if (off) {
+ fdt_delprop(blob, off, "ext-reset-output");
+ fdt_delprop(blob, off, "fsl,ext-reset-output");
+ }
+}
+
+void ft_early_fixup(void *blob, int board_type)
+{
+ struct ventana_board_info *info = &ventana_info;
+ char rev = 0;
+ int i;
+
+ /* determine board revision */
+ for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
+ if (ventana_info.model[i] >= 'A') {
+ rev = ventana_info.model[i];
+ break;
+ }
+ }
+
+ /*
+ * Board model specific fixups
+ */
+ switch (board_type) {
+ case GW51xx:
+ /*
+ * disable wdog node for GW51xx-A/B to work around
+ * errata causing wdog timer to be unreliable.
+ */
+ if (rev >= 'A' && rev < 'C') {
+ i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
+ WDOG1_ADDR);
+ if (i)
+ fdt_status_disabled(blob, i);
+ }
+
+ /* GW51xx-E adds WDOG1_B external reset */
+ if (rev < 'E')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ break;
+
+ case GW52xx:
+ /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
+ if (info->model[4] == '2') {
+ u32 handle = 0;
+ u32 *range = NULL;
+
+ i = fdt_node_offset_by_compatible(blob, -1,
+ "fsl,imx6q-pcie");
+ if (i)
+ range = (u32 *)fdt_getprop(blob, i,
+ "reset-gpio", NULL);
+
+ if (range) {
+ i = fdt_node_offset_by_compat_reg(blob,
+ "fsl,imx6q-gpio", GPIO3_ADDR);
+ if (i)
+ handle = fdt_get_phandle(blob, i);
+ if (handle) {
+ range[0] = cpu_to_fdt32(handle);
+ range[1] = cpu_to_fdt32(23);
+ }
+ }
+
+ /* these have broken usd_vsel */
+ if (strstr((const char *)info->model, "SP318-B") ||
+ strstr((const char *)info->model, "SP331-B"))
+ gpio_cfg[board_type].usd_vsel = 0;
+
+ /* GW522x-B adds WDOG1_B external reset */
+ if (rev < 'B')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ }
+
+ /* GW520x-E adds WDOG1_B external reset */
+ else if (info->model[4] == '0' && rev < 'E')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ break;
+
+ case GW53xx:
+ /* GW53xx-E adds WDOG1_B external reset */
+ if (rev < 'E')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+
+ /* GW53xx-G has an adv7280 instead of an adv7180 */
+ else if (rev > 'F') {
+ i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
+ if (i) {
+ fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
+ fdt_setprop_empty(blob, i, "adv,force-bt656-4");
+ }
+ }
+ break;
+
+ case GW54xx:
+ /*
+ * disable serial2 node for GW54xx for compatibility with older
+ * 3.10.x kernel that improperly had this node enabled in the DT
+ */
+ fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED);
+
+ /* GW54xx-E adds WDOG2_B external reset */
+ if (rev < 'E')
+ ft_board_wdog_fixup(blob, WDOG2_ADDR);
+
+ /* GW54xx-G has an adv7280 instead of an adv7180 */
+ else if (rev > 'F') {
+ i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
+ if (i) {
+ fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
+ fdt_setprop_empty(blob, i, "adv,force-bt656-4");
+ }
+ }
+ break;
+
+ case GW551x:
+ /* GW551x-C adds WDOG1_B external reset */
+ if (rev < 'C')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ break;
+ case GW5901:
+ case GW5902:
+ /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
+ if (rev < 'B')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ break;
+ }
+
+ /* remove no-1-8-v if UHS-I support is present */
+ if (gpio_cfg[board_type].usd_vsel) {
+ debug("Enabling UHS-I support\n");
+ i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
+ USDHC3_ADDR);
+ if (i)
+ fdt_delprop(blob, i, "no-1-8-v");
+ }
+}
+
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
#include <env.h>
#include <i2c.h>
#include <spl.h>
+#include <power/pmic.h>
+#include <power/ltc3676_pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <power/mp5416.h>
#include "gsc.h"
#include "common.h"
writel(0x000003FF, &ccm->CCGR6);
}
+/* UART2: Serial Console */
+static const iomux_v3_cfg_t uart2_pads[] = {
+ IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart2_pads);
+}
+
+/*
+ * I2C pad configs:
+ * I2C1: GSC
+ * I2C2: PMIC,PCIe Switch,Clock,Mezz
+ * I2C3: Multimedia/Expansion
+ */
+static struct i2c_pads_info mx6q_i2c_pad_info[] = {
+ {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+ }, {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+ }, {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+ }
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info[] = {
+ {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+ }, {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+ }, {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+ }
+};
+
+static void setup_ventana_i2c(int i2c)
+{
+ struct i2c_pads_info *p;
+
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ p = &mx6q_i2c_pad_info[i2c];
+ else
+ p = &mx6dl_i2c_pad_info[i2c];
+
+ setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p);
+}
+
+/* setup board specific PMIC */
+void setup_pmic(void)
+{
+ struct pmic *p;
+ struct ventana_board_info ventana_info;
+ int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+ const int i2c_pmic = 1;
+ u32 reg;
+ char rev;
+ int i;
+
+ /* determine board revision */
+ rev = 'A';
+ for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
+ if (ventana_info.model[i] >= 'A') {
+ rev = ventana_info.model[i];
+ break;
+ }
+ }
+
+ i2c_set_bus_num(i2c_pmic);
+
+ /* configure PFUZE100 PMIC */
+ if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
+ debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
+ power_pfuze100_init(i2c_pmic);
+ p = pmic_get("PFUZE100");
+ if (p && !pmic_probe(p)) {
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set VGEN1 to 1.5V and enable */
+ pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
+ reg &= ~(LDO_VOL_MASK);
+ reg |= (LDOA_1_50V | LDO_EN);
+ pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
+
+ /* Set SWBST to 5.0V and enable */
+ pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
+ reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+ reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
+ pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+
+ if (board == GW54xx && (rev == 'G')) {
+ /* Disable VGEN5 */
+ pmic_reg_write(p, PFUZE100_VGEN5VOL, 0);
+
+ /* Set VGEN6 to 2.5V and enable */
+ pmic_reg_read(p, PFUZE100_VGEN6VOL, ®);
+ reg &= ~(LDO_VOL_MASK);
+ reg |= (LDOB_2_50V | LDO_EN);
+ pmic_reg_write(p, PFUZE100_VGEN6VOL, reg);
+ }
+ }
+
+ /* put all switchers in continuous mode */
+ pmic_reg_read(p, PFUZE100_SW1ABMODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW1ABMODE, reg);
+
+ pmic_reg_read(p, PFUZE100_SW2MODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW2MODE, reg);
+
+ pmic_reg_read(p, PFUZE100_SW3AMODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
+
+ pmic_reg_read(p, PFUZE100_SW3BMODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW3BMODE, reg);
+
+ pmic_reg_read(p, PFUZE100_SW4MODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW4MODE, reg);
+ }
+
+ /* configure LTC3676 PMIC */
+ else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
+ debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
+ power_ltc3676_init(i2c_pmic);
+ p = pmic_get("LTC3676_PMIC");
+ if (!p || pmic_probe(p))
+ return;
+ puts("PMIC: LTC3676\n");
+ /*
+ * set board-specific scalar for max CPU frequency
+ * per CPU based on the LDO enabled Operating Ranges
+ * defined in the respective IMX6DQ and IMX6SDL
+ * datasheets. The voltage resulting from the R1/R2
+ * feedback inputs on Ventana is 1308mV. Note that this
+ * is a bit shy of the Vmin of 1350mV in the datasheet
+ * for LDO enabled mode but is as high as we can go.
+ */
+ switch (board) {
+ case GW560x:
+ /* mask PGOOD during SW3 transition */
+ pmic_reg_write(p, LTC3676_DVB3B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW3 (VDD_ARM) */
+ pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+ break;
+ case GW5903:
+ /* mask PGOOD during SW3 transition */
+ pmic_reg_write(p, LTC3676_DVB3B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW3 (VDD_ARM) */
+ pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+
+ /* mask PGOOD during SW4 transition */
+ pmic_reg_write(p, LTC3676_DVB4B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW4 (VDD_SOC) */
+ pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
+ break;
+ case GW5905:
+ /* mask PGOOD during SW1 transition */
+ pmic_reg_write(p, LTC3676_DVB1B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW1 (VDD_ARM) */
+ pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
+
+ /* mask PGOOD during SW3 transition */
+ pmic_reg_write(p, LTC3676_DVB3B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW3 (VDD_SOC) */
+ pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+ break;
+ default:
+ /* mask PGOOD during SW1 transition */
+ pmic_reg_write(p, LTC3676_DVB1B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW1 (VDD_SOC) */
+ pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
+
+ /* mask PGOOD during SW3 transition */
+ pmic_reg_write(p, LTC3676_DVB3B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW3 (VDD_ARM) */
+ pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+ }
+
+ /* put all switchers in continuous mode */
+ pmic_reg_write(p, LTC3676_BUCK1, 0xc0);
+ pmic_reg_write(p, LTC3676_BUCK2, 0xc0);
+ pmic_reg_write(p, LTC3676_BUCK3, 0xc0);
+ pmic_reg_write(p, LTC3676_BUCK4, 0xc0);
+ }
+
+ /* configure MP5416 PMIC */
+ else if (!i2c_probe(0x69)) {
+ puts("PMIC: MP5416\n");
+ switch (board) {
+ case GW5910:
+ /* SW1: VDD_ARM 1.2V -> (1.275 to 1.475) */
+ reg = MP5416_VSET_EN | MP5416_VSET_SW1_SVAL(1475000);
+ i2c_write(0x69, MP5416_VSET_SW1, 1, (uint8_t *)®, 1);
+ /* SW4: VDD_SOC 1.2V -> (1.350 to 1.475) */
+ reg = MP5416_VSET_EN | MP5416_VSET_SW4_SVAL(1475000);
+ i2c_write(0x69, MP5416_VSET_SW4, 1, (uint8_t *)®, 1);
+ break;
+ }
+ }
+}
+
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
return ret;
}
#endif
-
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
- ft_early_fixup(spl_image->fdt_addr, board_type);
-}
if (ret)
hang();
- return ((16 << som_info.sdram_size) / 1024);
+ return (16 << som_info.sdram_size);
}
const char *gsc_get_model(void)
#define __LPDDR4_TIMING_H__
#ifdef CONFIG_IMX8MM
+extern struct dram_timing_info dram_timing_512mb;
extern struct dram_timing_info dram_timing_1gb;
extern struct dram_timing_info dram_timing_2gb;
extern struct dram_timing_info dram_timing_4gb;
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
-static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = {
- /** Initialize DDRC registers **/
- { 0x3d400304, 0x1 },
- { 0x3d400030, 0x1 },
- { 0x3d400000, 0xa1080020 },
- { 0x3d400020, 0x223 },
- { 0x3d400024, 0x3a980 },
- { 0x3d400064, 0x5b0087 },
- { 0x3d4000d0, 0xc00305ba },
- { 0x3d4000d4, 0x940000 },
- { 0x3d4000dc, 0xd4002d },
- { 0x3d4000e0, 0x310000 },
- { 0x3d4000e8, 0x66004d },
- { 0x3d4000ec, 0x16004d },
- { 0x3d400100, 0x191e1920 },
- { 0x3d400104, 0x60630 },
- { 0x3d40010c, 0xb0b000 },
- { 0x3d400110, 0xe04080e },
- { 0x3d400114, 0x2040c0c },
- { 0x3d400118, 0x1010007 },
- { 0x3d40011c, 0x401 },
- { 0x3d400130, 0x20600 },
- { 0x3d400134, 0xc100002 },
- { 0x3d400138, 0x8d },
- { 0x3d400144, 0x96004b },
- { 0x3d400180, 0x2ee0017 },
- { 0x3d400184, 0x2605b8e },
- { 0x3d400188, 0x0 },
- { 0x3d400190, 0x497820a },
- { 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x170a },
- { 0x3d4001a0, 0xe0400018 },
- { 0x3d4001a4, 0xdf00e4 },
- { 0x3d4001a8, 0x80000000 },
- { 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
- { 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x70e1617 },
- { 0x3d400200, 0x1f },
- { 0x3d40020c, 0x0 },
- { 0x3d400210, 0x1f1f },
- { 0x3d400204, 0x80808 },
- { 0x3d400214, 0x7070707 },
- { 0x3d400218, 0xf070707 },
- { 0x3d400250, 0x29001701 },
- { 0x3d400254, 0x2c },
- { 0x3d40025c, 0x4000030 },
- { 0x3d400264, 0x900093e7 },
- { 0x3d40026c, 0x2005574 },
- { 0x3d400400, 0x111 },
- { 0x3d400408, 0x72ff },
- { 0x3d400494, 0x2100e07 },
- { 0x3d400498, 0x620096 },
- { 0x3d40049c, 0x1100e07 },
- { 0x3d4004a0, 0xc8012c },
- { 0x3d402020, 0x21 },
- { 0x3d402024, 0x7d00 },
- { 0x3d402050, 0x20d040 },
- { 0x3d402064, 0xc0012 },
- { 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x310000 },
- { 0x3d4020e8, 0x66004d },
- { 0x3d4020ec, 0x16004d },
- { 0x3d402100, 0xa040305 },
- { 0x3d402104, 0x30407 },
- { 0x3d402108, 0x203060b },
- { 0x3d40210c, 0x505000 },
- { 0x3d402110, 0x2040202 },
- { 0x3d402114, 0x2030202 },
- { 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
- { 0x3d402130, 0x20300 },
- { 0x3d402134, 0xa100002 },
- { 0x3d402138, 0x13 },
- { 0x3d402144, 0x14000a },
- { 0x3d402180, 0x640004 },
- { 0x3d402190, 0x3818200 },
- { 0x3d402194, 0x80303 },
- { 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
- { 0x3d403020, 0x21 },
- { 0x3d403024, 0x1f40 },
- { 0x3d403050, 0x20d040 },
- { 0x3d403064, 0x30005 },
- { 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x310000 },
- { 0x3d4030e8, 0x66004d },
- { 0x3d4030ec, 0x16004d },
- { 0x3d403100, 0xa010102 },
- { 0x3d403104, 0x30404 },
- { 0x3d403108, 0x203060b },
- { 0x3d40310c, 0x505000 },
- { 0x3d403110, 0x2040202 },
- { 0x3d403114, 0x2030202 },
- { 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
- { 0x3d403130, 0x20300 },
- { 0x3d403134, 0xa100002 },
- { 0x3d403138, 0x5 },
- { 0x3d403144, 0x50003 },
- { 0x3d403180, 0x190004 },
- { 0x3d403190, 0x3818200 },
- { 0x3d403194, 0x80303 },
- { 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
- { 0x3d400028, 0x0 },
-};
-
-/* PHY Initialize Configuration */
-static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = {
- { 0x100a0, 0x0 },
- { 0x100a1, 0x1 },
- { 0x100a2, 0x2 },
- { 0x100a3, 0x3 },
- { 0x100a4, 0x4 },
- { 0x100a5, 0x5 },
- { 0x100a6, 0x6 },
- { 0x100a7, 0x7 },
- { 0x110a0, 0x0 },
- { 0x110a1, 0x1 },
- { 0x110a2, 0x3 },
- { 0x110a3, 0x4 },
- { 0x110a4, 0x5 },
- { 0x110a5, 0x2 },
- { 0x110a6, 0x7 },
- { 0x110a7, 0x6 },
- { 0x120a0, 0x0 },
- { 0x120a1, 0x1 },
- { 0x120a2, 0x3 },
- { 0x120a3, 0x2 },
- { 0x120a4, 0x5 },
- { 0x120a5, 0x4 },
- { 0x120a6, 0x7 },
- { 0x120a7, 0x6 },
- { 0x130a0, 0x0 },
- { 0x130a1, 0x1 },
- { 0x130a2, 0x2 },
- { 0x130a3, 0x3 },
- { 0x130a4, 0x4 },
- { 0x130a5, 0x5 },
- { 0x130a6, 0x6 },
- { 0x130a7, 0x7 },
- { 0x1005f, 0x1ff },
- { 0x1015f, 0x1ff },
- { 0x1105f, 0x1ff },
- { 0x1115f, 0x1ff },
- { 0x1205f, 0x1ff },
- { 0x1215f, 0x1ff },
- { 0x1305f, 0x1ff },
- { 0x1315f, 0x1ff },
- { 0x11005f, 0x1ff },
- { 0x11015f, 0x1ff },
- { 0x11105f, 0x1ff },
- { 0x11115f, 0x1ff },
- { 0x11205f, 0x1ff },
- { 0x11215f, 0x1ff },
- { 0x11305f, 0x1ff },
- { 0x11315f, 0x1ff },
- { 0x21005f, 0x1ff },
- { 0x21015f, 0x1ff },
- { 0x21105f, 0x1ff },
- { 0x21115f, 0x1ff },
- { 0x21205f, 0x1ff },
- { 0x21215f, 0x1ff },
- { 0x21305f, 0x1ff },
- { 0x21315f, 0x1ff },
- { 0x55, 0x1ff },
- { 0x1055, 0x1ff },
- { 0x2055, 0x1ff },
- { 0x3055, 0x1ff },
- { 0x4055, 0x1ff },
- { 0x5055, 0x1ff },
- { 0x6055, 0x1ff },
- { 0x7055, 0x1ff },
- { 0x8055, 0x1ff },
- { 0x9055, 0x1ff },
- { 0x200c5, 0x19 },
- { 0x1200c5, 0x7 },
- { 0x2200c5, 0x7 },
- { 0x2002e, 0x2 },
- { 0x12002e, 0x2 },
- { 0x22002e, 0x2 },
- { 0x90204, 0x0 },
- { 0x190204, 0x0 },
- { 0x290204, 0x0 },
- { 0x20024, 0x1ab },
- { 0x2003a, 0x0 },
- { 0x120024, 0x1ab },
- { 0x2003a, 0x0 },
- { 0x220024, 0x1ab },
- { 0x2003a, 0x0 },
- { 0x20056, 0x3 },
- { 0x120056, 0x3 },
- { 0x220056, 0x3 },
- { 0x1004d, 0xe00 },
- { 0x1014d, 0xe00 },
- { 0x1104d, 0xe00 },
- { 0x1114d, 0xe00 },
- { 0x1204d, 0xe00 },
- { 0x1214d, 0xe00 },
- { 0x1304d, 0xe00 },
- { 0x1314d, 0xe00 },
- { 0x11004d, 0xe00 },
- { 0x11014d, 0xe00 },
- { 0x11104d, 0xe00 },
- { 0x11114d, 0xe00 },
- { 0x11204d, 0xe00 },
- { 0x11214d, 0xe00 },
- { 0x11304d, 0xe00 },
- { 0x11314d, 0xe00 },
- { 0x21004d, 0xe00 },
- { 0x21014d, 0xe00 },
- { 0x21104d, 0xe00 },
- { 0x21114d, 0xe00 },
- { 0x21204d, 0xe00 },
- { 0x21214d, 0xe00 },
- { 0x21304d, 0xe00 },
- { 0x21314d, 0xe00 },
- { 0x10049, 0xeba },
- { 0x10149, 0xeba },
- { 0x11049, 0xeba },
- { 0x11149, 0xeba },
- { 0x12049, 0xeba },
- { 0x12149, 0xeba },
- { 0x13049, 0xeba },
- { 0x13149, 0xeba },
- { 0x110049, 0xeba },
- { 0x110149, 0xeba },
- { 0x111049, 0xeba },
- { 0x111149, 0xeba },
- { 0x112049, 0xeba },
- { 0x112149, 0xeba },
- { 0x113049, 0xeba },
- { 0x113149, 0xeba },
- { 0x210049, 0xeba },
- { 0x210149, 0xeba },
- { 0x211049, 0xeba },
- { 0x211149, 0xeba },
- { 0x212049, 0xeba },
- { 0x212149, 0xeba },
- { 0x213049, 0xeba },
- { 0x213149, 0xeba },
- { 0x43, 0x63 },
- { 0x1043, 0x63 },
- { 0x2043, 0x63 },
- { 0x3043, 0x63 },
- { 0x4043, 0x63 },
- { 0x5043, 0x63 },
- { 0x6043, 0x63 },
- { 0x7043, 0x63 },
- { 0x8043, 0x63 },
- { 0x9043, 0x63 },
- { 0x20018, 0x3 },
- { 0x20075, 0x4 },
- { 0x20050, 0x0 },
- { 0x20008, 0x2ee },
- { 0x120008, 0x64 },
- { 0x220008, 0x19 },
- { 0x20088, 0x9 },
- { 0x200b2, 0xdc },
- { 0x10043, 0x5a1 },
- { 0x10143, 0x5a1 },
- { 0x11043, 0x5a1 },
- { 0x11143, 0x5a1 },
- { 0x12043, 0x5a1 },
- { 0x12143, 0x5a1 },
- { 0x13043, 0x5a1 },
- { 0x13143, 0x5a1 },
- { 0x1200b2, 0xdc },
- { 0x110043, 0x5a1 },
- { 0x110143, 0x5a1 },
- { 0x111043, 0x5a1 },
- { 0x111143, 0x5a1 },
- { 0x112043, 0x5a1 },
- { 0x112143, 0x5a1 },
- { 0x113043, 0x5a1 },
- { 0x113143, 0x5a1 },
- { 0x2200b2, 0xdc },
- { 0x210043, 0x5a1 },
- { 0x210143, 0x5a1 },
- { 0x211043, 0x5a1 },
- { 0x211143, 0x5a1 },
- { 0x212043, 0x5a1 },
- { 0x212143, 0x5a1 },
- { 0x213043, 0x5a1 },
- { 0x213143, 0x5a1 },
- { 0x200fa, 0x1 },
- { 0x1200fa, 0x1 },
- { 0x2200fa, 0x1 },
- { 0x20019, 0x1 },
- { 0x120019, 0x1 },
- { 0x220019, 0x1 },
- { 0x200f0, 0x660 },
- { 0x200f1, 0x0 },
- { 0x200f2, 0x4444 },
- { 0x200f3, 0x8888 },
- { 0x200f4, 0x5665 },
- { 0x200f5, 0x0 },
- { 0x200f6, 0x0 },
- { 0x200f7, 0xf000 },
- { 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
- { 0x200c7, 0x21 },
- { 0x200ca, 0x24 },
- { 0x1200c7, 0x21 },
- { 0x1200ca, 0x24 },
- { 0x2200c7, 0x21 },
- { 0x2200ca, 0x24 },
-};
-
-/* ddr phy trained csr */
-static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
- { 0x200b2, 0x0 },
- { 0x1200b2, 0x0 },
- { 0x2200b2, 0x0 },
- { 0x200cb, 0x0 },
- { 0x10043, 0x0 },
- { 0x110043, 0x0 },
- { 0x210043, 0x0 },
- { 0x10143, 0x0 },
- { 0x110143, 0x0 },
- { 0x210143, 0x0 },
- { 0x11043, 0x0 },
- { 0x111043, 0x0 },
- { 0x211043, 0x0 },
- { 0x11143, 0x0 },
- { 0x111143, 0x0 },
- { 0x211143, 0x0 },
- { 0x12043, 0x0 },
- { 0x112043, 0x0 },
- { 0x212043, 0x0 },
- { 0x12143, 0x0 },
- { 0x112143, 0x0 },
- { 0x212143, 0x0 },
- { 0x13043, 0x0 },
- { 0x113043, 0x0 },
- { 0x213043, 0x0 },
- { 0x13143, 0x0 },
- { 0x113143, 0x0 },
- { 0x213143, 0x0 },
- { 0x80, 0x0 },
- { 0x100080, 0x0 },
- { 0x200080, 0x0 },
- { 0x1080, 0x0 },
- { 0x101080, 0x0 },
- { 0x201080, 0x0 },
- { 0x2080, 0x0 },
- { 0x102080, 0x0 },
- { 0x202080, 0x0 },
- { 0x3080, 0x0 },
- { 0x103080, 0x0 },
- { 0x203080, 0x0 },
- { 0x4080, 0x0 },
- { 0x104080, 0x0 },
- { 0x204080, 0x0 },
- { 0x5080, 0x0 },
- { 0x105080, 0x0 },
- { 0x205080, 0x0 },
- { 0x6080, 0x0 },
- { 0x106080, 0x0 },
- { 0x206080, 0x0 },
- { 0x7080, 0x0 },
- { 0x107080, 0x0 },
- { 0x207080, 0x0 },
- { 0x8080, 0x0 },
- { 0x108080, 0x0 },
- { 0x208080, 0x0 },
- { 0x9080, 0x0 },
- { 0x109080, 0x0 },
- { 0x209080, 0x0 },
- { 0x10080, 0x0 },
- { 0x110080, 0x0 },
- { 0x210080, 0x0 },
- { 0x10180, 0x0 },
- { 0x110180, 0x0 },
- { 0x210180, 0x0 },
- { 0x11080, 0x0 },
- { 0x111080, 0x0 },
- { 0x211080, 0x0 },
- { 0x11180, 0x0 },
- { 0x111180, 0x0 },
- { 0x211180, 0x0 },
- { 0x12080, 0x0 },
- { 0x112080, 0x0 },
- { 0x212080, 0x0 },
- { 0x12180, 0x0 },
- { 0x112180, 0x0 },
- { 0x212180, 0x0 },
- { 0x13080, 0x0 },
- { 0x113080, 0x0 },
- { 0x213080, 0x0 },
- { 0x13180, 0x0 },
- { 0x113180, 0x0 },
- { 0x213180, 0x0 },
- { 0x10081, 0x0 },
- { 0x110081, 0x0 },
- { 0x210081, 0x0 },
- { 0x10181, 0x0 },
- { 0x110181, 0x0 },
- { 0x210181, 0x0 },
- { 0x11081, 0x0 },
- { 0x111081, 0x0 },
- { 0x211081, 0x0 },
- { 0x11181, 0x0 },
- { 0x111181, 0x0 },
- { 0x211181, 0x0 },
- { 0x12081, 0x0 },
- { 0x112081, 0x0 },
- { 0x212081, 0x0 },
- { 0x12181, 0x0 },
- { 0x112181, 0x0 },
- { 0x212181, 0x0 },
- { 0x13081, 0x0 },
- { 0x113081, 0x0 },
- { 0x213081, 0x0 },
- { 0x13181, 0x0 },
- { 0x113181, 0x0 },
- { 0x213181, 0x0 },
- { 0x100d0, 0x0 },
- { 0x1100d0, 0x0 },
- { 0x2100d0, 0x0 },
- { 0x101d0, 0x0 },
- { 0x1101d0, 0x0 },
- { 0x2101d0, 0x0 },
- { 0x110d0, 0x0 },
- { 0x1110d0, 0x0 },
- { 0x2110d0, 0x0 },
- { 0x111d0, 0x0 },
- { 0x1111d0, 0x0 },
- { 0x2111d0, 0x0 },
- { 0x120d0, 0x0 },
- { 0x1120d0, 0x0 },
- { 0x2120d0, 0x0 },
- { 0x121d0, 0x0 },
- { 0x1121d0, 0x0 },
- { 0x2121d0, 0x0 },
- { 0x130d0, 0x0 },
- { 0x1130d0, 0x0 },
- { 0x2130d0, 0x0 },
- { 0x131d0, 0x0 },
- { 0x1131d0, 0x0 },
- { 0x2131d0, 0x0 },
- { 0x100d1, 0x0 },
- { 0x1100d1, 0x0 },
- { 0x2100d1, 0x0 },
- { 0x101d1, 0x0 },
- { 0x1101d1, 0x0 },
- { 0x2101d1, 0x0 },
- { 0x110d1, 0x0 },
- { 0x1110d1, 0x0 },
- { 0x2110d1, 0x0 },
- { 0x111d1, 0x0 },
- { 0x1111d1, 0x0 },
- { 0x2111d1, 0x0 },
- { 0x120d1, 0x0 },
- { 0x1120d1, 0x0 },
- { 0x2120d1, 0x0 },
- { 0x121d1, 0x0 },
- { 0x1121d1, 0x0 },
- { 0x2121d1, 0x0 },
- { 0x130d1, 0x0 },
- { 0x1130d1, 0x0 },
- { 0x2130d1, 0x0 },
- { 0x131d1, 0x0 },
- { 0x1131d1, 0x0 },
- { 0x2131d1, 0x0 },
- { 0x10068, 0x0 },
- { 0x10168, 0x0 },
- { 0x10268, 0x0 },
- { 0x10368, 0x0 },
- { 0x10468, 0x0 },
- { 0x10568, 0x0 },
- { 0x10668, 0x0 },
- { 0x10768, 0x0 },
- { 0x10868, 0x0 },
- { 0x11068, 0x0 },
- { 0x11168, 0x0 },
- { 0x11268, 0x0 },
- { 0x11368, 0x0 },
- { 0x11468, 0x0 },
- { 0x11568, 0x0 },
- { 0x11668, 0x0 },
- { 0x11768, 0x0 },
- { 0x11868, 0x0 },
- { 0x12068, 0x0 },
- { 0x12168, 0x0 },
- { 0x12268, 0x0 },
- { 0x12368, 0x0 },
- { 0x12468, 0x0 },
- { 0x12568, 0x0 },
- { 0x12668, 0x0 },
- { 0x12768, 0x0 },
- { 0x12868, 0x0 },
- { 0x13068, 0x0 },
- { 0x13168, 0x0 },
- { 0x13268, 0x0 },
- { 0x13368, 0x0 },
- { 0x13468, 0x0 },
- { 0x13568, 0x0 },
- { 0x13668, 0x0 },
- { 0x13768, 0x0 },
- { 0x13868, 0x0 },
- { 0x10069, 0x0 },
- { 0x10169, 0x0 },
- { 0x10269, 0x0 },
- { 0x10369, 0x0 },
- { 0x10469, 0x0 },
- { 0x10569, 0x0 },
- { 0x10669, 0x0 },
- { 0x10769, 0x0 },
- { 0x10869, 0x0 },
- { 0x11069, 0x0 },
- { 0x11169, 0x0 },
- { 0x11269, 0x0 },
- { 0x11369, 0x0 },
- { 0x11469, 0x0 },
- { 0x11569, 0x0 },
- { 0x11669, 0x0 },
- { 0x11769, 0x0 },
- { 0x11869, 0x0 },
- { 0x12069, 0x0 },
- { 0x12169, 0x0 },
- { 0x12269, 0x0 },
- { 0x12369, 0x0 },
- { 0x12469, 0x0 },
- { 0x12569, 0x0 },
- { 0x12669, 0x0 },
- { 0x12769, 0x0 },
- { 0x12869, 0x0 },
- { 0x13069, 0x0 },
- { 0x13169, 0x0 },
- { 0x13269, 0x0 },
- { 0x13369, 0x0 },
- { 0x13469, 0x0 },
- { 0x13569, 0x0 },
- { 0x13669, 0x0 },
- { 0x13769, 0x0 },
- { 0x13869, 0x0 },
- { 0x1008c, 0x0 },
- { 0x11008c, 0x0 },
- { 0x21008c, 0x0 },
- { 0x1018c, 0x0 },
- { 0x11018c, 0x0 },
- { 0x21018c, 0x0 },
- { 0x1108c, 0x0 },
- { 0x11108c, 0x0 },
- { 0x21108c, 0x0 },
- { 0x1118c, 0x0 },
- { 0x11118c, 0x0 },
- { 0x21118c, 0x0 },
- { 0x1208c, 0x0 },
- { 0x11208c, 0x0 },
- { 0x21208c, 0x0 },
- { 0x1218c, 0x0 },
- { 0x11218c, 0x0 },
- { 0x21218c, 0x0 },
- { 0x1308c, 0x0 },
- { 0x11308c, 0x0 },
- { 0x21308c, 0x0 },
- { 0x1318c, 0x0 },
- { 0x11318c, 0x0 },
- { 0x21318c, 0x0 },
- { 0x1008d, 0x0 },
- { 0x11008d, 0x0 },
- { 0x21008d, 0x0 },
- { 0x1018d, 0x0 },
- { 0x11018d, 0x0 },
- { 0x21018d, 0x0 },
- { 0x1108d, 0x0 },
- { 0x11108d, 0x0 },
- { 0x21108d, 0x0 },
- { 0x1118d, 0x0 },
- { 0x11118d, 0x0 },
- { 0x21118d, 0x0 },
- { 0x1208d, 0x0 },
- { 0x11208d, 0x0 },
- { 0x21208d, 0x0 },
- { 0x1218d, 0x0 },
- { 0x11218d, 0x0 },
- { 0x21218d, 0x0 },
- { 0x1308d, 0x0 },
- { 0x11308d, 0x0 },
- { 0x21308d, 0x0 },
- { 0x1318d, 0x0 },
- { 0x11318d, 0x0 },
- { 0x21318d, 0x0 },
- { 0x100c0, 0x0 },
- { 0x1100c0, 0x0 },
- { 0x2100c0, 0x0 },
- { 0x101c0, 0x0 },
- { 0x1101c0, 0x0 },
- { 0x2101c0, 0x0 },
- { 0x102c0, 0x0 },
- { 0x1102c0, 0x0 },
- { 0x2102c0, 0x0 },
- { 0x103c0, 0x0 },
- { 0x1103c0, 0x0 },
- { 0x2103c0, 0x0 },
- { 0x104c0, 0x0 },
- { 0x1104c0, 0x0 },
- { 0x2104c0, 0x0 },
- { 0x105c0, 0x0 },
- { 0x1105c0, 0x0 },
- { 0x2105c0, 0x0 },
- { 0x106c0, 0x0 },
- { 0x1106c0, 0x0 },
- { 0x2106c0, 0x0 },
- { 0x107c0, 0x0 },
- { 0x1107c0, 0x0 },
- { 0x2107c0, 0x0 },
- { 0x108c0, 0x0 },
- { 0x1108c0, 0x0 },
- { 0x2108c0, 0x0 },
- { 0x110c0, 0x0 },
- { 0x1110c0, 0x0 },
- { 0x2110c0, 0x0 },
- { 0x111c0, 0x0 },
- { 0x1111c0, 0x0 },
- { 0x2111c0, 0x0 },
- { 0x112c0, 0x0 },
- { 0x1112c0, 0x0 },
- { 0x2112c0, 0x0 },
- { 0x113c0, 0x0 },
- { 0x1113c0, 0x0 },
- { 0x2113c0, 0x0 },
- { 0x114c0, 0x0 },
- { 0x1114c0, 0x0 },
- { 0x2114c0, 0x0 },
- { 0x115c0, 0x0 },
- { 0x1115c0, 0x0 },
- { 0x2115c0, 0x0 },
- { 0x116c0, 0x0 },
- { 0x1116c0, 0x0 },
- { 0x2116c0, 0x0 },
- { 0x117c0, 0x0 },
- { 0x1117c0, 0x0 },
- { 0x2117c0, 0x0 },
- { 0x118c0, 0x0 },
- { 0x1118c0, 0x0 },
- { 0x2118c0, 0x0 },
- { 0x120c0, 0x0 },
- { 0x1120c0, 0x0 },
- { 0x2120c0, 0x0 },
- { 0x121c0, 0x0 },
- { 0x1121c0, 0x0 },
- { 0x2121c0, 0x0 },
- { 0x122c0, 0x0 },
- { 0x1122c0, 0x0 },
- { 0x2122c0, 0x0 },
- { 0x123c0, 0x0 },
- { 0x1123c0, 0x0 },
- { 0x2123c0, 0x0 },
- { 0x124c0, 0x0 },
- { 0x1124c0, 0x0 },
- { 0x2124c0, 0x0 },
- { 0x125c0, 0x0 },
- { 0x1125c0, 0x0 },
- { 0x2125c0, 0x0 },
- { 0x126c0, 0x0 },
- { 0x1126c0, 0x0 },
- { 0x2126c0, 0x0 },
- { 0x127c0, 0x0 },
- { 0x1127c0, 0x0 },
- { 0x2127c0, 0x0 },
- { 0x128c0, 0x0 },
- { 0x1128c0, 0x0 },
- { 0x2128c0, 0x0 },
- { 0x130c0, 0x0 },
- { 0x1130c0, 0x0 },
- { 0x2130c0, 0x0 },
- { 0x131c0, 0x0 },
- { 0x1131c0, 0x0 },
- { 0x2131c0, 0x0 },
- { 0x132c0, 0x0 },
- { 0x1132c0, 0x0 },
- { 0x2132c0, 0x0 },
- { 0x133c0, 0x0 },
- { 0x1133c0, 0x0 },
- { 0x2133c0, 0x0 },
- { 0x134c0, 0x0 },
- { 0x1134c0, 0x0 },
- { 0x2134c0, 0x0 },
- { 0x135c0, 0x0 },
- { 0x1135c0, 0x0 },
- { 0x2135c0, 0x0 },
- { 0x136c0, 0x0 },
- { 0x1136c0, 0x0 },
- { 0x2136c0, 0x0 },
- { 0x137c0, 0x0 },
- { 0x1137c0, 0x0 },
- { 0x2137c0, 0x0 },
- { 0x138c0, 0x0 },
- { 0x1138c0, 0x0 },
- { 0x2138c0, 0x0 },
- { 0x100c1, 0x0 },
- { 0x1100c1, 0x0 },
- { 0x2100c1, 0x0 },
- { 0x101c1, 0x0 },
- { 0x1101c1, 0x0 },
- { 0x2101c1, 0x0 },
- { 0x102c1, 0x0 },
- { 0x1102c1, 0x0 },
- { 0x2102c1, 0x0 },
- { 0x103c1, 0x0 },
- { 0x1103c1, 0x0 },
- { 0x2103c1, 0x0 },
- { 0x104c1, 0x0 },
- { 0x1104c1, 0x0 },
- { 0x2104c1, 0x0 },
- { 0x105c1, 0x0 },
- { 0x1105c1, 0x0 },
- { 0x2105c1, 0x0 },
- { 0x106c1, 0x0 },
- { 0x1106c1, 0x0 },
- { 0x2106c1, 0x0 },
- { 0x107c1, 0x0 },
- { 0x1107c1, 0x0 },
- { 0x2107c1, 0x0 },
- { 0x108c1, 0x0 },
- { 0x1108c1, 0x0 },
- { 0x2108c1, 0x0 },
- { 0x110c1, 0x0 },
- { 0x1110c1, 0x0 },
- { 0x2110c1, 0x0 },
- { 0x111c1, 0x0 },
- { 0x1111c1, 0x0 },
- { 0x2111c1, 0x0 },
- { 0x112c1, 0x0 },
- { 0x1112c1, 0x0 },
- { 0x2112c1, 0x0 },
- { 0x113c1, 0x0 },
- { 0x1113c1, 0x0 },
- { 0x2113c1, 0x0 },
- { 0x114c1, 0x0 },
- { 0x1114c1, 0x0 },
- { 0x2114c1, 0x0 },
- { 0x115c1, 0x0 },
- { 0x1115c1, 0x0 },
- { 0x2115c1, 0x0 },
- { 0x116c1, 0x0 },
- { 0x1116c1, 0x0 },
- { 0x2116c1, 0x0 },
- { 0x117c1, 0x0 },
- { 0x1117c1, 0x0 },
- { 0x2117c1, 0x0 },
- { 0x118c1, 0x0 },
- { 0x1118c1, 0x0 },
- { 0x2118c1, 0x0 },
- { 0x120c1, 0x0 },
- { 0x1120c1, 0x0 },
- { 0x2120c1, 0x0 },
- { 0x121c1, 0x0 },
- { 0x1121c1, 0x0 },
- { 0x2121c1, 0x0 },
- { 0x122c1, 0x0 },
- { 0x1122c1, 0x0 },
- { 0x2122c1, 0x0 },
- { 0x123c1, 0x0 },
- { 0x1123c1, 0x0 },
- { 0x2123c1, 0x0 },
- { 0x124c1, 0x0 },
- { 0x1124c1, 0x0 },
- { 0x2124c1, 0x0 },
- { 0x125c1, 0x0 },
- { 0x1125c1, 0x0 },
- { 0x2125c1, 0x0 },
- { 0x126c1, 0x0 },
- { 0x1126c1, 0x0 },
- { 0x2126c1, 0x0 },
- { 0x127c1, 0x0 },
- { 0x1127c1, 0x0 },
- { 0x2127c1, 0x0 },
- { 0x128c1, 0x0 },
- { 0x1128c1, 0x0 },
- { 0x2128c1, 0x0 },
- { 0x130c1, 0x0 },
- { 0x1130c1, 0x0 },
- { 0x2130c1, 0x0 },
- { 0x131c1, 0x0 },
- { 0x1131c1, 0x0 },
- { 0x2131c1, 0x0 },
- { 0x132c1, 0x0 },
- { 0x1132c1, 0x0 },
- { 0x2132c1, 0x0 },
- { 0x133c1, 0x0 },
- { 0x1133c1, 0x0 },
- { 0x2133c1, 0x0 },
- { 0x134c1, 0x0 },
- { 0x1134c1, 0x0 },
- { 0x2134c1, 0x0 },
- { 0x135c1, 0x0 },
- { 0x1135c1, 0x0 },
- { 0x2135c1, 0x0 },
- { 0x136c1, 0x0 },
- { 0x1136c1, 0x0 },
- { 0x2136c1, 0x0 },
- { 0x137c1, 0x0 },
- { 0x1137c1, 0x0 },
- { 0x2137c1, 0x0 },
- { 0x138c1, 0x0 },
- { 0x1138c1, 0x0 },
- { 0x2138c1, 0x0 },
- { 0x10020, 0x0 },
- { 0x110020, 0x0 },
- { 0x210020, 0x0 },
- { 0x11020, 0x0 },
- { 0x111020, 0x0 },
- { 0x211020, 0x0 },
- { 0x12020, 0x0 },
- { 0x112020, 0x0 },
- { 0x212020, 0x0 },
- { 0x13020, 0x0 },
- { 0x113020, 0x0 },
- { 0x213020, 0x0 },
- { 0x20072, 0x0 },
- { 0x20073, 0x0 },
- { 0x20074, 0x0 },
- { 0x100aa, 0x0 },
- { 0x110aa, 0x0 },
- { 0x120aa, 0x0 },
- { 0x130aa, 0x0 },
- { 0x20010, 0x0 },
- { 0x120010, 0x0 },
- { 0x220010, 0x0 },
- { 0x20011, 0x0 },
- { 0x120011, 0x0 },
- { 0x220011, 0x0 },
- { 0x100ae, 0x0 },
- { 0x1100ae, 0x0 },
- { 0x2100ae, 0x0 },
- { 0x100af, 0x0 },
- { 0x1100af, 0x0 },
- { 0x2100af, 0x0 },
- { 0x110ae, 0x0 },
- { 0x1110ae, 0x0 },
- { 0x2110ae, 0x0 },
- { 0x110af, 0x0 },
- { 0x1110af, 0x0 },
- { 0x2110af, 0x0 },
- { 0x120ae, 0x0 },
- { 0x1120ae, 0x0 },
- { 0x2120ae, 0x0 },
- { 0x120af, 0x0 },
- { 0x1120af, 0x0 },
- { 0x2120af, 0x0 },
- { 0x130ae, 0x0 },
- { 0x1130ae, 0x0 },
- { 0x2130ae, 0x0 },
- { 0x130af, 0x0 },
- { 0x1130af, 0x0 },
- { 0x2130af, 0x0 },
- { 0x20020, 0x0 },
- { 0x120020, 0x0 },
- { 0x220020, 0x0 },
- { 0x100a0, 0x0 },
- { 0x100a1, 0x0 },
- { 0x100a2, 0x0 },
- { 0x100a3, 0x0 },
- { 0x100a4, 0x0 },
- { 0x100a5, 0x0 },
- { 0x100a6, 0x0 },
- { 0x100a7, 0x0 },
- { 0x110a0, 0x0 },
- { 0x110a1, 0x0 },
- { 0x110a2, 0x0 },
- { 0x110a3, 0x0 },
- { 0x110a4, 0x0 },
- { 0x110a5, 0x0 },
- { 0x110a6, 0x0 },
- { 0x110a7, 0x0 },
- { 0x120a0, 0x0 },
- { 0x120a1, 0x0 },
- { 0x120a2, 0x0 },
- { 0x120a3, 0x0 },
- { 0x120a4, 0x0 },
- { 0x120a5, 0x0 },
- { 0x120a6, 0x0 },
- { 0x120a7, 0x0 },
- { 0x130a0, 0x0 },
- { 0x130a1, 0x0 },
- { 0x130a2, 0x0 },
- { 0x130a3, 0x0 },
- { 0x130a4, 0x0 },
- { 0x130a5, 0x0 },
- { 0x130a6, 0x0 },
- { 0x130a7, 0x0 },
- { 0x2007c, 0x0 },
- { 0x12007c, 0x0 },
- { 0x22007c, 0x0 },
- { 0x2007d, 0x0 },
- { 0x12007d, 0x0 },
- { 0x22007d, 0x0 },
- { 0x400fd, 0x0 },
- { 0x400c0, 0x0 },
- { 0x90201, 0x0 },
- { 0x190201, 0x0 },
- { 0x290201, 0x0 },
- { 0x90202, 0x0 },
- { 0x190202, 0x0 },
- { 0x290202, 0x0 },
- { 0x90203, 0x0 },
- { 0x190203, 0x0 },
- { 0x290203, 0x0 },
- { 0x90204, 0x0 },
- { 0x190204, 0x0 },
- { 0x290204, 0x0 },
- { 0x90205, 0x0 },
- { 0x190205, 0x0 },
- { 0x290205, 0x0 },
- { 0x90206, 0x0 },
- { 0x190206, 0x0 },
- { 0x290206, 0x0 },
- { 0x90207, 0x0 },
- { 0x190207, 0x0 },
- { 0x290207, 0x0 },
- { 0x90208, 0x0 },
- { 0x190208, 0x0 },
- { 0x290208, 0x0 },
- { 0x10062, 0x0 },
- { 0x10162, 0x0 },
- { 0x10262, 0x0 },
- { 0x10362, 0x0 },
- { 0x10462, 0x0 },
- { 0x10562, 0x0 },
- { 0x10662, 0x0 },
- { 0x10762, 0x0 },
- { 0x10862, 0x0 },
- { 0x11062, 0x0 },
- { 0x11162, 0x0 },
- { 0x11262, 0x0 },
- { 0x11362, 0x0 },
- { 0x11462, 0x0 },
- { 0x11562, 0x0 },
- { 0x11662, 0x0 },
- { 0x11762, 0x0 },
- { 0x11862, 0x0 },
- { 0x12062, 0x0 },
- { 0x12162, 0x0 },
- { 0x12262, 0x0 },
- { 0x12362, 0x0 },
- { 0x12462, 0x0 },
- { 0x12562, 0x0 },
- { 0x12662, 0x0 },
- { 0x12762, 0x0 },
- { 0x12862, 0x0 },
- { 0x13062, 0x0 },
- { 0x13162, 0x0 },
- { 0x13262, 0x0 },
- { 0x13362, 0x0 },
- { 0x13462, 0x0 },
- { 0x13562, 0x0 },
- { 0x13662, 0x0 },
- { 0x13762, 0x0 },
- { 0x13862, 0x0 },
- { 0x20077, 0x0 },
- { 0x10001, 0x0 },
- { 0x11001, 0x0 },
- { 0x12001, 0x0 },
- { 0x13001, 0x0 },
- { 0x10040, 0x0 },
- { 0x10140, 0x0 },
- { 0x10240, 0x0 },
- { 0x10340, 0x0 },
- { 0x10440, 0x0 },
- { 0x10540, 0x0 },
- { 0x10640, 0x0 },
- { 0x10740, 0x0 },
- { 0x10840, 0x0 },
- { 0x10030, 0x0 },
- { 0x10130, 0x0 },
- { 0x10230, 0x0 },
- { 0x10330, 0x0 },
- { 0x10430, 0x0 },
- { 0x10530, 0x0 },
- { 0x10630, 0x0 },
- { 0x10730, 0x0 },
- { 0x10830, 0x0 },
- { 0x11040, 0x0 },
- { 0x11140, 0x0 },
- { 0x11240, 0x0 },
- { 0x11340, 0x0 },
- { 0x11440, 0x0 },
- { 0x11540, 0x0 },
- { 0x11640, 0x0 },
- { 0x11740, 0x0 },
- { 0x11840, 0x0 },
- { 0x11030, 0x0 },
- { 0x11130, 0x0 },
- { 0x11230, 0x0 },
- { 0x11330, 0x0 },
- { 0x11430, 0x0 },
- { 0x11530, 0x0 },
- { 0x11630, 0x0 },
- { 0x11730, 0x0 },
- { 0x11830, 0x0 },
- { 0x12040, 0x0 },
- { 0x12140, 0x0 },
- { 0x12240, 0x0 },
- { 0x12340, 0x0 },
- { 0x12440, 0x0 },
- { 0x12540, 0x0 },
- { 0x12640, 0x0 },
- { 0x12740, 0x0 },
- { 0x12840, 0x0 },
- { 0x12030, 0x0 },
- { 0x12130, 0x0 },
- { 0x12230, 0x0 },
- { 0x12330, 0x0 },
- { 0x12430, 0x0 },
- { 0x12530, 0x0 },
- { 0x12630, 0x0 },
- { 0x12730, 0x0 },
- { 0x12830, 0x0 },
- { 0x13040, 0x0 },
- { 0x13140, 0x0 },
- { 0x13240, 0x0 },
- { 0x13340, 0x0 },
- { 0x13440, 0x0 },
- { 0x13540, 0x0 },
- { 0x13640, 0x0 },
- { 0x13740, 0x0 },
- { 0x13840, 0x0 },
- { 0x13030, 0x0 },
- { 0x13130, 0x0 },
- { 0x13230, 0x0 },
- { 0x13330, 0x0 },
- { 0x13430, 0x0 },
- { 0x13530, 0x0 },
- { 0x13630, 0x0 },
- { 0x13730, 0x0 },
- { 0x13830, 0x0 },
-};
-
-/* P0 message block paremeter for training firmware */
-static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
- { 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
- { 0x54003, 0xbb8 },
- { 0x54004, 0x2 },
- { 0x54005, 0x2228 },
- { 0x54006, 0x11 },
- { 0x54007, 0x0 },
- { 0x54008, 0x131f },
- { 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
- { 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
- { 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
- { 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
- { 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
- { 0x5402b, 0x1000 },
- { 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
- { 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
- { 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
- { 0xd0000, 0x1 },
-};
-
-/* P1 message block paremeter for training firmware */
-static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
- { 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x101 },
- { 0x54003, 0x190 },
- { 0x54004, 0x2 },
- { 0x54005, 0x2228 },
- { 0x54006, 0x11 },
- { 0x54007, 0x0 },
- { 0x54008, 0x121f },
- { 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
- { 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
- { 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
- { 0x54019, 0x84 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
- { 0x5401e, 0x16 },
- { 0x5401f, 0x84 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
- { 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
- { 0x5402b, 0x1000 },
- { 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
- { 0x54032, 0x8400 },
- { 0x54033, 0x3100 },
- { 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
- { 0x54037, 0x1600 },
- { 0x54038, 0x8400 },
- { 0x54039, 0x3100 },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
- { 0xd0000, 0x1 },
-};
-
-/* P2 message block paremeter for training firmware */
-static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
- { 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x102 },
- { 0x54003, 0x64 },
- { 0x54004, 0x2 },
- { 0x54005, 0x2228 },
- { 0x54006, 0x11 },
- { 0x54007, 0x0 },
- { 0x54008, 0x121f },
- { 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
- { 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
- { 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
- { 0x54019, 0x84 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
- { 0x5401e, 0x16 },
- { 0x5401f, 0x84 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
- { 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
- { 0x5402b, 0x1000 },
- { 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
- { 0x54032, 0x8400 },
- { 0x54033, 0x3100 },
- { 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
- { 0x54037, 0x1600 },
- { 0x54038, 0x8400 },
- { 0x54039, 0x3100 },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
- { 0xd0000, 0x1 },
-};
-
-/* P0 2D message block paremeter for training firmware */
-static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
- { 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
- { 0x54003, 0xbb8 },
- { 0x54004, 0x2 },
- { 0x54005, 0x2228 },
- { 0x54006, 0x11 },
- { 0x54007, 0x0 },
- { 0x54008, 0x61 },
- { 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
- { 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x100 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x100 },
- { 0x54010, 0x1f7f },
- { 0x54011, 0x0 },
- { 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
- { 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
- { 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
- { 0x5402b, 0x1000 },
- { 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
- { 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
- { 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
- { 0xd0000, 0x1 },
+/* ddr phy trained csr */
+static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
};
/* DRAM PHY init engine image */
{ 0xd0000, 0x1 },
};
+static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x203 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b0062 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0x68 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0xf0f0707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc000d },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0xe },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30004 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x4 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg_512mb[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x4 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x2 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x2200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
+ { 0x2200ca, 0x24 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg_512mb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg_512mb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg_512mb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg_512mb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg_512mb[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg_512mb,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_512mb),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg_512mb,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_512mb),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg_512mb,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_512mb),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg_512mb,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_512mb),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_512mb = {
+ .ddrc_cfg = ddr_ddrc_cfg_512mb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb),
+ .ddrphy_cfg = ddr_ddrphy_cfg_512mb,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_512mb),
+ .fsp_msg = ddr_dram_fsp_msg_512mb,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_512mb),
+ .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
+
+static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b0087 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0x8d },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0xf070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc0012 },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x13 },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30005 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x5 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
static struct dram_fsp_msg lpddr4_dram_fsp_msg_1gb[] = {
{
/* P0 3000mts 1D */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generated code from MX8M_DDR_tool v3.20 using RPAv20
+ * - 1x Micron MT53E128M32D2DS-046 32bit dual-channel for total of 512MiB
+ * - imx8mm-gw7903
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x203 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b0062 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0x68 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0xf0f0707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc000d },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0xe },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30004 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x4 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x4 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x2 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x2200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
+ { 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x5d },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_512mb = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
switch (size) {
#ifdef CONFIG_IMX8MM
- case 1:
+ case 512:
+ dram_timing = &dram_timing_512mb;
+ break;
+ case 1024:
dram_timing = &dram_timing_1gb;
break;
- case 2:
+ case 2048:
dram_timing = &dram_timing_2gb;
break;
- case 4:
+ case 4096:
dram_timing = &dram_timing_4gb;
break;
default:
- printf("Unknown DDR configuration: %d GiB\n", size);
+ printf("Unknown DDR configuration: %d MiB\n", size);
dram_timing = &dram_timing_1gb;
- size = 1;
+ size = 1024;
#endif
#ifdef CONFIG_IMX8MN
- case 1:
+ case 1024:
dram_timing = &dram_timing_1gb_single_die;
break;
- case 2:
+ case 2048:
if (!strcmp(gsc_get_model(), "GW7902-SP466-A") ||
!strcmp(gsc_get_model(), "GW7902-SP466-B")) {
dram_timing = &dram_timing_2gb_dual_die;
}
break;
default:
- printf("Unknown DDR configuration: %d GiB\n", size);
+ printf("Unknown DDR configuration: %d MiB\n", size);
dram_timing = &dram_timing_2gb_dual_die;
- size = 2;
+ size = 2048;
#endif
}
- printf("DRAM : LPDDR4 %d GiB\n", size);
+ printf("DRAM : LPDDR4 ");
+ if (size > 512)
+ printf("%d GiB\n", size / 1024);
+ else
+ printf("%d MiB\n", size);
ddr_init(dram_timing);
}
return BOOT_DEVICE_NONE;
}
}
+
+const char *spl_board_loader_name(u32 boot_device)
+{
+ switch (boot_device) {
+ /* SDHC2 */
+ case BOOT_DEVICE_MMC1:
+ return "eMMC";
+ /* SDHC3 */
+ case BOOT_DEVICE_MMC2:
+ return "SD card";
+ default:
+ return NULL;
+ }
+}
int board_phys_sdram_size(phys_size_t *size)
{
- const fdt64_t *val;
- int offset;
- int len;
-
- /* get size from dt which SPL updated per EEPROM config */
- offset = fdt_path_offset(gd->fdt_blob, "/memory");
- if (offset < 0)
+ if (!size)
return -EINVAL;
- val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
- if (len < sizeof(*val) * 2)
- return -EINVAL;
- *size = get_unaligned_be64(&val[1]);
+ *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
unsigned short val;
+ ofnode node;
switch (phydev->phy_id) {
case 0x2000a231: /* TI DP83867 GbE PHY */
val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
break;
+ case 0xd565a401: /* MaxLinear GPY111 */
+ puts("GPY111 ");
+ node = phy_get_ofnode(phydev);
+ if (ofnode_valid(node)) {
+ u32 rx_delay, tx_delay;
+
+ rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
+ tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
+ val &= ~((0x7 << 12) | (0x7 << 8));
+ val |= (rx_delay / 500) << 12;
+ val |= (tx_delay / 500) << 8;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, val);
+ }
+ break;
}
if (phydev->drv->config)
int board_init(void)
{
- if (CONFIG_IS_ENABLED(FSL_CAAM))
- sec_init();
-
return 0;
}
--- /dev/null
+if TARGET_IMX8MM_MX8MENLO
+
+config SYS_BOARD
+ default "mx8menlo"
+
+config SYS_VENDOR
+ default "menlo"
+
+config SYS_CONFIG_NAME
+ default "imx8mm-mx8menlo"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_CFG_BLOCK_EXTRA
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+config TDX_HAVE_EEPROM_EXTRA
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+config IMX_CONFIG
+ default "board/toradex/verdin-imx8mm/imximage.cfg"
+
+source "board/toradex/common/Kconfig"
+
+endif
--- /dev/null
+MX8MENLO BOARD
+M: Marek Vasut <marex@denx.de>
+M: Olaf Mandel <o.mandel@menlosystems.com>
+S: Maintained
+F: board/menlo/mx8menlo/
+F: include/configs/imx8mm-mx8menlo.h
+F: configs/imx8mm-mx8menlo_defconfig
--- /dev/null
+#
+# Menlosystems MX8Menlo
+# Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx8menlo.o
+
+obj-y += ../../toradex/verdin-imx8mm/verdin-imx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += ../../toradex/verdin-imx8mm/spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += ../../toradex/verdin-imx8mm/lpddr4_timing.o
+endif
+
+# Common for all Toradex modules
+ifeq ($(CONFIG_SPL_BUILD),y)
+# Necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-$(CONFIG_TDX_CFG_BLOCK) += ../../toradex/common/tdx-cfg-block.o
+obj-y += ../../toradex/common/tdx-common.o
+obj-y += ../../toradex/common/tdx-eeprom.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021-2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <spl.h>
+
+#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+/* Verdin UART_3, Console/Debug UART */
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#define SNVS_BASE_ADDR 0x30370000
+#define SNVS_LPSR 0x4c
+#define SNVS_LPLVDR 0x64
+#define SNVS_LPPGDR_INIT 0x41736166
+
+static void setup_snvs(void)
+{
+ /* Enable SNVS clock */
+ clock_enable(CCGR_SNVS, 1);
+ /* Initialize glitch detect */
+ writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
+ /* Clear interrupt status */
+ writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
+}
+
+void board_early_init(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(1);
+
+ setup_snvs();
+}
# Ilko Iliev <www.ronetix.at>
obj-y += pm9261.o
-obj-$(CONFIG_RED_LED) += led.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Ilko Iliev <www.ronetix.at>
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/gpio.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-
-void coloured_LED_init(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOC);
-
- gpio_direction_output(CONFIG_RED_LED, 1);
- gpio_direction_output(CONFIG_GREEN_LED, 1);
- gpio_direction_output(CONFIG_YELLOW_LED, 1);
-
- gpio_set_value(CONFIG_RED_LED, 0);
- gpio_set_value(CONFIG_GREEN_LED, 1);
- gpio_set_value(CONFIG_YELLOW_LED, 1);
-}
# Ilko Iliev <www.ronetix.at>
obj-y += pm9263.o
-obj-$(CONFIG_AT91_LED) += led.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Ilko Iliev <www.ronetix.at>
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/gpio.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-
-void coloured_LED_init(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOB);
-
- gpio_direction_output(CONFIG_RED_LED, 1);
- gpio_direction_output(CONFIG_GREEN_LED, 1);
-
- gpio_set_value(CONFIG_RED_LED, 0);
- gpio_set_value(CONFIG_GREEN_LED, 1);
-}
gpio_request(AT91_PIN_PD3, "USB1");
gpio_request(AT91_PIN_PB18, "SPICS1");
gpio_request(AT91_PIN_PB3, "SPICS0");
- gpio_request(CONFIG_RED_LED, "red led");
- gpio_request(CONFIG_GREEN_LED, "green led");
+ gpio_request(AT91_PIN_PD31, "red led"); /* this is the user1 led */
+ gpio_request(AT91_PIN_PD0, "green led"); /* this is the user2 led */
+}
+
+void red_led_on(void)
+{
+ gpio_set_value(AT91_PIN_PD31, 1);
+}
+
+void red_led_off(void)
+{
+ gpio_set_value(AT91_PIN_PD31, 0);
+}
+
+void green_led_on(void)
+{
+ gpio_set_value(AT91_PIN_PD0, 0);
+}
+
+void green_led_off(void)
+{
+ gpio_set_value(AT91_PIN_PD0, 1);
}
static void corvus_nand_hw_init(void)
#include <status_led.h>
#include <asm-generic/gpio.h>
+#define RED_LED 110
+#define GREEN_LED 109
+
void coloured_LED_init(void)
{
- gpio_request(CONFIG_RED_LED, "red led");
- gpio_direction_output(CONFIG_RED_LED, 0);
- gpio_request(CONFIG_GREEN_LED, "green led");
- gpio_direction_output(CONFIG_GREEN_LED, 0);
+ gpio_request(RED_LED, "red led");
+ gpio_direction_output(RED_LED, 0);
+ gpio_request(GREEN_LED, "green led");
+ gpio_direction_output(GREEN_LED, 0);
}
void red_led_off(void)
{
- gpio_set_value(CONFIG_RED_LED, 0);
+ gpio_set_value(RED_LED, 0);
}
void green_led_off(void)
{
- gpio_set_value(CONFIG_GREEN_LED, 0);
+ gpio_set_value(GREEN_LED, 0);
}
void red_led_on(void)
{
- gpio_set_value(CONFIG_RED_LED, 1);
+ gpio_set_value(RED_LED, 1);
}
void green_led_on(void)
{
- gpio_set_value(CONFIG_GREEN_LED, 1);
+ gpio_set_value(GREEN_LED, 1);
}
--- /dev/null
+choice
+ prompt "SPL Image Type"
+ default SPL_IMAGE_TYPE_SUNXI_EGON
+
+config SPL_IMAGE_TYPE_SUNXI_EGON
+ bool "eGON (normal)"
+ help
+ Select this option to embed the SPL binary in an eGON.BT0 image,
+ which is compatible with the normal boot ROM (NBROM).
+
+ This is usually the correct option to choose.
+
+config SPL_IMAGE_TYPE_SUNXI_TOC0
+ bool "TOC0 (secure)"
+ help
+ Select this option to embed the SPL binary in a TOC0 image,
+ which is compatible with the secure boot ROM (SBROM).
+
+endchoice
+
+config SPL_IMAGE_TYPE
+ string
+ default "sunxi_egon" if SPL_IMAGE_TYPE_SUNXI_EGON
+ default "sunxi_toc0" if SPL_IMAGE_TYPE_SUNXI_TOC0
#endif
#endif
-#ifdef CONFIG_I2C2_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || \
- defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
- clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
- clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN6I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
- clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
- sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
- clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN50I)
- sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
- sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
- clock_twi_onoff(2, 1);
-#endif
-#endif
-
-#ifdef CONFIG_I2C3_ENABLE
-#if defined(CONFIG_MACH_SUN6I)
- sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
- sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
- clock_twi_onoff(3, 1);
-#elif defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
- sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
- sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
- clock_twi_onoff(3, 1);
-#endif
-#endif
-
-#ifdef CONFIG_I2C4_ENABLE
-#if defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
- sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
- sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
- clock_twi_onoff(4, 1);
-#endif
-#endif
-
#ifdef CONFIG_R_I2C_ENABLE
#ifdef CONFIG_MACH_SUN50I
clock_twi_onoff(5, 1);
i2c_init_board();
#endif
-#ifdef CONFIG_DM_MMC
- /*
- * Temporary workaround for enabling MMC clocks until a sunxi DM
- * pinctrl driver lands.
- */
- mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
-#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
- mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
-#endif
-#endif /* CONFIG_DM_MMC */
-
eth_init_board();
return 0;
#include <common.h>
#include <netdev.h>
#include <miiphy.h>
-#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
void eth_init_board(void)
{
- int pin;
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
CCM_GMAC_CTRL_GPIT_MII);
#endif
-
-#ifndef CONFIG_MACH_SUN6I
- /* Configure pin mux settings for GMAC */
-#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
-#else
- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
-#endif
-#ifdef CONFIG_RGMII
- /* skip unused pins in RGMII mode */
- if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
- continue;
-#endif
- sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
- sunxi_gpio_set_drv(pin, 3);
- }
-#elif defined CONFIG_RGMII
- /* Configure sun6i RGMII mode pin mux settings */
- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
- sunxi_gpio_set_drv(pin, 3);
- }
- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
- sunxi_gpio_set_drv(pin, 3);
- }
- for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
- sunxi_gpio_set_drv(pin, 3);
- }
- for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
- sunxi_gpio_set_drv(pin, 3);
- }
-#elif defined CONFIG_GMII
- /* Configure sun6i GMII mode pin mux settings */
- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
- sunxi_gpio_set_drv(pin, 2);
- }
-#else
- /* Configure sun6i MII mode pin mux settings */
- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
- for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
- for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
- for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
- for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-#endif
}
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
int dram_init(void)
{
gd->ram_size = 2048ul * 1024 * 1024;
return 0;
}
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-}
-
#ifdef CONFIG_FSL_ESDHC_IMX
/* set environment device to boot device when booting from SD */
int board_mmc_get_env_dev(int devno)
}
#endif /* CONFIG_VIDEO_IPUV3 */
-int board_early_init_f(void)
-{
- setup_iomux_uart();
- return 0;
-}
-
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
/*
* Board specific initialization for AM642 EVM
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
* Keerthy <j-keerthy@ti.com>
*
*/
#include <common.h>
#include <asm/io.h>
+#include <dm/uclass.h>
+#include <k3-ddrss.h>
#include <spl.h>
#include <fdt_support.h>
#include <asm/arch/hardware.h>
int dram_init(void)
{
- gd->ram_size = 0x80000000;
+ s32 ret;
- return 0;
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ printf("Error setting up mem size and base. %d\n", ret);
+
+ return ret;
}
int dram_init_banksize(void)
{
- /* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x80000000;
- gd->ram_size = 0x80000000;
+ s32 ret;
- return 0;
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ printf("Error setting up memory banksize. %d\n", ret);
+
+ return ret;
}
#if defined(CONFIG_SPL_LOAD_FIT)
}
#endif
-#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(USB_STORAGE)
+#if defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(USB_STORAGE)
static int fixup_usb_boot(const void *fdt_blob)
{
int ret = 0;
return ret;
}
+#endif
+
+#if defined(CONFIG_K3_AM64_DDRSS)
+static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
+{
+ struct udevice *dev;
+ int ret;
+
+ dram_init_banksize();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret)
+ panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
+
+ ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
+ if (ret)
+ printf("Error fixing up ddr node for ECC use! %d\n", ret);
+}
+#else
+static void fixup_memory_node(struct spl_image_info *spl_image)
+{
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+ int bank;
+ int ret;
+
+ dram_init();
+ dram_init_banksize();
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start[bank] = gd->bd->bi_dram[bank].start;
+ size[bank] = gd->bd->bi_dram[bank].size;
+ }
+
+ /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
+ ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS);
+ if (ret)
+ printf("Error fixing up memory node! %d\n", ret);
+}
+#endif
void spl_perform_fixups(struct spl_image_info *spl_image)
{
+#if defined(CONFIG_K3_AM64_DDRSS)
+ fixup_ddr_driver_for_ecc(spl_image);
+#else
+ fixup_memory_node(spl_image);
+#endif
+
+#if CONFIG_IS_ENABLED(USB_STORAGE)
fixup_usb_boot(spl_image->fdt_addr);
+#endif
}
#endif
env_set("fdt_module", FDT_MODULE_V1_0);
printf("patching fdt_module to " FDT_MODULE_V1_0
" for older V1.0 and V1.1 HW\n");
-#ifndef CONFIG_ENV_IS_NOWHERE
- env_save();
-#endif
}
/* activate USB power enable GPIOs */
if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
env_set("fdt_file", FDT_FILE_V1_0);
printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
-#ifndef CONFIG_ENV_IS_NOWHERE
- env_save();
-#endif
}
}
#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
- /* provide the PHY clock from the i.MX 6 */
+ /*
+ * Use 50MHz anatop loopback REF_CLK2 for ENET2,
+ * clear gpr1[14], set gpr1[18].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
ret = enable_fec_anatop_clock(1, ENET_50MHZ);
if (ret)
return ret;
- /* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */
- clrsetbits_le32(&iomuxc_regs->gpr[1],
- IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
- IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
-
- /* give new Ethernet PHY power save mode circuitry time to settle */
- mdelay(300);
+ enable_enet_clk(1);
return 0;
}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
-}
#endif /* CONFIG_FEC_MXC */
int board_init(void)
} else {
if (is_emmc)
env_set("variant", "-emmc");
+ else
+ env_set("variant", "");
}
#else
if (is_emmc)
env_set("variant", "-emmc");
+ else
+ env_set("variant", "");
#endif
/*
#include <dm/uclass-internal.h>
#include <hang.h>
#include <i2c.h>
-#include <power/bd71837.h>
#include <power/pca9450.h>
#include <power/pmic.h>
#include <spl.h>
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
-int board_early_init_f(void)
+__weak void board_early_init(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+ init_uart_clk(0);
+
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
- return 0;
}
int power_init_board(void)
arch_cpu_init();
- init_uart_clk(0);
-
- board_early_init_f();
+ board_early_init();
timer_init();
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
- PAD_CTL_HYS)
-
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-};
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
#ifdef CONFIG_DM_PMIC
int power_init_board(void)
{
#include <env.h>
#include <fdtdec.h>
#include <init.h>
+#include <image.h>
#include <env_internal.h>
#include <log.h>
#include <malloc.h>
return 0;
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ phys_size_t size;
+ phys_addr_t reg;
+ struct lmb lmb;
+
+ /* found enough not-reserved memory to relocated U-Boot */
+ lmb_init(&lmb);
+ lmb_add(&lmb, gd->ram_base, gd->ram_size);
+ boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
+ size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
+ reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
+
+ if (!reg)
+ reg = gd->ram_top - size;
+
+ return reg + size;
+}
+
void reset_cpu(void)
{
}
psu_mask_write(0xFF5E0238, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
- psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
- psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
- psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
- psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
- psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
- psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
- psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
- psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
- psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
- psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
- psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
- psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
- psu_mask_write(0xFF000034, 0x000000FFU, 0x0000000CU);
- psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000003EU);
- psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
- psu_mask_write(0xFF010034, 0x000000FFU, 0x0000000CU);
- psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000003EU);
- psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
- psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
- psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
- psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
- psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
- psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
- psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
- psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
- psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
- psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
- psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
- psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
- psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
- psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
u8 device;
u8 variants;
} zynqmp_devices[] = {
+ {
+ .id = 0x04688093,
+ .device = 1,
+ .variants = ZYNQMP_VARIANT_EG,
+ },
{
.id = 0x04711093,
.device = 2,
help
This option is used to set the default fdt file to boot OS.
+config SAVE_PREV_BL_FDT_ADDR
+ depends on ARM
+ bool "Saves fdt address, passed by the previous bootloader, to env var"
+ help
+ When u-boot is used as a chain-loaded bootloader (replacing OS kernel),
+ enable this option to save fdt address, passed by the
+ previous bootloader for future use.
+ Address is saved to `prevbl_fdt_addr` environment variable.
+
+ If no fdt was provided by previous bootloader, no env variables
+ will be created.
+
+config SAVE_PREV_BL_INITRAMFS_START_ADDR
+ depends on ARM
+ bool "Saves initramfs address, passed by the previous bootloader, to env var"
+ help
+ When u-boot is used as a chain-loaded bootloader(replacing OS kernel),
+ enable this option to save initramfs address, passed by the
+ previous bootloader for future use.
+ Address is saved to `prevbl_initrd_start_addr` environment variable.
+
+ If no initramfs was provided by previous bootloader, no env variables
+ will be created.
+
endmenu # Booting
#include <mapmem.h>
#include <asm/io.h>
#include <malloc.h>
+#include <memalign.h>
#include <asm/global_data.h>
#ifdef CONFIG_DM_HASH
#include <dm.h>
static int fit_image_check_hash(const void *fit, int noffset, const void *data,
size_t size, char **err_msgp)
{
- uint8_t value[FIT_MAX_HASH_LEN];
+ DEFINE_ALIGN_BUFFER(uint8_t, value, FIT_MAX_HASH_LEN,
+ ARCH_DMA_MINALIGN);
int value_len;
const char *algo;
uint8_t *fit_value;
{ IH_TYPE_MTKIMAGE, "mtk_image", "MediaTek BootROM loadable Image" },
{ IH_TYPE_COPRO, "copro", "Coprocessor Image"},
{ IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image" },
+ { IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image" },
{ -1, "", "", },
};
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <env.h>
#include <image.h>
#include <log.h>
#include <lcd.h>
#include <net.h>
#include <fdt_support.h>
+#include <video.h>
#include <linux/libfdt.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/list.h>
#ifdef CONFIG_DM_RNG
-#include <dm.h>
#include <rng.h>
#endif
/* display BMP if available */
if (cfg->bmp) {
if (get_relfile(ctx, cfg->bmp, image_load_addr, NULL)) {
- if (CONFIG_IS_ENABLED(CMD_CLS))
- run_command("cls", 0);
+#if defined(CONFIG_DM_VIDEO)
+ struct udevice *dev;
+
+ err = uclass_first_device_err(UCLASS_VIDEO, &dev);
+ if (!err)
+ video_clear(dev);
+#endif
bmp_display(image_load_addr,
BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
} else {
Enable editing and History functions for interactive command line
input operations
+config CMDLINE_PS_SUPPORT
+ bool "Enable support for changing the command prompt string at run-time"
+ depends on HUSH_PARSER
+ help
+ Only static string in the prompt is supported so far. The string is
+ obtained from environment variables PS1 and PS2.
+
config AUTO_COMPLETE
bool "Enable auto complete using TAB"
depends on CMDLINE
If enabled, we are allowed to set/print UEFI variables using
"env" command with "-e" option without knowing details.
+config CMD_NVEDIT_INDIRECT
+ bool "env indirect - Sets environment value from another"
+
config CMD_NVEDIT_INFO
bool "env info - print or evaluate environment information"
help
return CMD_RET_SUCCESS;
}
+#ifdef CONFIG_EFI_CAPSULE_ON_DISK
static int do_efi_capsule_on_disk_update(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
return ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
+#endif
/**
* do_efi_capsule_show() - show capsule information
U_BOOT_CMD_MKENT(esrt, CONFIG_SYS_MAXARGS, 1, do_efi_capsule_esrt,
"", ""),
#endif
+#ifdef CONFIG_EFI_CAPSULE_ON_DISK
U_BOOT_CMD_MKENT(disk-update, 0, 0, do_efi_capsule_on_disk_update,
"", ""),
+#endif
U_BOOT_CMD_MKENT(result, CONFIG_SYS_MAXARGS, 1, do_efi_capsule_res,
"", ""),
};
}
#endif
+#if defined(CONFIG_CMD_NVEDIT_INDIRECT)
+static int do_env_indirect(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ char *to = argv[1];
+ char *from = argv[2];
+ char *default_value = NULL;
+ int ret = 0;
+
+ if (argc < 3 || argc > 4) {
+ return CMD_RET_USAGE;
+ }
+
+ if (argc == 4) {
+ default_value = argv[3];
+ }
+
+ if (env_get(from) == NULL && default_value == NULL) {
+ printf("## env indirect: Environment variable for <from> (%s) does not exist.\n", from);
+
+ return CMD_RET_FAILURE;
+ }
+
+ if (env_get(from) == NULL) {
+ ret = env_set(to, default_value);
+ }
+ else {
+ ret = env_set(to, env_get(from));
+ }
+
+ if (ret == 0) {
+ return CMD_RET_SUCCESS;
+ }
+ else {
+ return CMD_RET_FAILURE;
+ }
+}
+#endif
+
#if defined(CONFIG_CMD_NVEDIT_INFO)
/*
* print_env_info - print environment information
#if defined(CONFIG_CMD_IMPORTENV)
U_BOOT_CMD_MKENT(import, 5, 0, do_env_import, "", ""),
#endif
+#if defined(CONFIG_CMD_NVEDIT_INDIRECT)
+ U_BOOT_CMD_MKENT(indirect, 3, 0, do_env_indirect, "", ""),
+#endif
#if defined(CONFIG_CMD_NVEDIT_INFO)
U_BOOT_CMD_MKENT(info, 3, 0, do_env_info, "", ""),
#endif
#if defined(CONFIG_CMD_IMPORTENV)
"env import [-d] [-t [-r] | -b | -c] addr [size] [var ...] - import environment\n"
#endif
+#if defined(CONFIG_CMD_NVEDIT_INDIRECT)
+ "env indirect <to> <from> [default] - sets <to> to the value of <from>, using [default] when unset\n"
+#endif
#if defined(CONFIG_CMD_NVEDIT_INFO)
"env info - display environment information\n"
"env info [-d] [-p] [-q] - evaluate environment information\n"
{ SBI_EXT_RFENCE, "RFENCE Extension" },
{ SBI_EXT_HSM, "Hart State Management Extension" },
{ SBI_EXT_SRST, "System Reset Extension" },
+ { SBI_EXT_PMU, "Performance Monitoring Unit Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
{
int i, impl_id;
long ret;
+ long mvendorid, marchid, mimpid;
ret = sbi_get_spec_version();
if (ret >= 0)
if (i == ARRAY_SIZE(implementations))
printf("Unknown implementation ID %ld", ret);
}
- printf("\nExtensions:\n");
+ printf("\nMachine:\n");
+ ret = sbi_get_mvendorid(&mvendorid);
+ if (!ret)
+ printf(" Vendor ID %lx\n", mvendorid);
+ ret = sbi_get_marchid(&marchid);
+ if (!ret)
+ printf(" Architecture ID %lx\n", marchid);
+ ret = sbi_get_mimpid(&mimpid);
+ if (!ret)
+ printf(" Implementation ID %lx\n", mimpid);
+ printf("Extensions:\n");
for (i = 0; i < ARRAY_SIZE(extensions); ++i) {
ret = sbi_probe_extension(extensions[i].id);
if (ret > 0)
struct mtd_info *mtd;
int err = 0;
+ if (ubi && ubi->mtd && !strcmp(ubi->mtd->name, part_name)) {
+ printf("UBI partition '%s' already selected\n", part_name);
+ return 0;
+ }
+
ubi_detach();
mtd_probe_devices();
char *const argv[])
{
if (argc == 2 && !strcmp(argv[1], "scan")) {
- /* make sure all virtio devices are enumerated */
- virtio_init();
+ /*
+ * make sure all virtio devices are enumerated.
+ * Do the same as virtio_init(), but also call
+ * device_probe() for children (i.e. virtio devices)
+ */
+ struct udevice *bus, *child;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_VIRTIO, &bus);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ while (bus) {
+ device_foreach_child_probe(child, bus)
+ ;
+ ret = uclass_next_device(&bus);
+ if (ret)
+ break;
+ }
return CMD_RET_SUCCESS;
}
s = env_get("bootdelay");
bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
+ /*
+ * Does it really make sense that the devicetree overrides the user
+ * setting? It is possibly helpful for security since the device tree
+ * may be signed whereas the environment is often loaded from storage.
+ */
if (IS_ENABLED(CONFIG_OF_CONTROL))
bootdelay = ofnode_conf_read_int("bootdelay", bootdelay);
env_set_hex("fdtcontroladdr",
(unsigned long)map_to_sysmem(gd->fdt_blob));
+ #if (CONFIG_IS_ENABLED(SAVE_PREV_BL_INITRAMFS_START_ADDR) || \
+ CONFIG_IS_ENABLED(SAVE_PREV_BL_FDT_ADDR))
+ save_prev_bl_data();
+ #endif
+
/* Initialize from environment */
image_load_addr = env_get_ulong("loadaddr", 16, image_load_addr);
#include <malloc.h>
#include <asm/io.h>
+#include <valgrind/memcheck.h>
#ifdef DEBUG
#if __STD_C
unlink(victim, bck, fwd);
set_inuse_bit_at_offset(victim, victim_size);
check_malloced_chunk(victim, nb);
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
}
unlink(victim, bck, fwd);
set_inuse_bit_at_offset(victim, victim_size);
check_malloced_chunk(victim, nb);
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
}
}
set_head(remainder, remainder_size | PREV_INUSE);
set_foot(remainder, remainder_size);
check_malloced_chunk(victim, nb);
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
}
{
set_inuse_bit_at_offset(victim, victim_size);
check_malloced_chunk(victim, nb);
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
}
set_head(remainder, remainder_size | PREV_INUSE);
set_foot(remainder, remainder_size);
check_malloced_chunk(victim, nb);
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
}
set_inuse_bit_at_offset(victim, victim_size);
unlink(victim, bck, fwd);
check_malloced_chunk(victim, nb);
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
}
/* If big and would otherwise need to extend, try to use mmap instead */
if ((unsigned long)nb >= (unsigned long)mmap_threshold &&
(victim = mmap_chunk(nb)))
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
#endif
top = chunk_at_offset(victim, nb);
set_head(top, remainder_size | PREV_INUSE);
check_malloced_chunk(victim, nb);
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
}
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* free() is a no-op - all the memory will be freed on relocation */
- if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
+ if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
+ VALGRIND_FREELIKE_BLOCK(mem, SIZE_SZ);
return;
+ }
#endif
if (mem == NULL) /* free(0) has no effect */
sz = hd & ~PREV_INUSE;
next = chunk_at_offset(p, sz);
nextsz = chunksize(next);
+ VALGRIND_FREELIKE_BLOCK(mem, SIZE_SZ);
if (next == top) /* merge with top */
{
top = chunk_at_offset(oldp, nb);
set_head(top, (newsize - nb) | PREV_INUSE);
set_head_size(oldp, nb);
+ VALGRIND_RESIZEINPLACE_BLOCK(chunk2mem(oldp), 0, bytes, SIZE_SZ);
+ VALGRIND_MAKE_MEM_DEFINED(chunk2mem(oldp), bytes);
return chunk2mem(oldp);
}
}
{
unlink(next, bck, fwd);
newsize += nextsize;
+ VALGRIND_RESIZEINPLACE_BLOCK(chunk2mem(oldp), 0, bytes, SIZE_SZ);
+ VALGRIND_MAKE_MEM_DEFINED(chunk2mem(oldp), bytes);
goto split;
}
}
newp = prev;
newsize += prevsize + nextsize;
newmem = chunk2mem(newp);
+ VALGRIND_MALLOCLIKE_BLOCK(newmem, bytes, SIZE_SZ, false);
MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ);
top = chunk_at_offset(newp, nb);
set_head(top, (newsize - nb) | PREV_INUSE);
set_head_size(newp, nb);
+ VALGRIND_FREELIKE_BLOCK(oldmem, SIZE_SZ);
return newmem;
}
}
newp = prev;
newsize += nextsize + prevsize;
newmem = chunk2mem(newp);
+ VALGRIND_MALLOCLIKE_BLOCK(newmem, bytes, SIZE_SZ, false);
MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ);
goto split;
}
newp = prev;
newsize += prevsize;
newmem = chunk2mem(newp);
+ VALGRIND_MALLOCLIKE_BLOCK(newmem, bytes, SIZE_SZ, false);
MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ);
goto split;
}
MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ);
fREe(oldmem);
return newmem;
+ } else {
+ VALGRIND_RESIZEINPLACE_BLOCK(oldmem, 0, bytes, SIZE_SZ);
+ VALGRIND_MAKE_MEM_DEFINED(oldmem, bytes);
}
set_head_size(newp, nb);
set_head(remainder, remainder_size | PREV_INUSE);
set_inuse_bit_at_offset(remainder, remainder_size);
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(remainder), remainder_size, SIZE_SZ,
+ false);
fREe(chunk2mem(remainder)); /* let free() deal with it */
}
else
set_head_size(p, leadsize);
fREe(chunk2mem(p));
p = newp;
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(p), bytes, SIZE_SZ, false);
assert (newsize >= nb && (((unsigned long)(chunk2mem(p))) % alignment) == 0);
}
remainder = chunk_at_offset(p, nb);
set_head(remainder, remainder_size | PREV_INUSE);
set_head_size(p, nb);
+ VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(remainder), remainder_size, SIZE_SZ,
+ false);
fREe(chunk2mem(remainder));
}
#endif
MALLOC_ZERO(mem, csz - SIZE_SZ);
+ VALGRIND_MAKE_MEM_DEFINED(mem, sz);
return mem;
}
}
#include <mapmem.h>
#include <asm/global_data.h>
#include <asm/io.h>
+#include <valgrind/valgrind.h>
DECLARE_GLOBAL_DATA_PTR;
return ptr;
log_debug("%lx\n", (ulong)ptr);
+ VALGRIND_MALLOCLIKE_BLOCK(ptr, bytes, 0, false);
return ptr;
}
if (!ptr)
return ptr;
log_debug("aligned to %lx\n", (ulong)ptr);
+ VALGRIND_MALLOCLIKE_BLOCK(ptr, bytes, 0, false);
return ptr;
}
return ptr;
}
+
+#if IS_ENABLED(CONFIG_VALGRIND)
+void free_simple(void *ptr)
+{
+ VALGRIND_FREELIKE_BLOCK(ptr, 0);
+}
+#endif
#endif
void malloc_simple_info(void)
default 1
help
Partition on the MMC to load U-Boot from when the MMC is being
- used in fs mode
+ used in fs mode.
+ Use -1 as a special value to use the first bootable partition.
config SPL_MMC_TINY
bool "Tiny MMC framework in SPL"
config TPL_TEXT_BASE
hex "Base address for the .text section of the TPL stage"
+ default 0
help
The base address for the .text section of the TPL stage.
#include <serial.h>
#include <spl.h>
#include <asm/global_data.h>
+#include <asm-generic/gpio.h>
#include <asm/u-boot.h>
#include <nand.h>
#include <fat.h>
}
}
+ if (CONFIG_IS_ENABLED(GPIO_HOG))
+ gpio_hog_probe_all();
+
#if CONFIG_IS_ENABLED(BOARD_INIT)
spl_board_init();
#endif
{
int err = -ENOSYS;
+ __maybe_unused int partition = CONFIG_SYS_MMCSD_FS_BOOT_PARTITION;
+
+#if CONFIG_SYS_MMCSD_FS_BOOT_PARTITION == -1
+ {
+ struct disk_partition info;
+ debug("Checking for the first MBR bootable partition\n");
+ for (int type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) {
+ err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
+ if (err)
+ continue;
+ debug("Partition %d is of type %d and bootable=%d\n", type_part, info.sys_ind, info.bootable);
+ if (info.bootable != 0) {
+ debug("Partition %d is bootable, using it\n", type_part);
+ partition = type_part;
+ break;
+ }
+ }
+ printf("Using first bootable partition: %d\n", partition);
+ if (partition == CONFIG_SYS_MMCSD_FS_BOOT_PARTITION) {
+ return -ENOSYS;
+ }
+ }
+#endif
+
#ifdef CONFIG_SPL_FS_FAT
if (!spl_start_uboot()) {
err = spl_load_image_fat_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
- CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
+ partition);
if (!err)
return err;
}
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
err = spl_load_image_fat(spl_image, bootdev, mmc_get_blk_desc(mmc),
- CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
+ partition,
filename);
if (!err)
return err;
#ifdef CONFIG_SPL_FS_EXT4
if (!spl_start_uboot()) {
err = spl_load_image_ext_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
- CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
+ partition);
if (!err)
return err;
}
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
err = spl_load_image_ext(spl_image, bootdev, mmc_get_blk_desc(mmc),
- CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
+ partition,
filename);
if (!err)
return err;
}
#endif
-u32 __weak spl_mmc_boot_mode(const u32 boot_device)
+u32 __weak spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
}
}
- boot_mode = spl_mmc_boot_mode(bootdev->boot_device);
+ boot_mode = spl_mmc_boot_mode(mmc, bootdev->boot_device);
err = -EINVAL;
switch (boot_mode) {
case MMCSD_MODE_EMMCBOOT:
if (ret)
return ret;
}
+
+ ret = blk_probe_or_unbind(dev);
+ if (ret)
+ return ret;
}
#else
/* We don't have space to even probe if we hit the maximum */
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
CONFIG_SYS_LOAD_ADDR=0xcc000000
+CONFIG_ENV_ADDR=0xF4080000
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0xCFF80000
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_PING=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xF4080000
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
CONFIG_SYS_LOAD_ADDR=0xd4000000
+CONFIG_ENV_ADDR=0xE2880000
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0xD7F80000
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_PING=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xE2880000
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE"
+CONFIG_SYS_LOAD_ADDR=0x40010000
+CONFIG_ENV_ADDR=0x2000
CONFIG_TARGET_M5208EVBE=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x2000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32"
+CONFIG_SYS_LOAD_ADDR=0x20000
+CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y
CONFIG_NORFLASH_PS32BIT=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="u-boot.bin"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5235EVB"
+CONFIG_SYS_LOAD_ADDR=0x20000
+CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="u-boot.bin"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
+CONFIG_SYS_LOAD_ADDR=0x200000
+CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5249EVB=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_SYS_MONITOR_BASE=0xFFE00400
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xFF804000
CONFIG_TARGET_M5253DEMO=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SYS_MONITOR_BASE=0xFF800400
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
-CONFIG_ENV_ADDR=0xFF804000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_IDE_MAXBUS=1
CONFIG_SYS_ATA_STRIDE=4
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5272C3"
+CONFIG_SYS_LOAD_ADDR=0x20000
+CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5272C3=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MII_INIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5275EVB"
+CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5275EVB=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTCOMMAND=y
CONFIG_MII_INIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5282EVB"
+CONFIG_SYS_LOAD_ADDR=0x20000
+CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5282EVB=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MII_INIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x8000
CONFIG_DEFAULT_DEVICE_TREE="M53017EVB"
+CONFIG_SYS_LOAD_ADDR=0x40010000
+CONFIG_ENV_ADDR=0x40000
CONFIG_TARGET_M53017EVB=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE"
+CONFIG_SYS_LOAD_ADDR=0x40010000
+CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
-CONFIG_ENV_ADDR=0x4000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE"
+CONFIG_SYS_LOAD_ADDR=0x40010000
+CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
-CONFIG_ENV_ADDR=0x4000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="M5373EVB"
+CONFIG_SYS_LOAD_ADDR=0x40010000
+CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5373EVB=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
-CONFIG_ENV_ADDR=0x4000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="mcr3000"
+CONFIG_SYS_LOAD_ADDR=0x200000
+CONFIG_ENV_ADDR=0x4004000
CONFIG_MPC8xx=y
CONFIG_TARGET_MCR3000=y
CONFIG_8xx_GCLK_FREQ=132000000
CONFIG_SYS_SCCR=0x00C20000
CONFIG_SYS_SCCR_MASK=0x60000000
CONFIG_SYS_DER=0x2002000F
-CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_MONITOR_BASE=0x04000000
CONFIG_BOOTDELAY=5
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x4004000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
CONFIG_SYS_CLK_FREQ=66666667
+CONFIG_ENV_ADDR=0xFE080000
# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xE0000000
CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
+CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
# CONFIG_CMD_HASH is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFF60000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="8548cds/uImage.uboot"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xE0000000
CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
+CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
# CONFIG_CMD_HASH is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFF60000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="8548cds/uImage.uboot"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xE0000000
CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
+CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
# CONFIG_CMD_HASH is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFF60000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="8548cds/uImage.uboot"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x20000
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifkw"
CONFIG_IDENT_STRING="\nSBx81LIFKW"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x1000000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat"
CONFIG_IDENT_STRING="\nSBx81LIFXCAT"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x1000000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_ENV_ADDR=0xFFE20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_FIT=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y
+CONFIG_LMB_MAX_REGIONS=64
CONFIG_FIT=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y
+CONFIG_LMB_MAX_REGIONS=64
CONFIG_FIT=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y
+CONFIG_LMB_MAX_REGIONS=64
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae3xx"
CONFIG_SYS_CLK_FREQ=39062500
-CONFIG_TARGET_ADP_AE3XX=y
CONFIG_SYS_LOAD_ADDR=0x300000
+CONFIG_TARGET_ADP_AE3XX=y
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_BOOTDELAY=3
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="ag101p"
CONFIG_SYS_CLK_FREQ=39062500
-CONFIG_TARGET_ADP_AG101P=y
CONFIG_SYS_LOAD_ADDR=0x300000
+CONFIG_ENV_ADDR=0x80140000
+CONFIG_TARGET_ADP_AG101P=y
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x80000000
CONFIG_BOOTDELAY=3
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x80140000
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOOTP_SERVERIP=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_BOOTDELAY=3
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_BOOTDELAY=3
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_ENV_ADDR=0xC0000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xC0000
CONFIG_VERSION_VARIABLE=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_TPS65217=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_TPS65217=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_TPS65217=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_NOP_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_PMIC_TPS65217=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_TPS65217=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_TPS65217=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_PMIC_TPS65217=y
CONFIG_LZO=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_PMIC_TPS65217=y
CONFIG_LZO=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_PMIC_TPS65217=y
CONFIG_LZO=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_PMIC_TPS65217=y
CONFIG_LZO=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PMIC_TPS65217=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM642=y
CONFIG_TARGET_AM642_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SPL_MISC=y
+CONFIG_ESM_K3=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="amcore"
+CONFIG_SYS_LOAD_ADDR=0x20000
+CONFIG_ENV_ADDR=0xFFC1F000
CONFIG_TARGET_AMCORE=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTCOMMAND=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_DIAG=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFC1F000
# CONFIG_NET is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ARCH_ATH79=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000
-CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ARCH_ATH79=y
CONFIG_TARGET_AP143=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000
-CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ARCH_ATH79=y
CONFIG_TARGET_AP152=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000
-CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis"
CONFIG_TARGET_APALIS_IMX8=y
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_LOG=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis"
CONFIG_TARGET_APALIS_IMX8X=y
+CONFIG_SYS_LOAD_ADDR=0x89000000
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x89000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=1
CONFIG_DM_I2C=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_I2C=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_TARGET_ARMADILLO_800EVA=y
CONFIG_SYS_CLK_FREQ=50000000
CONFIG_SYS_LOAD_ADDR=0x44000000
+CONFIG_ENV_ADDR=0x40000
CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_BOOTDELAY=3
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_CMD_SLEEP is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
CONFIG_VERSION_VARIABLE=y
# CONFIG_MMC is not set
CONFIG_BITBANGMII=y
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for ARNDALE"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x43e00000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_USE_PREBOOT=y
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_SECT_SIZE=0x8000
CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l"
+CONFIG_SYS_LOAD_ADDR=0x20000
+CONFIG_ENV_ADDR=0x1FF8000
CONFIG_TARGET_ASTRO_MCF5373L=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_JFFS2=y
-CONFIG_ENV_ADDR=0x1FF8000
# CONFIG_NET is not set
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_ENV_ADDR=0x107E0000
+CONFIG_DEBUG_UART=y
CONFIG_SYS_MONITOR_BASE=0x10000000
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x107E0000
CONFIG_ENV_ADDR_REDUND=0x107D0000
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_ENV_ADDR=0x107E0000
+CONFIG_DEBUG_UART=y
CONFIG_SYS_MONITOR_BASE=0x10000000
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x107E0000
CONFIG_ENV_ADDR_REDUND=0x107D0000
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ZYNQ_MAC_IN_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_ENV_OFFSET_REDUND=0x180000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_DEBUG_UART_BASE=0xe0022000
CONFIG_DEBUG_UART_CLOCK=33333333
CONFIG_SYS_CLK_FREQ=750000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS3,115200n8"
CONFIG_DEBUG_UART_BASE=0xe0022000
CONFIG_DEBUG_UART_CLOCK=33333333
CONFIG_SYS_CLK_FREQ=100000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS3,115200n8"
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING="bpi-m5"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
+CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_TARGET_BCM963158=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_RSASSA_PSS=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm96753ref"
CONFIG_ARMV7_LPAE=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_TARGET_BCM96753REF=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_CIPHER=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm968360bg"
+CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_TARGET_BCM968360BG=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6838=y
CONFIG_MIPS_CACHE_SETUP=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref"
+CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_TARGET_BCM968580XREF=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" beelink"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" beelink"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" beelink"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x220000
CONFIG_TARGET_BK4R1=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
-CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=520192
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_R8A7792=y
CONFIG_TARGET_BLANCHE=y
CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_ENV_ADDR=0x40000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x40000
CONFIG_VERSION_VARIABLE=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_SYS_LOAD_ADDR=0x88000000
+CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_TARGET_BOSTON=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_SYS_LOAD_ADDR=0x88000000
+CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_SYS_LOAD_ADDR=0x88000000
+CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS32_R6=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_SYS_LOAD_ADDR=0x88000000
+CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS32_R6=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
+CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R2=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
+CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS64_R2=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
+CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R6=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
+CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS64_R6=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x50000
-# CONFIG_EXPERT is not set
CONFIG_SYS_LOAD_ADDR=0x80000000
+# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_TPS65217=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
-# CONFIG_EXPERT is not set
CONFIG_SYS_LOAD_ADDR=0x80000000
+# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_TPS65217=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_ENV_OFFSET_REDUND=0x30000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-# CONFIG_EXPERT is not set
CONFIG_SYS_LOAD_ADDR=0x80000000
+# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPI_BOOT=y
CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_TPS65217=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_CMD_BMODE is not set
-# CONFIG_EXPERT is not set
CONFIG_SYS_LOAD_ADDR=0x10700000
+# CONFIG_EXPERT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_ENV_OFFSET_REDUND=0x30000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-# CONFIG_EXPERT is not set
CONFIG_SYS_LOAD_ADDR=0x80000000
+# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PMIC_TPS65217=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x50000
-# CONFIG_EXPERT is not set
CONFIG_SYS_LOAD_ADDR=0x80000000
+# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PMIC_TPS65217=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96"
CONFIG_MACH_S900=y
CONFIG_IDENT_STRING="\nBubblegum-96"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x7ffc0
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyOWL5,115200n8"
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PMIC_TPS65217=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL_TEXT_BASE=0xf4000a00
CONFIG_SPL_MMC=y
CONFIG_SPL=y
-CONFIG_ARCH_JZ47XX=y
CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ARCH_JZ47XX=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k"
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="cobra5272"
+CONFIG_SYS_LOAD_ADDR=0x20000
+CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_COBRA5272=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_PING=y
-CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
CONFIG_TARGET_COLIBRI_IMX8X=y
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0xa0000000
+CONFIG_ENV_ADDR=0x80000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=262144
CONFIG_TIMESTAMP=y
CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_USE_BOOTARGS=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x80000
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
CONFIG_TARGET_COLIBRI_VF=y
+CONFIG_SYS_LOAD_ADDR=0x80008000
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x80008000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=520192
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;"
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6318=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6328=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6348=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM63268=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6368=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_REMAKE_ELF=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_REMAKE_ELF=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_REMAKE_ELF=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s-bit"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s-bit"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s-bit"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7"
CONFIG_MACH_S700=y
CONFIG_IDENT_STRING="\ncubieboard7"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x7ffc0
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyOWL3,115200n8"
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-d2net"
CONFIG_IDENT_STRING=" D2 v2"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x70000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DM=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_LTO=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
-CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_ENV_ADDR=0x60100000
+CONFIG_LTO=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60100000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_LTO=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=200000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_SYS_MEMTEST_START=0x00800000
CONFIG_SYS_MEMTEST_END=0x00ffffff
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_IDENT_STRING=" ##v01.06"
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_REMAKE_ELF=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325"
CONFIG_IDENT_STRING="\nD-Link DNS-325"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test -n ${bootenv} && usb start; then if run loadbootenv; then echo Loaded environment ${bootenv} from usb;run importbootenv;fi;if test -n ${bootenvcmd}; then echo Running bootenvcmd ...;run bootenvcmd;fi;fi;run setnandbootenv subbootcmd;"
CONFIG_ENV_OFFSET=0x80000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dockstar"
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:root; ubifsload 0x800000 ${kernel}; ubifsload 0x1100000 ${initrd}; bootm 0x800000 0x1100000"
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_ENV_OFFSET=0x0
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
+CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80080000
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
CONFIG_TARGET_DRAGONBOARD820C=y
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80080000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyMSM0,115200n8"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug"
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x100000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv ethact ethernet-controller@72000; ${x_bootcmd_ethernet}; setenv ethact ethernet-controller@76000; ${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_ENV_ADDR=0x100000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_ENV_OFFSET=0x3D0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x3D0000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv ethact egiga0; ${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_ENV_ADDR=0x3D0000
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DM=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 ip=off initrd=0x8000040,8M root=/dev/md0 rw syno_hw_version=DS414r1 ihd_num=4 netif_num=2 flash_size=8 SataLedSpecial=1 HddHotplug=1"
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="phytium-durian"
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_SYS_PCI_64BIT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_EA_LPC3250DEVKITV2=y
CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80100000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=1048575
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282"
+CONFIG_SYS_LOAD_ADDR=0x20000
+CONFIG_ENV_ADDR=0xFF040000
CONFIG_TARGET_EB_CPU5282=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_MONITOR_BASE=0xFF000400
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_CMD_MII=y
CONFIG_MII_INIT=y
CONFIG_CMD_DATE=y
-CONFIG_ENV_ADDR=0xFF040000
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal"
+CONFIG_SYS_LOAD_ADDR=0x20000
+CONFIG_ENV_ADDR=0xFF040000
CONFIG_TARGET_EB_CPU5282=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_MONITOR_BASE=0xF0000418
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_CMD_MII=y
CONFIG_MII_INIT=y
CONFIG_CMD_DATE=y
-CONFIG_ENV_ADDR=0xFF040000
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_ENV_OFFSET=0x300000
CONFIG_DEFAULT_DEVICE_TREE="edison"
CONFIG_ENV_OFFSET_REDUND=0x600000
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_VENDOR_INTEL=y
CONFIG_TARGET_EDISON=y
CONFIG_SMP=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SYS_MONITOR_BASE=0x01101000
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL=y
CONFIG_IDENT_STRING=" EDMiniV2"
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0xFFF84000
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF84000
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_IDE_MAXBUS=1
# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x62000000
+CONFIG_DEBUG_UART=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DRAM_ODT_EN is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_SPL_SIZE_LIMIT=0x10000
CONFIG_SPL=y
# CONFIG_ARMV7_NONSEC is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_LOAD_ADDR=0x83000000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x60800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb"
# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x60800800
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R_ADDR=0x60600000
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x61800800
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_SIZE_LIMIT=0x4b000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
CONFIG_DEBUG_UART_BASE=0xFF0C0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TARGET_EVB_RK3568=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x62000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTCOMMAND="sf probe;sf read 0x62000000 0x140800 0x500000;dcache off;go 0x62000000"
CONFIG_DEFAULT_FDT_FILE="rv1108-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_TARGET_ROCK960_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0xB0000
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y
CONFIG_MIPS_CACHE_SETUP=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=655360
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_DEVICE_TREE="gazerbeam"
CONFIG_IDENT_STRING=" gazerbeam 0.01"
CONFIG_SYS_CLK_FREQ=33333333
+CONFIG_ENV_ADDR=0xFE080000
CONFIG_MPC83xx=y
CONFIG_TARGET_GAZERBEAM=y
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
CONFIG_OF_LIVE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFE080000
CONFIG_ENV_ADDR_REDUND=0xFE090000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_TARGET_GEEKBOX=y
CONFIG_DEBUG_UART_BASE=0xFF690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_IDENT_STRING=" ##v01.07"
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_REMAKE_ELF=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_ENV_OFFSET=0xC0000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet"
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:root; ubifsload 0x800000 ${kernel}; bootm 0x800000"
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_ENV_ADDR=0xC0000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xC0000
CONFIG_VERSION_VARIABLE=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus"
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=917504
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000"
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0xe00000
CONFIG_PHYLIB=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_DEVICE_TREE="highbank"
CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0xFFF88000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_MISC_INIT_R=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_NVRAM=y
-CONFIG_ENV_ADDR=0xFFF88000
CONFIG_SCSI_AHCI=y
CONFIG_BOOTCOUNT_LIMIT=y
# CONFIG_MMC is not set
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_HIHOPE_RZG2=y
# CONFIG_SPL is not set
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960"
CONFIG_IDENT_STRING="\nHikey960"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw"
CONFIG_ENV_OFFSET=0x0
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
CONFIG_IDENT_STRING="hikey"
+CONFIG_SYS_LOAD_ADDR=0x80000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80000
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw"
CONFIG_DEBUG_UART_BASE=0xf0005000
CONFIG_DEBUG_UART_CLOCK=33333333
CONFIG_SYS_CLK_FREQ=500000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_DEBUG_UART=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_DEBUG_UART_BASE=0xf0005000
CONFIG_DEBUG_UART_CLOCK=33333333
CONFIG_SYS_CLK_FREQ=500000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_DEBUG_UART=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6358=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ib62x0"
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000"
CONFIG_ENV_OFFSET=0x80000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-iconnect"
CONFIG_IDENT_STRING=" Iomega iConnect"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part rootfs; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; bootm 0x800000"
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_BOOTCOUNT_ADDR=0x9
CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xFFFC0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_IDS8313=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:7m(dum),768k(BOOT-BIN),128k(BOOT-ENV),128k(BOOT-REDENV);e1000000.flash:-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFFFC0000
CONFIG_ENV_ADDR_REDUND=0xFFFE0000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="ids8313/uImage"
CONFIG_SYS_MALLOC_F_LEN=0x600
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
+CONFIG_SYS_LOAD_ADDR=0x80500000
CONFIG_TARGET_XILFPGA=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
-CONFIG_SYS_LOAD_ADDR=0x80500000
CONFIG_TIMESTAMP=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_SYS_LOAD_ADDR=0x42000000
+CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_FIT=y
CONFIG_TIMESTAMP=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x90000
-CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_SYS_LOAD_ADDR=0x42000000
+CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_KEYBOARD=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x4400
+CONFIG_ENV_OFFSET=0x200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_OFFSET_REDUND=0x204000
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_KEYBOARD=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-mx8menlo"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_MX8MENLO=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_ENV_OFFSET_REDUND=0xFFFFDE00
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="mmc partconf 0 distro_bootpart && load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-mx8menlo.dtb"
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="Verdin iMX8MM # "
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
-CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_LTO=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0xFFFC0000
+CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_LOAD_ADDR=0x60000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run dmo_preboot"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=16384
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_BKOPS_ENABLE=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_SMC=y
+CONFIG_HASH_VERIFY=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
+CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+# CONFIG_INPUT is not set
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_SPL_DM_REGULATOR_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x0
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xff8000
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902"
+CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-bsh-smm-s2"
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_BSH_SMM_S2=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="> "
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_DEFAULT="gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),1m(nanddtb),8m(nandtee),-(nandrootfs)"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x40480000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_NXP_TJA11XX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_IMX_WATCHDOG=y
+# CONFIG_FAT_WRITE is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-bsh-smm-s2pro"
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_BSH_SMM_S2PRO=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2pro.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="> "
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x40480000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_NXP_TJA11XX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_IMX_WATCHDOG=y
+# CONFIG_FAT_WRITE is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xff8000
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_REMAKE_ELF=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_SPL=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_REMAKE_ELF=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x400000
CONFIG_IMX_CONFIG=""
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_SYS_LOAD_ADDR=0x80480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80480000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=0
CONFIG_ARM=y
CONFIG_ARCH_IMXRT=y
CONFIG_SYS_TEXT_BASE=0x80002000
-CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x20209000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_ARCH_IMXRT=y
CONFIG_SYS_TEXT_BASE=0x80002000
-CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x20209000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2"
CONFIG_IDENT_STRING=" IS v2"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x70000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_SYS_LOAD_ADDR=0x7fc0
+CONFIG_ENV_ADDR=0x24F00000
CONFIG_SYS_MONITOR_BASE=0x27F40000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_ADDR=0x24F00000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
# CONFIG_MMC is not set
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_SYS_LOAD_ADDR=0x7fc0
+CONFIG_ENV_ADDR=0x24F00000
CONFIG_SYS_MONITOR_BASE=0x27F40000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_ADDR=0x24F00000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
# CONFIG_MMC is not set
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_SYS_LOAD_ADDR=0x7fc0
+CONFIG_ENV_ADDR=0x24F00000
CONFIG_SYS_MONITOR_BASE=0x27F40000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_ADDR=0x24F00000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
# CONFIG_MMC is not set
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_SYS_LOAD_ADDR=0x7fc0
+CONFIG_ENV_ADDR=0x24F00000
CONFIG_SYS_MONITOR_BASE=0x27F40000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_ADDR=0x24F00000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
# CONFIG_MMC is not set
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="iot_devkit"
CONFIG_SYS_CLK_FREQ=16000000
-CONFIG_LOCALVERSION="-iotdk-1.0"
CONFIG_SYS_LOAD_ADDR=0x30000000
+CONFIG_LOCALVERSION="-iotdk-1.0"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_PROMPT="IoTDK# "
# CONFIG_CMD_BOOTD is not set
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" jethubj100"
+CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" jethubj80"
+CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=384000000
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=384000000
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim2"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3l"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3l"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3l"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood 128M16"
-CONFIG_KM_KIRKWOOD_128M16=y
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_KM_KIRKWOOD_128M16=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
-CONFIG_KM_KIRKWOOD=y
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_KM_KIRKWOOD=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood PCI"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_KM_FPGA_CONFIG=y
CONFIG_KM_KIRKWOOD_PCI=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
CONFIG_SYS_CLK_FREQ=66666666
+CONFIG_ENV_ADDR=0xebf20000
CONFIG_MPC85xx=y
CONFIG_TARGET_KMCENT2=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xebf20000
CONFIG_ENV_ADDR_REDUND=0xebf00000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="fm1-mac5"
CONFIG_DEFAULT_DEVICE_TREE="kmcoge5ne"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMCOGE5NE=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_KM_DEF_NETDEV="eth1"
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_CMD_UBIFS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="UEC0"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0xD0000
CONFIG_IDENT_STRING="\nHitachi Power Grids COGE5UN"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
CONFIG_KM_ENV_IS_IN_SPI_NOR=y
CONFIG_KM_PIGGY4_88E6352=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_DEFAULT_DEVICE_TREE="kmeter1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMETER1=y
CONFIG_LCRR_EADC_2=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_KM_DEF_NETDEV="eth2"
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_CMD_UBIFS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="UEC0"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0xD0000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_KM_FPGA_CONFIG=y
CONFIG_KM_ENV_IS_IN_SPI_NOR=y
CONFIG_KM_PIGGY4_88E6352=y
CONFIG_KM_NUSA=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_DEFAULT_DEVICE_TREE="kmopti2"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMOPTI2=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_CMD_UBIFS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="UEC0"
CONFIG_DEFAULT_DEVICE_TREE="kmsupm5"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMSUPX5=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_CMD_UBIFS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="UEC0"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0xD0000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_KM_FPGA_CONFIG=y
CONFIG_KM_FPGA_FORCE_CONFIG=y
CONFIG_KM_FPGA_NO_RESET=y
CONFIG_KM_ENV_IS_IN_SPI_NOR=y
CONFIG_KM_SUSE2=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_DEFAULT_DEVICE_TREE="kmtegr1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xF0100000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMTEGR1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_KM_DEF_NETDEV="eth1"
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_CMD_UBIFS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF0100000
CONFIG_ENV_ADDR_REDUND=0xF0120000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="UEC0"
CONFIG_DEFAULT_DEVICE_TREE="kmtepr2"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMTEPR2=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_CMD_UBIFS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="UEC0"
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_ENV_ADDR=0xC0000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xC0000
CONFIG_VERSION_VARIABLE=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x4000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x42000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_USB_DWC3=y
CONFIG_EFI_SET_TIME=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
-CONFIG_EFI_CAPSULE_ON_DISK=y
-CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_SET_TIME=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
-CONFIG_EFI_CAPSULE_ON_DISK=y
-CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x60800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
CONFIG_ARCH_RMOBILE_BOARD_STRING="KMC KZM-A9-GT"
CONFIG_TARGET_KZM9G=y
CONFIG_SYS_LOAD_ADDR=0x43000000
+CONFIG_ENV_ADDR=0x40000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/null console=ttySC4,115200"
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
CONFIG_VERSION_VARIABLE=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_ENV_ADDR=0xC0000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xC0000
CONFIG_VERSION_VARIABLE=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-ac"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-cc"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-cc-v2"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-s905d-pc"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-s912-pc"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y
CONFIG_BOARD_LINKIT_SMART_7688=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=524288
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x401D0000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x401D0000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FSL_QIXIS=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FSL_QIXIS=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_ENV_ADDR=0x40300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
# CONFIG_DEEP_SLEEP is not set
-CONFIG_AHCI=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_AHCI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
-CONFIG_AHCI=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_AHCI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg"
CONFIG_SD_BOOT=y
CONFIG_SD_BOOT_QSPI=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_RAMBOOT_PBL=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SD_BOOT_QSPI=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="ethernet@2d10000"
CONFIG_DM=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="ethernet@2d10000"
CONFIG_DM=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_USB=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart"
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x40300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x60500000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_BUS=0
-CONFIG_ENV_ADDR=0x60500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x60500000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_ADDR=0x60500000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x40500000
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nand_bootcmd; env exists secureboot && esbc_halt;;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x40300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x60500000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_BUS=0
-CONFIG_ENV_ADDR=0x60500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_ENV_ADDR=0x40300000
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_BOOTCOMMAND="run distro_bootcmd;run sd_bootcmd; env exists secureboot && esbc_halt;"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x40500000
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x80300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x80300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_ENV_ADDR=0x20300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_ENV_ADDR=0x20300000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_NXP_ESBC=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x80300000
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x80300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
CONFIG_AHCI=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x80300000
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x80300000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x580500000
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x580500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_ENV_ADDR=0x20300000
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x580500000
CONFIG_AHCI=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x580500000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2"
CONFIG_IDENT_STRING=" LS-CHLv2"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_API=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl"
CONFIG_IDENT_STRING=" LS-XHL"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_API=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_REMAKE_ELF=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC17@rgmii-id"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_EMC2305=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_EMC2305=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_REMAKE_ELF=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_EMC2305=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_REMAKE_ELF=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC1@xgmii"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_REMAKE_ELF=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC17@rgmii-id"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_REMAKE_ELF=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="DPMAC17@rgmii-id"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
+CONFIG_SYS_LOAD_ADDR=0xffffffff81000000
+CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
CONFIG_TARGET_MALTA=y
CONFIG_CPU_MIPS64_R2=y
-CONFIG_SYS_LOAD_ADDR=0xffffffff81000000
# CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
CONFIG_SYS_IDE_MAXBUS=1
CONFIG_SYS_ATA_DATA_OFFSET=0
CONFIG_SYS_ATA_REG_OFFSET=0
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
+CONFIG_SYS_LOAD_ADDR=0xffffffff81000000
+CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS64_R2=y
-CONFIG_SYS_LOAD_ADDR=0xffffffff81000000
# CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
CONFIG_SYS_IDE_MAXBUS=1
CONFIG_SYS_ATA_DATA_OFFSET=0
CONFIG_SYS_ATA_REG_OFFSET=0
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
-CONFIG_TARGET_MALTA=y
CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ENV_ADDR=0xBE3E0000
+CONFIG_TARGET_MALTA=y
# CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBE3E0000
CONFIG_SYS_IDE_MAXBUS=1
CONFIG_SYS_ATA_DATA_OFFSET=0
CONFIG_SYS_ATA_REG_OFFSET=0
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
+CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ENV_ADDR=0xBE3E0000
CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_SYS_LOAD_ADDR=0x81000000
# CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBE3E0000
CONFIG_SYS_IDE_MAXBUS=1
CONFIG_SYS_ATA_DATA_OFFSET=0
CONFIG_SYS_ATA_REG_OFFSET=0
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
+CONFIG_ENV_ADDR=0x8040000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x8040000
CONFIG_ENV_ADDR_REDUND=0x8060000
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
+CONFIG_ENV_ADDR=0x8040000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x8040000
CONFIG_ENV_ADDR_REDUND=0x8060000
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_MICROCHIP_ICICLE=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
CONFIG_DEBUG_UART_BASE=0x70100000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_ENV_OFFSET_REDUND=0x140000
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y
CONFIG_SOC_JR2=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fc00000
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BASE=0x70100000
CONFIG_DEBUG_UART_CLOCK=208333333
CONFIG_ENV_OFFSET_REDUND=0x140000
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y
CONFIG_SOC_LUTON=y
CONFIG_DDRTYPE_MT47H128M8HQ=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x87c00000
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BASE=0x70100000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_ENV_OFFSET_REDUND=0x140000
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fc00000
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="serval_pcb106"
CONFIG_ENV_OFFSET_REDUND=0x140000
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y
CONFIG_SOC_SERVAL=y
CONFIG_DDRTYPE_H5TQ1G63BFA=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x87c00000
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="servalt_pcb116"
CONFIG_ENV_OFFSET_REDUND=0x140000
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y
CONFIG_SOC_SERVALT=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fc00000
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xb0000c00
CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_ARCH_MTMIPS=y
CONFIG_BOARD_MT7620_MT7530_RFB=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y
-CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xb0000c00
CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_ARCH_MTMIPS=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y
-CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=25000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x4007ff28
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_DEFAULT_FDT_FILE="mt7622-rfb"
CONFIG_LOGLEVEL=7
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc"
CONFIG_TARGET_MT7623=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x84000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2"
CONFIG_TARGET_MT7623=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x84000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y
CONFIG_BOARD_MT7628_RFB=y
CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
CONFIG_MIPS_BOOT_FDT=y
-CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x40800000
+CONFIG_SYS_LOAD_ADDR=0x42007f1c
CONFIG_SPL_PAYLOAD="u-boot-lzma.img"
CONFIG_BUILD_TARGET="u-boot-mtk.bin"
CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin"
-CONFIG_SYS_LOAD_ADDR=0x42007f1c
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=26000000
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x4c000000
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DEBUG_UART_BASE=0x11005000
CONFIG_DEBUG_UART_CLOCK=26000000
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x4c000000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_DEFAULT_DEVICE_TREE="cn9130-crb-A"
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_SYS_LOAD_ADDR=0x6000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x6000000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db"
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEFAULT_DEVICE_TREE="cn9130-db-A"
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin"
CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_SYS_LOAD_ADDR=0x6000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x6000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-mcbin"
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-puzzle-m801"
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
CONFIG_AUTOBOOT_STOP_STR="s"
CONFIG_TARGET_MX23_OLINUXINO=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x42000000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loaduimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_DEFAULT_DEVICE_TREE="imx51-babbage"
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_LOAD_ADDR=0x92000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=785408
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_USE_PREBOOT=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020"
# CONFIG_CMD_BMODE is not set
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x70010000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_CMD_MMC=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-qsb"
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_LOAD_ADDR=0x72000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=785408
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto"
CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd"
CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_LDO_ENABLED_MODE=y
CONFIG_TARGET_MX7ULP_COM=y
CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=785408
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi"
CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
+CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x9e000000
-CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
+CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x9e000000
-CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" nanopi-k2"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_ENV_OFFSET=0xA0000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220"
CONFIG_IDENT_STRING="\nNAS 220"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_USE_PREBOOT=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-net2big"
CONFIG_IDENT_STRING=" 2Big v2"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x70000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DM=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6362=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite"
CONFIG_IDENT_STRING=" NS v2 Lite"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x70000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DM=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max"
CONFIG_IDENT_STRING=" NS Max v2"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x70000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DM=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini"
CONFIG_IDENT_STRING=" NS v2 Mini"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x70000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DM=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2"
CONFIG_IDENT_STRING=" NS v2"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x70000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DM=y
CONFIG_SYS_MALLOC_LEN=0xc0000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NOKIA_RX51=y
+CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_OPTIMIZE_INLINING=y
CONFIG_LTO=y
# CONFIG_SYS_MALLOC_F is not set
-CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_FIT is not set
CONFIG_BOOTDELAY=30
CONFIG_AUTOBOOT_KEYED=y
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_DEBUG_UART_CLOCK=408000000
CONFIG_TEGRA124=y
CONFIG_TARGET_NYAN_BIG=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x82408000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEBUG_UART_BASE=0x8001180000000800
CONFIG_DEBUG_UART_CLOCK=1200000000
+CONFIG_SYS_LOAD_ADDR=0xffffffff80100000
+CONFIG_ENV_ADDR=0x800000001FBFE000
CONFIG_ARCH_OCTEON=y
# CONFIG_MIPS_CACHE_SETUP is not set
# CONFIG_MIPS_CACHE_DISABLE is not set
CONFIG_MIPS_RELOCATION_TABLE_SIZE=0xc000
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_FIXUP=y
-CONFIG_SYS_LOAD_ADDR=0xffffffff80100000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x800000001FBFE000
CONFIG_CLK=y
# CONFIG_INPUT is not set
CONFIG_MISC=y
CONFIG_ENV_SECT_SIZE=0x100
CONFIG_DEBUG_UART_BASE=0x8001180000000800
CONFIG_DEBUG_UART_CLOCK=800000000
+CONFIG_SYS_LOAD_ADDR=0xffffffff80100000
+CONFIG_ENV_ADDR=0xe000
CONFIG_ARCH_OCTEON=y
CONFIG_TARGET_OCTEON_NIC23=y
# CONFIG_MIPS_CACHE_SETUP is not set
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
-CONFIG_SYS_LOAD_ADDR=0xffffffff80100000
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xe000
CONFIG_SATA=y
CONFIG_AHCI_MVEBU=y
CONFIG_CLK=y
CONFIG_DEFAULT_DEVICE_TREE="octeontx"
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x04000000
CONFIG_SYS_MEMTEST_END=0x040f0000
-CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_DEVICE_TREE="octeontx"
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_DEVICE_TREE="octeontx"
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x2800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x2800000
CONFIG_SYS_MEMTEST_END=0x28f0000
-CONFIG_SYS_LOAD_ADDR=0x2800000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_DEVICE_TREE="octeontx"
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x2800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SYS_LOAD_ADDR=0x2800000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-c2"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-c4/hc4"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-hc4"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-n2/n2-plus"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_ENV_OFFSET=0x310000
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2"
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x140000
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MALLOC_LEN=0x10000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
+CONFIG_SYS_LOAD_ADDR=0x87000000
CONFIG_TARGET_OPENPITON_RISCV64=y
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
-CONFIG_SYS_LOAD_ADDR=0x87000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x87000000
CONFIG_SPL_PAYLOAD=""
CONFIG_TARGET_OPENPITON_RISCV64=y
CONFIG_NR_CPUS=32
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
-CONFIG_SYS_LOAD_ADDR=0x87000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_ENV_OFFSET=0x80000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-base"
CONFIG_IDENT_STRING="\nOpenRD-Base"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=524288
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
CONFIG_ENV_OFFSET=0x80000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client"
CONFIG_IDENT_STRING="\nOpenRD-Client"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=524288
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
CONFIG_ENV_OFFSET=0x80000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate"
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=524288
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for ORIGEN"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x43e00000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run uenvcmd;fi;if run loadbootscript; then run bootscript; fi; fi;load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p200"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p201"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p212"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEFAULT_DEVICE_TREE="vf610-pcm052"
CONFIG_ENV_OFFSET_REDUND=0xC0000
CONFIG_TARGET_PCM052=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
-CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=520192
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run bootcmd_nand"
CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for Peach-Pi"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x23e00000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for Peach-Pit"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x23e00000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_SYS_CLK_FREQ=66666666
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60060000
CONFIG_AHCI=y
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x60060000
CONFIG_ENV_ADDR_REDUND=0x60040000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="ethernet@2d90000"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60220000
CONFIG_AHCI=y
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x60220000
CONFIG_ENV_ADDR_REDUND=0x60200000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="ethernet@2d90000"
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_SYS_CLK_FREQ=66666666
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60060000
CONFIG_AHCI=y
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x60060000
CONFIG_ENV_ADDR_REDUND=0x60040000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="ethernet@2d90000"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_ENV_ADDR=0x60220000
CONFIG_AHCI=y
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x60220000
CONFIG_ENV_ADDR_REDUND=0x60200000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="ethernet@2d90000"
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
+CONFIG_SYS_LOAD_ADDR=0x88500000
CONFIG_MACH_PIC32=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x88080000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x88500000
CONFIG_TIMESTAMP=y
CONFIG_BOOTDELAY=5
CONFIG_BOOTCOMMAND="run distro_bootcmd || run legacy_bootcmd"
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb"
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
CONFIG_SPL_I2C=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
CONFIG_SPL_I2C=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_SPL_I2C=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
CONFIG_SPL_I2C=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715776
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
CONFIG_SPL_I2C=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SUN8I_EMAC=y
CONFIG_SPI=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SUN8I_EMAC=y
CONFIG_PHY_SUN50I_USB3=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_ENV_ADDR=0x10040000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock4 rootfstype=jffs2 fbcon=rotate:3 "
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x10040000
# CONFIG_NET is not set
CONFIG_DM=y
CONFIG_BLK=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_ENV_ADDR=0x10040000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock4 rootfstype=jffs2 fbcon=rotate:3 "
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x10040000
CONFIG_DM=y
CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02"
CONFIG_IDENT_STRING="\nPogo E02"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs $(bootargs_console); run bootcmd_usb; bootm 0x00800000 0x01100000"
CONFIG_SYS_MALLOC_LEN=0x101000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo"
+CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_SYS_PCI_64BIT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ENV_OFFSET=0x1F0000
CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar"
CONFIG_IDENT_STRING="poplar"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="poplar# "
CONFIG_CMD_MMC=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_ENV_ADDR=0xC0000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xC0000
CONFIG_VERSION_VARIABLE=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
# CONFIG_OF_BOARD_FIXUP is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};"
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_DEFAULT_DEVICE_TREE="qemu-arm64"
CONFIG_DEBUG_UART_BASE=0x9000000
CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_SYS_LOAD_ADDR=0x40200000
+CONFIG_ENV_ADDR=0x4000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40200000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x4000000
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_DFU_TFTP=y
CONFIG_DEBUG_UART_BASE=0x9000000
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_ARMV7_LPAE=y
+CONFIG_SYS_LOAD_ADDR=0x40200000
+CONFIG_ENV_ADDR=0x4000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40200000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x4000000
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_DFU_TFTP=y
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="sh7751-r2dplus"
CONFIG_SYS_CLK_FREQ=60000000
-CONFIG_TARGET_R2DPLUS=y
CONFIG_SYS_LOAD_ADDR=0x8e000000
+CONFIG_ENV_ADDR=0xA0040000
+CONFIG_TARGET_R2DPLUS=y
CONFIG_SYS_MONITOR_BASE=0xA0000000
CONFIG_BOOTDELAY=-1
CONFIG_USE_BOOTARGS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xA0040000
CONFIG_DM=y
CONFIG_SYS_IDE_MAXBUS=1
CONFIG_SYS_IDE_MAXDEVICE=1
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EAGLE=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_CONDOR=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EBISU=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_DRAAK=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_SYS_CLK_FREQ=16666666
# CONFIG_PSCI_RESET is not set
CONFIG_ARMV8_PSCI=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" radxa-zero"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_LTO=y
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_ULCB=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_SPL_STACK_R_ADDR=0xc00000
CONFIG_DEBUG_UART_BASE=0xFF0C0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb"
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_ROCK960_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x60800800
+CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_TARGET_RPI_4_32B=y
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_TARGET_RPI_4=y
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_TARGET_RPI_ARM64=y
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_BEACON_RZG2M=y
# CONFIG_SPL is not set
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" s400"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_ROOT_DEV=1
CONFIG_BOOT_PART=1
CONFIG_ROOT_PART=2
+CONFIG_SYS_LOAD_ADDR=0x71080000
CONFIG_SYS_MEMTEST_START=0x71000000
CONFIG_SYS_MEMTEST_END=0xb0000000
-CONFIG_SYS_LOAD_ADDR=0x71080000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
CONFIG_TARGET_S5P_GONI=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x34000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock8 rootfstype=ext4 ${console} ${meminfo} ${mtdparts}"
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x44800000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
CONFIG_BOOTCOMMAND="run mmcboot"
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6338=y
CONFIG_MIPS_CACHE_SETUP=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_ENV_OFFSET_REDUND=0x100000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_SPI_BOOT=y
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf801c000
CONFIG_DEBUG_UART_CLOCK=83000000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x20000000
CONFIG_SYS_MEMTEST_END=0x40000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BOOT_GET_KBD=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf801c000
CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BASE=0xf801c000
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_ENV_OFFSET_REDUND=0x100000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ENV_OFFSET_REDUND=0x100000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_ENV_OFFSET_REDUND=0x100000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xe1824200
CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x62000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x70000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x62000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xe1824200
CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x62000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x70000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x62000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_TEXT_BASE=0
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_SANDBOX64=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_TEXT_BASE=0
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_PRE_CON_BUF_ADDR=0xf0000
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_RSASSA_PSS=y
CONFIG_FIT_CIPHER=y
CONFIG_SYS_TEXT_BASE=0
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_TEXT_BASE=0x200000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_SANDBOX_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_TEXT_BASE=0x200000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_SANDBOX_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" sei510"
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run load_logo"
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" sei610"
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run load_logo"
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser"
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6358=y
CONFIG_BOARD_SFR_NB4_SER=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_SHEEP=y
CONFIG_DEBUG_UART_BASE=0xFF1b0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-sheep.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ENV_OFFSET=0x80000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug"
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=524288
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_SIFIVE_UNLEASHED=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
CONFIG_USE_PREBOOT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SYS_PCI_64BIT=y
CONFIG_AHCI=y
CONFIG_TARGET_SIFIVE_UNMATCHED=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
CONFIG_USE_PREBOOT=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SILINUX_EK874=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_ENV_ADDR=0xC0000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xC0000
CONFIG_VERSION_VARIABLE=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_TARGET_SIPEED_MAIX=y
CONFIG_ARCH_RV64I=y
-CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_STACK_SIZE=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run k210_bootcmd"
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_TARGET_SIPEED_MAIX=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
-CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_STACK_SIZE=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run k210_bootcmd"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDK5250"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x43e00000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDK5420"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x23e00000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_IDENT_STRING=" for SMDKC100"
CONFIG_SYS_CLK_FREQ=12000000
CONFIG_SYS_LOAD_ADDR=0x30000000
+CONFIG_ENV_ADDR=0x40000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock5 ubi.mtd=4 rootfstype=cramfs console=ttySAC0,115200n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)"
CONFIG_MTDPARTS_DEFAULT="mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_ONENAND=y
-CONFIG_ENV_ADDR=0x40000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_SMC911X=y
CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDKC210/V310"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x43e00000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="fatload mmc 0 40007000 uImage; bootm 40007000"
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="SMDKV310 # "
CONFIG_DEBUG_UART_BASE=0x12c30000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_IDENT_STRING=" for snow"
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x02000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x3fe00000
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x02000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_ENV_OFFSET_REDUND=0x120000
# CONFIG_SPL_LIBDISK_SUPPORT is not set
# CONFIG_SPL_SPI is not set
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp"
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_BOOT_RETRY=y
CONFIG_BOOT_RETRY_TIME=45
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x02000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x3fe00000
CONFIG_OPTIMIZE_INLINING=y
CONFIG_SPL_OPTIMIZE_INLINING=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_CMDLINE_PS_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xE0000000
CONFIG_SYS_TEXT_BASE=0xfff80000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="socrates"
+CONFIG_ENV_ADDR=0xFFF40000
# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFFF40000
CONFIG_ENV_ADDR_REDUND=0xFFF20000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="TSEC0"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SUN8I_EMAC=y
CONFIG_SPI=y
CONFIG_DEBUG_UART_BASE=0x12c30000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_IDENT_STRING=" for spring"
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_SNAPDRAGON=y
-CONFIG_SYS_TEXT_BASE=0x80000000
-CONFIG_SYS_MALLOC_LEN=0x81f000
CONFIG_DEFAULT_DEVICE_TREE="starqltechn"
CONFIG_TARGET_STARQLTECHN=y
CONFIG_IDENT_STRING="\nSamsung S9 SM-G9600"
CONFIG_SYS_LOAD_ADDR=0x80000000
-CONFIG_USE_PREBOOT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_BMP=y
# CONFIG_NET is not set
# CONFIG_DM_STDIO is not set
CONFIG_CLK=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PM8916=y
-CONFIG_MSM_GENI_SERIAL=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_SPMI_MSM=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_SIMPLE=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_LMB_MAX_REGIONS=64
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260"
CONFIG_IDENT_STRING="STMicroelectronics STiH410-B2260"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x90400000
+CONFIG_ENV_ADDR=0x8040000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
CONFIG_CMD_TIMER=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x8040000
# CONFIG_NET is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval"
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_EVALUATION=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x400000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F469_DISCOVERY=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x400000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x8008000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x8008000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco"
CONFIG_STM32H7=y
CONFIG_TARGET_STM32H743_DISCO=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0xd0400000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval"
CONFIG_STM32H7=y
CONFIG_TARGET_STM32H743_EVAL=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0xd0400000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
CONFIG_STM32H7=y
CONFIG_TARGET_STM32H750_ART_PI=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0xc1800000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_TARGET_ICORE_STM32MP1=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
# CONFIG_ARMV7_VIRT is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_TARGET_ICORE_STM32MP1=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
# CONFIG_ARMV7_VIRT is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_TARGET_MICROGEA_STM32MP1=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
# CONFIG_ARMV7_VIRT is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_TARGET_MICROGEA_STM32MP1=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
# CONFIG_ARMV7_VIRT is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_ARMV7_VIRT is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_ENV_OFFSET_REDUND=0x4C0000
CONFIG_TYPEC_STUSB160X=y
# CONFIG_ARMV7_NONSEC is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_RESET_SCMI=y
CONFIG_DM_RNG=y
+CONFIG_RNG_OPTEE=y
CONFIG_RNG_STM32MP1=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_ARMV7_VIRT is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_ARMV7_VIRT is not set
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0xc2000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_TYPEC_STUSB160X=y
# CONFIG_ARMV7_NONSEC is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_RESET_SCMI=y
CONFIG_DM_RNG=y
+CONFIG_RNG_OPTEE=y
CONFIG_RNG_STM32MP1=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="stmark2"
+CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_TARGET_STMARK2=y
CONFIG_MCFTMR=y
-CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_TIMESTAMP=y
CONFIG_SYS_MONITOR_BASE=0x47E00400
CONFIG_USE_BOOTARGS=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_ENV_ADDR=0xC0000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xC0000
CONFIG_VERSION_VARIABLE=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SH_SCIF_CLK_FREQ=52000000
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SH_QSPI=y
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
+CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_ENV_ADDR=0x188000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00100000
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x188000
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=3000000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
+CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_TARGET_DEVELOPERBOX=y
CONFIG_AHCI=y
-CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_FIT=y
CONFIG_BOOTSTAGE_STASH_SIZE=4096
CONFIG_HUSH_PARSER=y
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ZYNQ_MAC_IN_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_OFFSET_REDUND=0x180000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x2f400000
CONFIG_LTO=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=392192
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_PREBOOT="echo PCI:; pci enum; pci 1; usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi"
CONFIG_DEFAULT_FDT_FILE="imx6q-tbs2910.dtb"
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Matrix U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_DEBUG_UART_BASE=0x87e024000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core"
+CONFIG_SYS_LOAD_ADDR=0x500000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x500000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e024000000 debug maxcpus=48 rootwait rw root=/dev/sda2 coherent_pool=16M"
CONFIG_SPL_SIZE_LIMIT=0x4b000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
CONFIG_SPL_SIZE_LIMIT=0x4B000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x18000000
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x18000000
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x18000000
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2a00000
CONFIG_DEFAULT_DEVICE_TREE="total_compute"
+CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xff000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
+CONFIG_SYS_LOAD_ADDR=0xa1000000
CONFIG_ARCH_ATH79=y
CONFIG_BOARD_TPLINK_WDR4300=y
CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000
-CONFIG_SYS_LOAD_ADDR=0xa1000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x44800000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_DEVICE_TREE="kmtuge1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_TUGE1=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_CMD_UBIFS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="UEC0"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox"
CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_SYS_MEMTEST_START=0x00800000
CONFIG_SYS_MEMTEST_END=0x00ffffff
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_DEVICE_TREE="kmtuxa1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_TUXX1=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
-CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_CMD_UBIFS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="UEC0"
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" u200"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU"
CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_SYS_LOAD_ADDR=0x6000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_LOAD_ADDR=0x6000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_USE_PREBOOT=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-usbarmory"
# CONFIG_CMD_BMODE is not set
+CONFIG_SYS_LOAD_ADDR=0x72000000
CONFIG_SYS_MEMTEST_START=0x70000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x72000000
CONFIG_BOOTCOMMAND="run distro_bootcmd; setenv bootargs console=${console} ${bootargs_default}; ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; bootz ${kernel_addr_r} - ${fdt_addr_r}"
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x43500000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x43500000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vexpress-v2p-ca9"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x90000000
+CONFIG_ENV_ADDR=0x47F80000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_MONITOR_BASE=0x40000000
CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash"
CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb"
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x47F80000
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_ARM_PL180_MMCI=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
-CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=520192
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
-CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=520192
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_ENV_OFFSET=0x10000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="at91-vinco"
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y
CONFIG_BOARD_VOCORE2=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BOOT_GET_KBD=y
-CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_IMX_HAB=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=785408
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_IMX_HAB=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=785408
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" wetek-core2"
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_ENV_ADDR=0x100000
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0x100000
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0"
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1"
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_CMD_FRU=y
CONFIG_DEFINE_TCM_OCM_MMAP=y
CONFIG_COUNTER_FREQUENCY=100000000
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL=y
CONFIG_CMD_FRU=y
CONFIG_CMD_ZYNQ_AES=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_DISPLAY=y
CONFIG_SPL_GZIP=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
-CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SPL=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_BASE=0xff010000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_CPU_FREQ_HZ=500000000
-CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_DEBUG_UART=y
CONFIG_BOOTSTAGE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="ZynqMP r5> "
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
CONFIG_CMD_FRU=y
CONFIG_ZYNQMP_USB=y
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_ZYNQ_GEM=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_CADENCE_TTC=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
CONFIG_RTC_ZYNQMP=y
CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_XTFPGA_KC705=y
CONFIG_SYS_LOAD_ADDR=0x02000000
+CONFIG_ENV_ADDR=0xF7FE0000
+CONFIG_XTFPGA_KC705=y
CONFIG_SYS_MONITOR_BASE=0xF6000000
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_CMD_PING=y
CONFIG_CMD_DIAG=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xF7FE0000
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_VERSION_VARIABLE=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_SYS_LOAD_ADDR=0x0
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_SYS_LOAD_ADDR=0x0
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=0
# CONFIG_ZYNQ_DDRC_INIT is not set
# CONFIG_CMD_ZYNQ is not set
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_SYS_LOAD_ADDR=0x0
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
#ccflags-y += -DET_DEBUG -DDEBUG
obj-$(CONFIG_$(SPL_TPL_)PARTITIONS) += part.o
-obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o
-obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o
-obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o
-obj-$(CONFIG_$(SPL_)AMIGA_PARTITION) += part_amiga.o
-obj-$(CONFIG_$(SPL_)EFI_PARTITION) += part_efi.o
+obj-$(CONFIG_$(SPL_TPL_)MAC_PARTITION) += part_mac.o
+obj-$(CONFIG_$(SPL_TPL_)DOS_PARTITION) += part_dos.o
+obj-$(CONFIG_$(SPL_TPL_)ISO_PARTITION) += part_iso.o
+obj-$(CONFIG_$(SPL_TPL_)AMIGA_PARTITION) += part_amiga.o
+obj-$(CONFIG_$(SPL_TPL_)EFI_PARTITION) += part_efi.o
/* Look up the device */
dev = blk_get_device_by_str(ifname, dev_str, dev_desc);
if (dev < 0) {
+ printf("** Bad device specification %s %s **\n",
+ ifname, dev_str);
ret = dev;
goto cleanup;
}
It is possible to run U-Boot under valgrind to check memory allocations::
- valgrind u-boot
+ valgrind ./u-boot
+
+For more detailed results, enable `CONFIG_VALGRIND`. There are many false
+positives due to `malloc` itself. Suppress these with::
+
+ valgrind --suppressions=scripts/u-boot.supp ./u-boot
If you are running sandbox SPL or TPL, then valgrind will not by default
notice when U-Boot jumps from TPL to SPL, or from SPL to U-Boot proper. To
-fix this, use::
-
- valgrind --trace-children=yes u-boot
+fix this, use `--trace-children=yes`. To show who alloc'd some troublesome
+memory, use `--track-origins=yes`. To uncover possible errors, try running all
+unit tests with::
+ valgrind --track-origins=yes --suppressions=scripts/u-boot.supp ./u-boot -Tc 'ut all'
Testing
-------
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mn_bsh_smm_s2
+=================
+
+U-Boot for the BSH SystemMaster (SMM) S2 board family.
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/ARM-software/arm-trusted-firmware
+tag: v2.5
+
+.. code-block:: bash
+
+ $ make PLAT=imx8mn IMX_BOOT_UART_BASE=0x30a60000 bl31
+ $ cp build/imx8mn/release/bl31.bin $(srctree)
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+ $ chmod +x firmware-imx-8.9.bin
+ $ ./firmware-imx-8.9
+ $ cp firmware-imx-8.9/firmware/ddr/synopsys/ddr3*.bin $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make imx8mn_bsh_smm_s2_defconfig
+ $ make
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+
+Start the board in USB serial downloader mode, plug-in the USB-OTG port and
+load flash.bin using Freescale/NXP UUU tool:
+
+.. code-block:: bash
+
+ $ uuu -v flash.bin
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+BSH Hausgeraete GmbH
+====================
+
+.. toctree::
+ :maxdepth: 2
+
+ imx8mn_bsh_smm_s2
-device ide-hd,drive=mydisk,bus=ahci.0
You will have to run 'scsi scan' to use it.
+
+Debug UART
+----------
+
+The following settings provide a debug UART for the virt machine::
+
+ CONFIG_DEBUG_UART=y
+ CONFIG_DEBUG_UART_NS16550=y
+ CONFIG_DEBUG_UART_BASE=0x10000000
+ CONFIG_DEBUG_UART_CLOCK=3686400
armltd/index
atmel/index
broadcom/index
+ bsh/index
congatec/index
coreboot/index
emulation/index
Installation
------------
-First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for your board::
+Build
+^^^^^
+Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
$ make <your board name here, see Boards section>_defconfig
This will build ``u-boot.bin`` in the configured output directory.
+Generate FIT image
+^^^^^^^^^^^^^^^^^^
+See doc/uImage.FIT for more details
+
+Pack android boot image
+^^^^^^^^^^^^^^^^^^^^^^^
+We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
+and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
+with appended dtb, so let's mimic linux to satisfy stock bootloader:
+
+- create dump dtb::
+
+ workdir=/tmp/prepare_payload
+ mkdir -p "$workdir"
+ cd "$workdir"
+ mock_dtb="$workdir"/payload_mock.dtb
+
+ dtc -I dts -O dtb -o "$mock_dtb" << EOF
+ /dts-v1/;
+ / {
+ memory {
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0 0 0>;
+ };
+
+ chosen { };
+ };
+ EOF
+
+- gzip u-boot ``gzip u-boot.bin``
+- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
+
+Now we've got everything to build android boot image:::
+
+ mkbootimg --base 0x0 --kernel_offset 0x00008000 \
+ --ramdisk_offset 0x02000000 --tags_offset 0x01e00000 \
+ --pagesize 4096 --second_offset 0x00f00000 \
+ --ramdisk "$fit_image" \
+ --kernel u-boot.bin.gz-dtb \
+ -o boot.img
+
+Flash image with your phone's flashing method.
+
Boards
------------
starqlte
It may be pure u-boot (with loading u-boot's payload from flash in mind),
or u-boot + u-boot's payload.
-It should be kept in mind, that SBOOT binary patches it's payload after loading
-in address range 0x401f8550-0x401f9280. Given SBOOT loads payload to 0x40001000,
-a range of 0x1f7550-0x1f8280 (2061648-2065024) in a payload file
-will be corrupted after loading to RAM.
-
Creating payload file
"""""""""""""""""""""
- Assemble FIT image for your kernel
-- Create a file for u-boot payload ``touch sboot-payload``
-- Write zeroes till 0x200000 address to be sure SBOOT won't corrupt your info
- ``dd if=/dev/zero of=sboot-payload bs=$((0x200000)) count=1``
-- Write u-boot to the start of the payload ``dd if=<u-boot.bin path> of=sboot-payload``
-- Write FIT image to payload from 0x200000 address
- ``dd if=<FIT image path> of=sboot-payload seek=1 bs=2M``
Creating android boot image
"""""""""""""""""""""""""""
Once payload created, it's time for android image::
- mkbootimg --base 0x40000000 --kernel_offset 0x00000000 --ramdisk_offset 0x01000000 --tags_offset 0x00000100 --pagesize 2048 --second_offset 0x00f00000 --kernel <sboot-payload path> -o uboot.img
+ uboot=<path to u-boot.bin file>
+ ramdisk=<path to FIT payload file>
+ mkbootimg --base 0x40000000 --kernel_offset 0x00000000 --ramdisk_offset 0x01000000 --tags_offset 0x00000100 --pagesize 2048 --second_offset 0x00f00000 --kernel "$uboot" --ramdisk "$ramdisk" -o uboot.img
Note, that stock Samsung bootloader ignores offsets, set in mkbootimg.
device or SD card) or type of boot device (e.g. USB disk). The parameters to
the func macro (passed in by the internal implementation of the header) are:
-- Upper-case disk type (MMC, SATA, SCSI, IDE, USB, DHCP, PXE, VIRTIO).
+- Upper-case disk type (DHCP, HOST, IDE, MMC, NVME, PXE, SATA, SCSI, UBIFS, USB,
+ VIRTIO).
- Lower-case disk type (same options as above).
- ID of the specific disk (MMC only) or ignored for other types.
- convert at least one existing board to use driver model serial
- (if no boards remain that don't use driver model) remove the old code
-This may be a good time to move your board to use device tree also. Mostly
+This may be a good time to move your board to use the device tree too. Mostly
this involves these steps:
- define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE
- build and get u-boot-dtb.bin so you can test it
- Your drivers can now use device tree
- For device tree in SPL, define CONFIG_SPL_OF_CONTROL
+
+
+Converting boards to CONFIG_DM_SERIAL
+-------------------------------------
+
+If your SoC has a serial driver that uses driver model (has U_BOOT_DRIVER() in
+it), then you may still find that your board has not been converted. To convert
+your board, enable the option and see if you can get it working.
+
+Firstly you will have a lot more success if you have a method of debugging your
+board, such as a JTAG connection. Failing that the debug UART is useful,
+although since you are trying to get the UART driver running, it will interfere
+with your efforts eventually.
+
+Secondly, while the UART is a relatively simple peripheral, it may need quite a
+few pieces to be up and running before it will work, such as the correct pin
+muxing, clocks, power domains and possibly even GPIOs, if an external
+transceiver is used. Look at other boards that use the same SoC, for clues as to
+what is needed.
+
+Thirdly, when added tags, put them in a xxx-u-boot.dtsi file, where xxx is your
+board name, or SoC name. There may already be a file for your SoC which contains
+what you need. U-Boot automatically includes these files: see :ref:`dttweaks`.
+
+Here are some things you might need to consider:
+
+1. The serial driver itself needs to be present before relocation, so that the
+ U-Boot banner appears. Make sure it has a u-boot,pre-reloc tag in the device
+ tree, so that the serial driver is bound when U-Boot starts.
+
+ For example, on iMX8::
+
+ lpuart3: serial@5a090000 {
+ compatible = "fsl,imx8qm-lpuart";
+ ...
+ };
+
+ put this in your xxx-u-boot.dtsi file::
+
+ &lpuart3 {
+ u-boot,dm-pre-proper;
+ };
+
+2. If your serial port requires a particular pinmux configuration, you may need
+ a pinctrl driver. This needs to have a u-boot,pre-reloc tag also. Take care
+ that any subnodes have the same tag, if they are needed to make the correct
+ pinctrl available.
+
+ For example, on RK3288, the UART2 uses uart2_xfer::
+
+ uart2: serial@ff690000 {
+ ...
+ pinctrl-0 = <&uart2_xfer>;
+ };
+
+ which is defined as follows::
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3228-pinctrl";
+
+ uart2: uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>,
+ <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ ...
+ };
+
+ This means you must make the uart2-xfer node available as well as all its
+ parents, so put this in your xxx-u-boot.dtsi file::
+
+ &pinctrl {
+ u-boot,dm-pre-reloc;
+ };
+
+ &uart2 {
+ u-boot,dm-pre-reloc;
+ };
+
+ &uart2_xfer {
+ u-boot,dm-pre-reloc;
+ };
+
+3. The same applies to power domains. For example, if a particular power domain
+ must be enabled for the serial port to work, you need to ensure it is
+ available before relocation:
+
+ For example, on iMX8, put this in your xxx-u-boot.dtsi file::
+
+ &pd_dma {
+ u-boot,dm-pre-proper;
+ };
+
+ &pd_dma_lpuart3 {
+ u-boot,dm-pre-proper;
+ };
+
+4. The same applies to clocks, in the same way. Make sure that when your driver
+ requests a clock, typically with clk_get_by_index(), it is available.
+
+
+Generally a failure to find a required device will cause an error which you can
+catch, if you have the debug UART working. U-Boot outputs serial data to the
+debug UART until the point where the real serial driver takes over. This point
+is marked by gd->flags having the GD_FLG_SERIAL_READY flag set. This change
+happens in serial_init() in serial-uclass.c so until that point the debug UART
+is used. You can see the relevant code in putc()
+, for example::
+
+ /* if we don't have a console yet, use the debug UART */
+ if (IS_ENABLED(CONFIG_DEBUG_UART) && !(gd->flags & GD_FLG_SERIAL_READY)) {
+ printch(c);
+ return;
+ }
+ ... carries on to use the console / serial driver
+
+Note that in device_probe() the call to pinctrl_select_state() silently fails
+if the pinctrl driver fails. You can add a temporary check there if needed.
+
+Why do we have all these tags? The problem is that before relocation we don't
+want to bind all the drivers since memory is limited and the CPU may be running
+at a slow speed. So many boards will fail to boot without this optimisation, or
+may take a long time to start up (e.g. hundreds of milliseconds). The tags tell
+U-Boot which drivers to bind.
+
+The good news is that this problem is normally solved by the SoC, so that any
+boards that use it will work as normal. But in some cases there are multiple
+UARTs or multiple pinmux options, which means that each board may need to do
+some customisation.
+
+Serial in SPL
+-------------
+
+A similar process is needed in SPL, but in this case the u-boot,dm-spl or
+u-boot,dm-tpl tags are used. Add these in the same way as above, to ensure that
+the SPL device tree contains the required nodes (see spl/u-boot-spl.dtb for
+what it actually contains).
+
+Removing old code
+-----------------
+
+In some cases there may be initialisation code that is no-longer needed when
+driver model is used, such as setting up the pin muxing, or enabling a clock.
+Be sure to remove this.
+
+Example patch
+-------------
+
+See this serial_patch_ for iMX7.
+
+.. _serial_patch: https://patchwork.ozlabs.org/project/uboot/patch/20220314232406.1945308-1-festevam@gmail.com/
---------
To assist with debugging events, enable `CONFIG_EVENT_DEBUG` and
-`CONFIG_CMD_EVENT`. The :doc:`../usage/event` command can then be used to
+`CONFIG_CMD_EVENT`. The :doc:`../usage/cmd/event` command can then be used to
provide a spy list.
It is also possible to list spy information from the U-Boot executable,, using
--- /dev/null
+LEDs connected to PWM (Linux compatible)
+
+Required properties:
+- compatible : should be "pwm-leds".
+
+Each LED is represented as a sub-node of the pwm-leds device. Each
+node's name represents the name of the corresponding LED.
+
+LED sub-node properties:
+- pwms : (required) LED pwm channel, see "pwms property" in
+ doc/device-tree-bindings/pwm/pwm.txt
+- label : (optional) LED label, see "label property" in
+ doc/device-tree-bindings/led/common.txt
+- max-brightness : (optional, unsigned, default 255) Maximum brightness possible
+ for the LED
+- active-low : (optional, boolean, default false) For PWMs where the LED is
+ wired to supply rather than ground
+- u-boot,default-brightness : (optional, unsigned, default 0) Initial state
+ of pwm-leds
+
+Example:
+
+leds {
+ compatible = "pwm-leds";
+ status = "okay";
+
+ blue {
+ label = "led-blue";
+ pwms = <&pwm1 0 100000 0>;
+ max-brightness = <255>;
+ u-boot,default-brightness = <127>;
+ };
+
+ green {
+ label = "led-green";
+ pwms = <&pwm2 0 100000 0>;
+ max-brightness = <255>;
+ u-boot,default-brightness = <127>;
+ };
+
+ red {
+ label = "led-red";
+ pwms = <&pwm3 0 100000 0>;
+ max-brightness = <255>;
+ u-boot,default-brightness = <127>;
+ };
+}
"ti,am64-ddrss" for am642
- reg-names cfg - Map the controller configuration region
ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
+ ss - Map the DDRSS configuration region
- reg: Contains the register map per reg-names.
- power-domains: Should contain two entries:
- an entry to TISCI DDR CFG device
- ti,pi-data: An array containing the phy independent block settings
- ti,phy-data: An array containing the ddr phy settings.
+Optional properties:
+--------------------
+- reg-names ss - Map the DDRSS configuration region
+- reg: Must add "ss" to list if the above ss region is included.
+- ti,ecc-enable: Boolean flag to enable ECC. This will reduce available DDR
+ by 1/9.
+
Example (J721E):
================
* UEFI run-time services driver
An operating system requires a hardware description which can either be
-presented as ACPI table (CONFIG\_GENERATE\_ACPI\_TABLE=y) or as device-tree
+presented as ACPI table (CONFIG\_GENERATE\_ACPI\_TABLE=y) or as device-tree.
The load address of the device-tree may be provided as parameter *fdt\_addr*. If
this address is not specified, the bootefi command will try to fall back in
sequence to:
-------------
To use the *bootefi* command you must specify CONFIG\_CMD\_BOOTEFI=y.
+The *bootefi bootmgr* sub-command requries CMD\_BOOTEFI\_BOOTMGR=y.
The *bootefi hello* sub-command requries CMD\_BOOTEFI\_HELLO=y.
The *bootefi selftest* sub-command depends on CMD\_BOOTEFI\_SELFTEST=y.
--------
* *bootm* for launching UEFI binaries packed in FIT images
-* *booti*, *bootm*, *bootz* for launching a Linux kernel without using the
- UEFI sub-system
-* *efidebug* for setting UEFI boot variables
+* :doc:`booti<booti>`, *bootm*, *bootz* for launching a Linux kernel without
+ using the UEFI sub-system
+* *efidebug* for setting UEFI boot variables and boot options
just shows `?`.
-See :doc:`../develop/event` for more information on events.
+See :doc:`../../develop/event` for more information on events.
Example
-------
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2021, Kory Maincent <kory.maincent@bootlin.com>
-U-Boot extension board usage (CONFIG_EXTENSION)
-===============================================
+extension command
+=================
Synopsis
--------
------------
The return value $? is always 0 (true).
-
-
mode
speed mode to set.
- CONFIG_MMC_SPEED_MODE_SET should be enabled. The required speed mode is
- passed as the index from the following list.
-
- 0 - MMC_LEGACY
- 1 - MMC_HS
- 2 - SD_HS
- 3 - MMC_HS_52
- 4 - MMC_DDR_52
- 5 - UHS_SDR12
- 6 - UHS_SDR25
- 7 - UHS_SDR50
- 8 - UHS_DDR50
- 9 - UHS_SDR104
- 10 - MMC_HS_200
- 11 - MMC_HS_400
- 12 - MMC_HS_400_ES
+ CONFIG_MMC_SPEED_MODE_SET should be enabled. The requested speed mode is
+ passed as a decimal number according to the following table:
+
+ ========== ==========================
+ Speed mode Description
+ ========== ==========================
+ 0 MMC legacy
+ 1 MMC High Speed (26MHz)
+ 2 SD High Speed (50MHz)
+ 3 MMC High Speed (52MHz)
+ 4 MMC DDR52 (52MHz)
+ 5 UHS SDR12 (25MHz)
+ 6 UHS SDR25 (50MHz)
+ 7 UHS SDR50 (100MHz)
+ 8 UHS DDR50 (50MHz)
+ 9 UHS SDR104 (208MHz)
+ 10 HS200 (200MHz)
+ 11 HS400 (200MHz)
+ 12 HS400ES (200MHz)
+ ========== ==========================
A speed mode can be set only if it has already been enabled in the device tree
The default value is defined by CONFIG_BOOTDELAY.
The value of 'bootdelay' is overridden by the /config/bootdelay value in
the device-tree if CONFIG_OF_CONTROL=y.
- Does it really make sense that the devicetree overrides the user setting?
bootcmd
The command that is run if the user does not enter the shell during the
if set to "no" (any string beginning with 'n'),
"bootp" and "dhcp" will just load perform a lookup of the
configuration from the BOOTP server, but not try to
- load any image using TFTP or DHCP.
+ load any image.
autostart
if set to "yes", an image loaded using the "bootp", "dhcp",
.. toctree::
:maxdepth: 1
- acpi
- addrmap
- askenv
- base
- bootefi
- booti
- bootmenu
- button
- x86/cbsysinfo
- conitrace
- echo
- event
- exception
- extension
- exit
- false
- fatinfo
- fatload
- for
- load
- loady
- mbr
- md
- mmc
- pinmux
- pstore
- qfw
- reset
- sbi
- sf
- scp03
- setexpr
- size
- true
- ums
- wdt
+ cmd/acpi
+ cmd/addrmap
+ cmd/askenv
+ cmd/base
+ cmd/bootefi
+ cmd/booti
+ cmd/bootmenu
+ cmd/button
+ cmd/cbsysinfo
+ cmd/conitrace
+ cmd/echo
+ cmd/event
+ cmd/exception
+ cmd/extension
+ cmd/exit
+ cmd/false
+ cmd/fatinfo
+ cmd/fatload
+ cmd/for
+ cmd/load
+ cmd/loady
+ cmd/mbr
+ cmd/md
+ cmd/mmc
+ cmd/pinmux
+ cmd/pstore
+ cmd/qfw
+ cmd/reset
+ cmd/sbi
+ cmd/sf
+ cmd/scp03
+ cmd/setexpr
+ cmd/size
+ cmd/true
+ cmd/ums
+ cmd/wdt
+
+Booting OS
+----------
+
+.. toctree::
+ :maxdepth: 1
+
+ os/plan9
+ os/vxworks
+.. SPDX-License-Identifier: GPL-2.0+
+.. Steven Stallion
+.. June 2013
+
+Plan 9
+======
+
Plan 9 from Bell Labs kernel images require additional setup to pass
configuration information to the kernel. An environment variable named
confaddr must be defined with the same value as CONFADDR (see mem.h).
If no command line arguments or bootargs are defined, CONFADDR is left
uninitialized to permit manual configuration. For example, PC-style
-configuration could be simulated by issuing a fatload in bootcmd:
+configuration could be simulated by issuing a fatload in bootcmd::
# setenv bootcmd fatload mmc 0 $confaddr plan9.ini; ...; bootm
-
-Steven Stallion
-June 2013
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2013, Miao Yan <miao.yan@windriver.com>
-# Copyright (C) 2015-2018, Bin Meng <bmeng.cn@gmail.com>
-# Copyright (C) 2019, Lihua Zhao <lihua.zhao@windriver.com>
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2013, Miao Yan <miao.yan@windriver.com>
+.. Copyright (C) 2015-2018, Bin Meng <bmeng.cn@gmail.com>
+.. Copyright (C) 2019, Lihua Zhao <lihua.zhao@windriver.com>
-VxWorks Support
-===============
+VxWorks
+=======
This document describes the information about U-Boot loading VxWorks kernel.
U-Boot supports loading VxWorks kernels via 'bootvx' and 'bootm' commands.
For booting old kernels (6.9.x) on PowerPC and ARM, and all kernel versions
on other architectures, 'bootvx' shall be used. For booting VxWorks 7 kernels
-on PowerPC and ARM, 'bootm' shall be used.
+on PowerPC/ARM/RISC-V, 'bootm' shall be used.
With CONFIG_EFI_LOADER option, it's possible to chain load a VxWorks x86 kernel
via the UEFI boot loader application for VxWorks loaded by 'bootefi' command.
-VxWorks 7 on PowerPC and ARM
----------------------------
+VxWorks 7 on PowerPC/ARM/RISC-V
+-------------------------------
From VxWorks 7, VxWorks starts adopting device tree as its hardware description
mechanism (for PowerPC and ARM), thus requiring boot interface changes.
This section will describe the new interface.
For PowerPC, the calling convention of the new VxWorks entry point conforms to
the ePAPR standard, which is shown below (see ePAPR for more details):
+.. code-block:: c
+
void (*kernel_entry)(fdt_addr, 0, 0, EPAPR_MAGIC, boot_IMA, 0, 0)
For ARM, the calling convention is shown below:
+.. code-block:: c
+
void (*kernel_entry)(void *fdt_addr)
When using the Linux compatible standard DTB, the calling convention of VxWorks
entry point is exactly the same as the Linux kernel.
+For RISC-V, there is no legacy bootm flow as VxWorks always uses the same boot
+interface as the Linux kernel, with the calling convention below::
+
+ void (*kernel_entry)(unsigned long hartid, void *fdt_addr)
+
When booting a VxWorks 7 kernel (uImage format), the parameters passed to bootm
-is like below:
+is like below::
bootm <kernel image address> - <device tree address>
CONFIG_FRAMEBUFFER_SET_VESA_MODE need remain set but care must be taken
at which VESA mode is to be set. The supported pixel format is 32-bit
RGBA, hence the available VESA mode can only be one of the following:
+
* FRAMEBUFFER_VESA_MODE_10F
* FRAMEBUFFER_VESA_MODE_112
* FRAMEBUFFER_VESA_MODE_115
static struct pci_device_id ahci_pci_supported[] = {
{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) },
{ PCI_DEVICE(0x1b21, 0x0611) },
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6121) },
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6145) },
{},
};
return ret;
}
+ ret = blk_probe_or_unbind(dev);
+ if (ret < 0)
+ /* TODO: undo create */
+ return ret;
+
return 0;
}
failed_number++;
continue;
}
+
+ ret = device_probe(dev);
+ if (ret < 0) {
+ debug("Probing %s failed (%d)\n", dev->name, ret);
+ ret = fsl_unbind_device(blk);
+ if (ret)
+ return ret;
+
+ failed_number++;
+ continue;
+ }
}
if (failed_number == nr_ports)
continue;
}
+ ret = blk_probe_or_unbind(dev);
+ if (ret < 0)
+ /* TODO: undo create */
+ continue;
+
/* If we got here, the current SATA port was probed
* successfully, so set the probe status to successful.
*/
failed_number++;
continue;
}
+
+ ret = device_probe(dev);
+ if (ret < 0) {
+ debug("Probing %s failed (%d)\n", dev->name, ret);
+ ret = sil_unbind_device(blk);
+ device_unbind(dev);
+ if (ret)
+ return ret;
+
+ failed_number++;
+ continue;
+ }
}
if (failed_number == sata_info.maxport)
return flags & req_flags ? 0 : 1;
}
+int blk_find_first(enum blk_flag_t flags, struct udevice **devp)
+{
+ int ret;
+
+ for (ret = uclass_find_first_device(UCLASS_BLK, devp);
+ *devp && !blk_flags_check(*devp, flags);
+ ret = uclass_find_next_device(devp))
+ return 0;
+
+ return -ENODEV;
+}
+
+int blk_find_next(enum blk_flag_t flags, struct udevice **devp)
+{
+ int ret;
+
+ for (ret = uclass_find_next_device(devp);
+ *devp && !blk_flags_check(*devp, flags);
+ ret = uclass_find_next_device(devp))
+ return 0;
+
+ return -ENODEV;
+}
+
int blk_first_device_err(enum blk_flag_t flags, struct udevice **devp)
{
int ret;
blksz, size, &blk_dev);
if (ret)
return ret;
+
+ ret = blk_probe_or_unbind(blk_dev);
+ if (ret)
+ return ret;
}
}
return CRF_APB_DBG_TRACE_CTRL;
case dbg_tstmp:
return CRF_APB_DBG_TSTMP_CTRL;
+ case dp_video_ref:
+ return CRF_APB_DP_VIDEO_REF_CTRL;
+ case dp_audio_ref:
+ return CRF_APB_DP_AUDIO_REF_CTRL;
+ case dp_stc_ref:
+ return CRF_APB_DP_STC_REF_CTRL;
case gpu_ref ... gpu_pp1_ref:
return CRF_APB_GPU_REF_CTRL;
case ddr_ref:
case dll_ref:
return zynqmp_clk_get_dll_rate(priv);
case gem_tsu_ref:
+ case dp_video_ref ... dp_stc_ref:
case pl0 ... pl3:
case gem0_ref ... gem3_ref:
case gem0_tx ... gem3_tx:
help
This enables support clock driver for i.MX8MP platforms.
+config SPL_CLK_IMX8MQ
+ bool "SPL clock support for i.MX8MQ"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MQ
+
+config CLK_IMX8MQ
+ bool "Clock support for i.MX8MQ"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ select CLK_COMPOSITE_CCF
+ help
+ This enables support clock driver for i.MX8MQ platforms.
+
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
+ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
-static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
- PLL_1416X_RATE(1800000000U, 225, 3, 0),
- PLL_1416X_RATE(1600000000U, 200, 3, 0),
- PLL_1416X_RATE(1200000000U, 300, 3, 1),
- PLL_1416X_RATE(1000000000U, 250, 3, 1),
- PLL_1416X_RATE(800000000U, 200, 3, 1),
- PLL_1416X_RATE(750000000U, 250, 2, 2),
- PLL_1416X_RATE(700000000U, 350, 3, 2),
- PLL_1416X_RATE(600000000U, 300, 3, 2),
-};
-
-static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
- PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
-};
-
-static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
- .type = PLL_1443X,
- .rate_table = imx8mm_drampll_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+
static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
clk_dm(IMX8MM_DRAM_PLL,
imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
- base + 0x50, &imx8mm_dram_pll));
+ base + 0x50, &imx_1443x_dram_pll));
clk_dm(IMX8MM_ARM_PLL,
imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
- base + 0x84, &imx8mm_arm_pll));
+ base + 0x84, &imx_1416x_pll));
clk_dm(IMX8MM_SYS_PLL1,
imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
- base + 0x94, &imx8mm_sys_pll));
+ base + 0x94, &imx_1416x_pll));
clk_dm(IMX8MM_SYS_PLL2,
imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
- base + 0x104, &imx8mm_sys_pll));
+ base + 0x104, &imx_1416x_pll));
clk_dm(IMX8MM_SYS_PLL3,
imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
- base + 0x114, &imx8mm_sys_pll));
+ base + 0x114, &imx_1416x_pll));
/* PLL bypass out */
clk_dm(IMX8MM_DRAM_PLL_BYPASS,
imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
clk_dm(IMX8MM_CLK_I2C4,
imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MM_CLK_PWM1,
+ imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MM_CLK_PWM2,
+ imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MM_CLK_PWM3,
+ imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MM_CLK_PWM4,
+ imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
clk_dm(IMX8MM_CLK_WDOG,
imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
clk_dm(IMX8MM_CLK_USDHC3,
imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MM_CLK_OCOTP_ROOT,
imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ clk_dm(IMX8MM_CLK_PWM1_ROOT,
+ imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ clk_dm(IMX8MM_CLK_PWM2_ROOT,
+ imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ clk_dm(IMX8MM_CLK_PWM3_ROOT,
+ imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ clk_dm(IMX8MM_CLK_PWM4_ROOT,
+ imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
clk_dm(IMX8MM_CLK_USDHC1_ROOT,
imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MM_CLK_USDHC2_ROOT,
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
-static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
- PLL_1416X_RATE(1800000000U, 225, 3, 0),
- PLL_1416X_RATE(1600000000U, 200, 3, 0),
- PLL_1416X_RATE(1200000000U, 300, 3, 1),
- PLL_1416X_RATE(1000000000U, 250, 3, 1),
- PLL_1416X_RATE(800000000U, 200, 3, 1),
- PLL_1416X_RATE(750000000U, 250, 2, 2),
- PLL_1416X_RATE(700000000U, 350, 3, 2),
- PLL_1416X_RATE(600000000U, 300, 3, 2),
-};
-
-static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
- PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
-};
-
-static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
- .type = PLL_1443X,
- .rate_table = imx8mn_drampll_tbl,
- .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mn_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mn_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
-};
-
static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
clk_dm(IMX8MN_DRAM_PLL,
imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
- base + 0x50, &imx8mn_dram_pll));
+ base + 0x50, &imx_1443x_dram_pll));
clk_dm(IMX8MN_ARM_PLL,
imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
- base + 0x84, &imx8mn_arm_pll));
+ base + 0x84, &imx_1416x_pll));
clk_dm(IMX8MN_SYS_PLL1,
imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
- base + 0x94, &imx8mn_sys_pll));
+ base + 0x94, &imx_1416x_pll));
clk_dm(IMX8MN_SYS_PLL2,
imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
- base + 0x104, &imx8mn_sys_pll));
+ base + 0x104, &imx_1416x_pll));
clk_dm(IMX8MN_SYS_PLL3,
imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
- base + 0x114, &imx8mn_sys_pll));
+ base + 0x114, &imx_1416x_pll));
/* PLL bypass out */
clk_dm(IMX8MN_DRAM_PLL_BYPASS,
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
-static const struct imx_pll14xx_rate_table imx8mp_pll1416x_tbl[] = {
- PLL_1416X_RATE(1800000000U, 225, 3, 0),
- PLL_1416X_RATE(1600000000U, 200, 3, 0),
- PLL_1416X_RATE(1200000000U, 300, 3, 1),
- PLL_1416X_RATE(1000000000U, 250, 3, 1),
- PLL_1416X_RATE(800000000U, 200, 3, 1),
- PLL_1416X_RATE(750000000U, 250, 2, 2),
- PLL_1416X_RATE(700000000U, 350, 3, 2),
- PLL_1416X_RATE(600000000U, 300, 3, 2),
-};
-
-static const struct imx_pll14xx_rate_table imx8mp_drampll_tbl[] = {
- PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
-};
-
-static struct imx_pll14xx_clk imx8mp_dram_pll __initdata = {
- .type = PLL_1443X,
- .rate_table = imx8mp_drampll_tbl,
- .rate_count = ARRAY_SIZE(imx8mp_drampll_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mp_arm_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mp_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mp_sys_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mp_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
-};
-
static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
+static const char *imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+ "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+ "clk_ext4", "audio_pll2_out", };
+
static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
"video_pll1_out", "sys_pll1_100m",};
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
+static const char *imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+ "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+ "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll2_100m", "sys_pll1_800m",
"sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
+static const char *imx8mp_ecspi1_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mp_ecspi2_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mp_ecspi3_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+
static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m" };
static int imx8mp_clk_probe(struct udevice *dev)
{
+ struct clk osc_24m_clk, osc_32k_clk;
void __iomem *base;
+ int ret;
base = (void *)ANATOP_BASE_ADDR;
clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
- clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mp_dram_pll));
- clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll));
- clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll));
- clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll));
- clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll));
+ clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
+ &imx_1443x_dram_pll));
+ clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84,
+ &imx_1416x_pll));
+ clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94,
+ &imx_1416x_pll));
+ clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104,
+ &imx_1416x_pll));
+ clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
+ &imx_1416x_pll));
clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+ ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
+ if (ret)
+ return ret;
+ clk_dm(IMX8MP_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
+
+ ret = clk_get_by_name(dev, "osc_32k", &osc_32k_clk);
+ if (ret)
+ return ret;
+ clk_dm(IMX8MP_CLK_32K, dev_get_clk_ptr(osc_32k_clk.dev));
+
base = dev_read_addr_ptr(dev);
if (!base)
return -EINVAL;
clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
+ clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
+ clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
+ clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
+ clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
+ clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
-
+ clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+ clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+ clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
+ clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "osc_32k", base + 0x44d0, 0));
+ clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+ clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4("hsio_root_clk", "ipg_root", base + 0x45c0, 0));
clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Purism
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imx8mq-clock.h>
+
+#include "clk.h"
+
+static const char *const pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m", "clock-phy-27m", "dummy", };
+static const char *const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char *const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
+static const char *const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
+static const char *const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
+static const char *const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+
+static const char *const imx8mq_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
+static const char *const imx8mq_a53_sels[] = {"clock-osc-25m", "arm_pll_out", "sys_pll2_500m",
+ "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
+ "audio_pll1_out", "sys_pll3_out", };
+
+static const char *const imx8mq_ahb_sels[] = {"clock-osc-25m", "sys_pll1_133m", "sys_pll1_800m",
+ "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
+ "audio_pll1_out", "video_pll1_out", };
+
+static const char *const imx8mq_dram_alt_sels[] = {"osc_25m", "sys_pll1_800m", "sys_pll1_100m",
+ "sys_pll2_500m", "sys_pll2_250m",
+ "sys_pll1_400m", "audio_pll1_out", "sys_pll1_266m", } ;
+
+static const char * const imx8mq_dram_apb_sels[] = {"osc_25m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *const imx8mq_enet_axi_sels[] = {"clock-osc-25m", "sys_pll1_266m", "sys_pll1_800m",
+ "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
+ "video_pll1_out", "sys_pll3_out", };
+
+static const char *const imx8mq_enet_ref_sels[] = {"clock-osc-25m", "sys_pll2_125m", "sys_pll2_50m",
+ "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
+ "video_pll1_out", "clk_ext4", };
+
+static const char *const imx8mq_enet_timer_sels[] = {"clock-osc-25m", "sys_pll2_100m", "audio_pll1_out",
+ "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4",
+ "video_pll1_out", };
+
+static const char *const imx8mq_enet_phy_sels[] = {"clock-osc-25m", "sys_pll2_50m", "sys_pll2_125m",
+ "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
+ "audio_pll2_out", };
+
+static const char *const imx8mq_nand_usdhc_sels[] = {"clock-osc-25m", "sys_pll1_266m", "sys_pll1_800m",
+ "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll1_out", };
+
+static const char *const imx8mq_usb_bus_sels[] = {"clock-osc-25m", "sys_pll2_500m", "sys_pll1_800m",
+ "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+ "clk_ext4", "audio_pll2_out", };
+
+static const char *const imx8mq_usdhc1_sels[] = {"clock-osc-25m", "sys_pll1_400m", "sys_pll1_800m",
+ "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
+ "audio_pll2_out", "sys_pll1_100m", };
+
+static const char *const imx8mq_usdhc2_sels[] = {"clock-osc-25m", "sys_pll1_400m", "sys_pll1_800m",
+ "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
+ "audio_pll2_out", "sys_pll1_100m", };
+
+static const char *const imx8mq_i2c1_sels[] = {"clock-osc-25m", "sys_pll1_160m", "sys_pll2_50m",
+ "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *const imx8mq_i2c2_sels[] = {"clock-osc-25m", "sys_pll1_160m", "sys_pll2_50m",
+ "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *const imx8mq_i2c3_sels[] = {"clock-osc-25m", "sys_pll1_160m", "sys_pll2_50m",
+ "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *const imx8mq_i2c4_sels[] = {"clock-osc-25m", "sys_pll1_160m", "sys_pll2_50m",
+ "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *const imx8mq_uart1_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext4", "audio_pll2_out", };
+
+static const char *const imx8mq_uart2_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
+static const char *const imx8mq_uart3_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext4", "audio_pll2_out", };
+
+static const char *const imx8mq_uart4_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
+static const char *const imx8mq_wdog_sels[] = {"clock-osc-25m", "sys_pll1_133m", "sys_pll1_160m",
+ "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
+ "sys_pll1_80m", "sys_pll2_166m", };
+
+static const char *const imx8mq_qspi_sels[] = {"clock-osc-25m", "sys_pll1_400m", "sys_pll2_333m",
+ "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
+ "sys_pll3_out", "sys_pll1_100m", };
+
+static const char *const imx8mq_usb_core_sels[] = {"clock-osc-25m", "sys_pll1_100m", "sys_pll1_40m",
+ "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
+static const char *const imx8mq_usb_phy_sels[] = {"clock-osc-25m", "sys_pll1_100m", "sys_pll1_40m",
+ "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
+static const char *const imx8mq_ecspi1_sels[] = {"clock-osc-25m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *const imx8mq_ecspi2_sels[] = {"clock-osc-25m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *const imx8mq_ecspi3_sels[] = {"clock-osc-25m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *const imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
+
+static const char *const pllout_monitor_sels[] = {"clock-osc-25m", "clock-osc-27m", "clock-phy-27m",
+ "dummy", "clock-ckil", "audio_pll1_out_monitor",
+ "audio_pll2_out_monitor", "gpu_pll_out_monitor",
+ "vpu_pll_out_monitor", "video_pll1_out_monitor",
+ "arm_pll_out_monitor", "sys_pll1_out_monitor",
+ "sys_pll2_out_monitor", "sys_pll3_out_monitor",
+ "video_pll2_out_monitor", "dram_pll_out_monitor", };
+
+static int imx8mq_clk_probe(struct udevice *dev)
+{
+ void __iomem *base;
+
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMX8MQ_CLK_32K, clk_register_fixed_rate(NULL, "ckil", 32768));
+ clk_dm(IMX8MQ_CLK_27M, clk_register_fixed_rate(NULL, "clock-osc-27m", 27000000));
+
+ clk_dm(IMX8MQ_DRAM_PLL1_REF_SEL,
+ imx_clk_mux("dram_pll_ref_sel", base + 0x60, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MQ_ARM_PLL_REF_SEL,
+ imx_clk_mux("arm_pll_ref_sel", base + 0x28, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MQ_GPU_PLL_REF_SEL,
+ imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MQ_VPU_PLL_REF_SEL,
+ imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MQ_SYS3_PLL1_REF_SEL,
+ imx_clk_mux("sys3_pll_ref_sel", base + 0x48, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MQ_AUDIO_PLL1_REF_SEL,
+ imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MQ_AUDIO_PLL2_REF_SEL,
+ imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MQ_VIDEO_PLL1_REF_SEL,
+ imx_clk_mux("video_pll1_ref_sel", base + 0x10, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MQ_VIDEO2_PLL1_REF_SEL,
+ imx_clk_mux("video_pll2_ref_sel", base + 0x54, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+
+ clk_dm(IMX8MQ_ARM_PLL,
+ imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
+ base + 0x28, &imx_1416x_pll));
+ clk_dm(IMX8MQ_GPU_PLL,
+ imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel",
+ base + 0x18, &imx_1416x_pll));
+ clk_dm(IMX8MQ_VPU_PLL,
+ imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel",
+ base + 0x20, &imx_1416x_pll));
+
+ clk_dm(IMX8MQ_SYS1_PLL1,
+ clk_register_fixed_rate(NULL, "sys1_pll", 800000000));
+ clk_dm(IMX8MQ_SYS2_PLL1,
+ clk_register_fixed_rate(NULL, "sys2_pll", 1000000000));
+ clk_dm(IMX8MQ_SYS2_PLL1,
+ clk_register_fixed_rate(NULL, "sys3_pll", 1000000000));
+ clk_dm(IMX8MQ_AUDIO_PLL1,
+ imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel",
+ base + 0x0, &imx_1443x_pll));
+ clk_dm(IMX8MQ_AUDIO_PLL2,
+ imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel",
+ base + 0x8, &imx_1443x_pll));
+ clk_dm(IMX8MQ_VIDEO_PLL1,
+ imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel",
+ base + 0x10, &imx_1443x_pll));
+
+ /* PLL bypass out */
+ clk_dm(IMX8MQ_ARM_PLL_BYPASS,
+ imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 4, 1,
+ arm_pll_bypass_sels,
+ ARRAY_SIZE(arm_pll_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MQ_GPU_PLL_BYPASS,
+ imx_clk_mux_flags("gpu_pll_bypass", base + 0x18, 4, 1,
+ gpu_pll_bypass_sels,
+ ARRAY_SIZE(gpu_pll_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MQ_VPU_PLL_BYPASS,
+ imx_clk_mux_flags("vpu_pll_bypass", base + 0x20, 4, 1,
+ vpu_pll_bypass_sels,
+ ARRAY_SIZE(vpu_pll_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MQ_AUDIO_PLL1_BYPASS,
+ imx_clk_mux_flags("audio_pll1_bypass", base + 0x0, 4, 1,
+ audio_pll1_bypass_sels,
+ ARRAY_SIZE(audio_pll1_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MQ_AUDIO_PLL2_BYPASS,
+ imx_clk_mux_flags("audio_pll2_bypass", base + 0x8, 4, 1,
+ audio_pll2_bypass_sels,
+ ARRAY_SIZE(audio_pll2_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MQ_VIDEO_PLL1_BYPASS,
+ imx_clk_mux_flags("video_pll1_bypass", base + 0x10, 4, 1,
+ video_pll1_bypass_sels,
+ ARRAY_SIZE(video_pll1_bypass_sels),
+ CLK_SET_RATE_PARENT));
+
+ /* PLL out gate */
+ clk_dm(IMX8MQ_DRAM_PLL_OUT,
+ imx_clk_gate("dram_pll_out", "dram_pll_ref_sel",
+ base + 0x60, 13));
+ clk_dm(IMX8MQ_ARM_PLL_OUT,
+ imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+ base + 0x28, 11));
+ clk_dm(IMX8MQ_GPU_PLL_OUT,
+ imx_clk_gate("gpu_pll_out", "gpu_pll_bypass",
+ base + 0x18, 11));
+ clk_dm(IMX8MQ_VPU_PLL_OUT,
+ imx_clk_gate("vpu_pll_out", "vpu_pll_bypass",
+ base + 0x20, 11));
+ clk_dm(IMX8MQ_AUDIO_PLL1_OUT,
+ imx_clk_gate("audio_pll1_out", "audio_pll1_bypass",
+ base + 0x0, 11));
+ clk_dm(IMX8MQ_AUDIO_PLL2_OUT,
+ imx_clk_gate("audio_pll2_out", "audio_pll2_bypass",
+ base + 0x8, 11));
+ clk_dm(IMX8MQ_VIDEO_PLL1_OUT,
+ imx_clk_gate("video_pll1_out", "video_pll1_bypass",
+ base + 0x10, 11));
+
+ clk_dm(IMX8MQ_SYS1_PLL_OUT,
+ imx_clk_gate("sys_pll1_out", "sys1_pll",
+ base + 0x30, 11));
+ clk_dm(IMX8MQ_SYS2_PLL_OUT,
+ imx_clk_gate("sys_pll2_out", "sys2_pll",
+ base + 0x3c, 11));
+ clk_dm(IMX8MQ_SYS3_PLL_OUT,
+ imx_clk_gate("sys_pll3_out", "sys3_pll",
+ base + 0x48, 11));
+ clk_dm(IMX8MQ_VIDEO2_PLL_OUT,
+ imx_clk_gate("video_pll2_out", "video_pll2_ref_sel",
+ base + 0x54, 11));
+
+ /* SYS PLL fixed output */
+ clk_dm(IMX8MQ_SYS1_PLL_40M,
+ imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+ clk_dm(IMX8MQ_SYS1_PLL_80M,
+ imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+ clk_dm(IMX8MQ_SYS1_PLL_100M,
+ imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+ clk_dm(IMX8MQ_SYS1_PLL_133M,
+ imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+ clk_dm(IMX8MQ_SYS1_PLL_160M,
+ imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+ clk_dm(IMX8MQ_SYS1_PLL_200M,
+ imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+ clk_dm(IMX8MQ_SYS1_PLL_266M,
+ imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+ clk_dm(IMX8MQ_SYS1_PLL_400M,
+ imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+ clk_dm(IMX8MQ_SYS1_PLL_800M,
+ imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+
+ clk_dm(IMX8MQ_SYS2_PLL_50M,
+ imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+ clk_dm(IMX8MQ_SYS2_PLL_100M,
+ imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+ clk_dm(IMX8MQ_SYS2_PLL_125M,
+ imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+ clk_dm(IMX8MQ_SYS2_PLL_166M,
+ imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+ clk_dm(IMX8MQ_SYS2_PLL_200M,
+ imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+ clk_dm(IMX8MQ_SYS2_PLL_250M,
+ imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+ clk_dm(IMX8MQ_SYS2_PLL_333M,
+ imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+ clk_dm(IMX8MQ_SYS2_PLL_500M,
+ imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+ clk_dm(IMX8MQ_SYS2_PLL_1000M,
+ imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+
+ clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL1_DIV,
+ imx_clk_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3));
+ clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL2_DIV,
+ imx_clk_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3));
+ clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL1_DIV,
+ imx_clk_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3));
+ clk_dm(IMX8MQ_CLK_MON_GPU_PLL_DIV,
+ imx_clk_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3));
+ clk_dm(IMX8MQ_CLK_MON_VPU_PLL_DIV,
+ imx_clk_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3));
+ clk_dm(IMX8MQ_CLK_MON_ARM_PLL_DIV,
+ imx_clk_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3));
+ clk_dm(IMX8MQ_CLK_MON_SYS_PLL1_DIV,
+ imx_clk_divider("sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3));
+ clk_dm(IMX8MQ_CLK_MON_SYS_PLL2_DIV,
+ imx_clk_divider("sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3));
+ clk_dm(IMX8MQ_CLK_MON_SYS_PLL3_DIV,
+ imx_clk_divider("sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3));
+ clk_dm(IMX8MQ_CLK_MON_DRAM_PLL_DIV,
+ imx_clk_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3));
+ clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL2_DIV,
+ imx_clk_divider("video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3));
+ clk_dm(IMX8MQ_CLK_MON_SEL,
+ imx_clk_mux_flags("pllout_monitor_sel", base + 0x74, 0, 4,
+ pllout_monitor_sels,
+ ARRAY_SIZE(pllout_monitor_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MQ_CLK_MON_CLK2_OUT,
+ imx_clk_gate4("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4));
+
+ base = dev_read_addr_ptr(dev);
+ if (!base) {
+ printf("%s : base failed\n", __func__);
+ return -EINVAL;
+ }
+
+ clk_dm(IMX8MQ_CLK_A53_SRC,
+ imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+ imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels)));
+ clk_dm(IMX8MQ_CLK_A53_CG,
+ imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+ clk_dm(IMX8MQ_CLK_A53_DIV,
+ imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+ base + 0x8000, 0, 3));
+ clk_dm(IMX8MQ_CLK_A53_CORE,
+ imx_clk_mux2("arm_a53_src", base + 0x9880, 24, 1,
+ imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)));
+
+ clk_dm(IMX8MQ_CLK_AHB,
+ imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels,
+ base + 0x9000));
+ clk_dm(IMX8MQ_CLK_IPG_ROOT,
+ imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+
+ clk_dm(IMX8MQ_CLK_ENET_AXI,
+ imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels,
+ base + 0x8880));
+ clk_dm(IMX8MQ_CLK_NAND_USDHC_BUS,
+ imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8mq_nand_usdhc_sels,
+ base + 0x8900));
+ clk_dm(IMX8MQ_CLK_USB_BUS,
+ imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
+
+ /* DRAM */
+ clk_dm(IMX8MQ_CLK_DRAM_CORE,
+ imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1,
+ imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels)));
+ clk_dm(IMX8MQ_CLK_DRAM_ALT,
+ imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
+ clk_dm(IMX8MQ_CLK_DRAM_APB,
+ imx8m_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
+
+ /* IP */
+ clk_dm(IMX8MQ_CLK_USDHC1,
+ imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels,
+ base + 0xac00));
+ clk_dm(IMX8MQ_CLK_USDHC2,
+ imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels,
+ base + 0xac80));
+ clk_dm(IMX8MQ_CLK_I2C1,
+ imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00));
+ clk_dm(IMX8MQ_CLK_I2C2,
+ imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80));
+ clk_dm(IMX8MQ_CLK_I2C3,
+ imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00));
+ clk_dm(IMX8MQ_CLK_I2C4,
+ imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MQ_CLK_WDOG,
+ imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900));
+ clk_dm(IMX8MQ_CLK_UART1,
+ imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00));
+ clk_dm(IMX8MQ_CLK_UART2,
+ imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80));
+ clk_dm(IMX8MQ_CLK_UART3,
+ imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000));
+ clk_dm(IMX8MQ_CLK_UART4,
+ imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080));
+ clk_dm(IMX8MQ_CLK_QSPI,
+ imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80));
+ clk_dm(IMX8MQ_CLK_USB_CORE_REF,
+ imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
+ clk_dm(IMX8MQ_CLK_USB_PHY_REF,
+ imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
+ clk_dm(IMX8MQ_CLK_ECSPI1,
+ imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
+ clk_dm(IMX8MQ_CLK_ECSPI2,
+ imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MQ_CLK_ECSPI3,
+ imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
+
+ clk_dm(IMX8MQ_CLK_ECSPI1_ROOT,
+ imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+ clk_dm(IMX8MQ_CLK_ECSPI2_ROOT,
+ imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+ clk_dm(IMX8MQ_CLK_ECSPI3_ROOT,
+ imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+ clk_dm(IMX8MQ_CLK_I2C1_ROOT,
+ imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+ clk_dm(IMX8MQ_CLK_I2C2_ROOT,
+ imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+ clk_dm(IMX8MQ_CLK_I2C3_ROOT,
+ imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+ clk_dm(IMX8MQ_CLK_I2C4_ROOT,
+ imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ clk_dm(IMX8MQ_CLK_UART1_ROOT,
+ imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
+ clk_dm(IMX8MQ_CLK_UART2_ROOT,
+ imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
+ clk_dm(IMX8MQ_CLK_UART3_ROOT,
+ imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
+ clk_dm(IMX8MQ_CLK_UART4_ROOT,
+ imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
+ clk_dm(IMX8MQ_CLK_OCOTP_ROOT,
+ imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ clk_dm(IMX8MQ_CLK_USDHC1_ROOT,
+ imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+ clk_dm(IMX8MQ_CLK_USDHC2_ROOT,
+ imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+ clk_dm(IMX8MQ_CLK_WDOG1_ROOT,
+ imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+ clk_dm(IMX8MQ_CLK_WDOG2_ROOT,
+ imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+ clk_dm(IMX8MQ_CLK_WDOG3_ROOT,
+ imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+ clk_dm(IMX8MQ_CLK_QSPI_ROOT,
+ imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+ clk_dm(IMX8MQ_CLK_USB1_CTRL_ROOT,
+ imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+ clk_dm(IMX8MQ_CLK_USB2_CTRL_ROOT,
+ imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0));
+ clk_dm(IMX8MQ_CLK_USB1_PHY_ROOT,
+ imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
+ clk_dm(IMX8MQ_CLK_USB2_PHY_ROOT,
+ imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0));
+
+ clk_dm(IMX8MQ_CLK_ENET_REF,
+ imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels,
+ base + 0xa980));
+ clk_dm(IMX8MQ_CLK_ENET_TIMER,
+ imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels,
+ base + 0xaa00));
+ clk_dm(IMX8MQ_CLK_ENET_PHY_REF,
+ imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels,
+ base + 0xaa80));
+ clk_dm(IMX8MQ_CLK_ENET1_ROOT,
+ imx_clk_gate4("enet1_root_clk", "enet_axi",
+ base + 0x40a0, 0));
+
+ clk_dm(IMX8MQ_CLK_DRAM_ALT_ROOT,
+ imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
+
+ return 0;
+}
+
+static const struct udevice_id imx8mq_clk_ids[] = {
+ { .compatible = "fsl,imx8mq-ccm" },
+ { },
+};
+
+U_BOOT_DRIVER(imx8mq_clk) = {
+ .name = "clk_imx8mq",
+ .id = UCLASS_CLK,
+ .of_match = imx8mq_clk_ids,
+ .ops = &ccf_clk_ops,
+ .probe = imx8mq_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
void *base;
/* Anatop clocks */
- base = (void *)ANATOP_BASE_ADDR;
+ base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
clk_dm(IMXRT1020_CLK_PLL2_SYS,
imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
void *base;
/* Anatop clocks */
- base = (void *)ANATOP_BASE_ADDR;
+ base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
+ PLL_1416X_RATE(1800000000U, 225, 3, 0),
+ PLL_1416X_RATE(1600000000U, 200, 3, 0),
+ PLL_1416X_RATE(1500000000U, 375, 3, 1),
+ PLL_1416X_RATE(1400000000U, 350, 3, 1),
+ PLL_1416X_RATE(1200000000U, 300, 3, 1),
+ PLL_1416X_RATE(1000000000U, 250, 3, 1),
+ PLL_1416X_RATE(800000000U, 200, 3, 1),
+ PLL_1416X_RATE(750000000U, 250, 2, 2),
+ PLL_1416X_RATE(700000000U, 350, 3, 2),
+ PLL_1416X_RATE(600000000U, 300, 3, 2),
+};
+
+const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
+ PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
+ PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
+ PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
+ PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+ PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+};
+
+struct imx_pll14xx_clk imx_1443x_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
+};
+EXPORT_SYMBOL_GPL(imx_1443x_pll);
+
+struct imx_pll14xx_clk imx_1443x_dram_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
+ .flags = CLK_GET_RATE_NOCACHE,
+};
+EXPORT_SYMBOL_GPL(imx_1443x_dram_pll);
+
+struct imx_pll14xx_clk imx_1416x_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
+};
+EXPORT_SYMBOL_GPL(imx_1416x_pll);
+
static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
struct clk_pll14xx *pll, unsigned long rate)
{
int flags;
};
+extern struct imx_pll14xx_clk imx_1416x_pll;
+extern struct imx_pll14xx_clk imx_1443x_pll;
+extern struct imx_pll14xx_clk imx_1443x_dram_pll;
+
struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
void __iomem *base,
const struct imx_pll14xx_clk *pll_clk);
#
# Copyright (c) 2013 Google, Inc
-obj-y += device.o fdtaddr.o lists.o root.o uclass.o util.o
+obj-y += device.o fdtaddr.o lists.o root.o uclass.o util.o tag.o
obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi.o
obj-$(CONFIG_DEVRES) += devres.o
obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o
return ret;
}
+ INIT_LIST_HEAD((struct list_head *)&gd->dmtag_list);
+
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Linaro Limited
+ * Author: AKASHI Takahiro
+ */
+
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <dm/tag.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/types.h>
+
+struct udevice;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dev_tag_set_ptr(struct udevice *dev, enum dm_tag_t tag, void *ptr)
+{
+ struct dmtag_node *node;
+
+ if (!dev || tag >= DM_TAG_COUNT)
+ return -EINVAL;
+
+ list_for_each_entry(node, &gd->dmtag_list, sibling) {
+ if (node->dev == dev && node->tag == tag)
+ return -EEXIST;
+ }
+
+ node = calloc(sizeof(*node), 1);
+ if (!node)
+ return -ENOSPC;
+
+ node->dev = dev;
+ node->tag = tag;
+ node->ptr = ptr;
+ list_add_tail(&node->sibling, (struct list_head *)&gd->dmtag_list);
+
+ return 0;
+}
+
+int dev_tag_set_val(struct udevice *dev, enum dm_tag_t tag, ulong val)
+{
+ struct dmtag_node *node;
+
+ if (!dev || tag >= DM_TAG_COUNT)
+ return -EINVAL;
+
+ list_for_each_entry(node, &gd->dmtag_list, sibling) {
+ if (node->dev == dev && node->tag == tag)
+ return -EEXIST;
+ }
+
+ node = calloc(sizeof(*node), 1);
+ if (!node)
+ return -ENOSPC;
+
+ node->dev = dev;
+ node->tag = tag;
+ node->val = val;
+ list_add_tail(&node->sibling, (struct list_head *)&gd->dmtag_list);
+
+ return 0;
+}
+
+int dev_tag_get_ptr(struct udevice *dev, enum dm_tag_t tag, void **ptrp)
+{
+ struct dmtag_node *node;
+
+ if (!dev || tag >= DM_TAG_COUNT)
+ return -EINVAL;
+
+ list_for_each_entry(node, &gd->dmtag_list, sibling) {
+ if (node->dev == dev && node->tag == tag) {
+ *ptrp = node->ptr;
+ return 0;
+ }
+ }
+
+ return -ENOENT;
+}
+
+int dev_tag_get_val(struct udevice *dev, enum dm_tag_t tag, ulong *valp)
+{
+ struct dmtag_node *node;
+
+ if (!dev || tag >= DM_TAG_COUNT)
+ return -EINVAL;
+
+ list_for_each_entry(node, &gd->dmtag_list, sibling) {
+ if (node->dev == dev && node->tag == tag) {
+ *valp = node->val;
+ return 0;
+ }
+ }
+
+ return -ENOENT;
+}
+
+int dev_tag_del(struct udevice *dev, enum dm_tag_t tag)
+{
+ struct dmtag_node *node, *tmp;
+
+ if (!dev || tag >= DM_TAG_COUNT)
+ return -EINVAL;
+
+ list_for_each_entry_safe(node, tmp, &gd->dmtag_list, sibling) {
+ if (node->dev == dev && node->tag == tag) {
+ list_del(&node->sibling);
+ free(node);
+
+ return 0;
+ }
+ }
+
+ return -ENOENT;
+}
+
+int dev_tag_del_all(struct udevice *dev)
+{
+ struct dmtag_node *node, *tmp;
+ bool found = false;
+
+ if (!dev)
+ return -EINVAL;
+
+ list_for_each_entry_safe(node, tmp, &gd->dmtag_list, sibling) {
+ if (node->dev == dev) {
+ list_del(&node->sibling);
+ free(node);
+ found = true;
+ }
+ }
+
+ if (found)
+ return 0;
+
+ return -ENOENT;
+}
bool "Freescale Crypto Driver Support"
select SHA_HW_ACCEL
# hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL
+ select MISC if DM
imply SPL_CRYPTO if (ARM && SPL)
imply CMD_HASH
help
config CAAM_64BIT
bool
- default y if PHYS_64BIT && !ARCH_IMX8M
+ default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
help
Select Crypto driver for 64 bits CAAM version
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
* Based on CAAM driver in drivers/crypto/caam in Linux
*/
#include <linux/kernel.h>
#include <log.h>
#include <malloc.h>
-#include "fsl_sec.h"
+#include <power-domain.h>
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
#include <asm/cache.h>
#include <asm/fsl_pamu.h>
#endif
+#include <dm.h>
#include <dm/lists.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
#include <linux/delay.h>
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#endif
};
+#if CONFIG_IS_ENABLED(DM)
+struct udevice *caam_dev;
+#else
#define SEC_ADDR(idx) \
(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
#define SEC_JR0_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+struct caam_regs caam_st;
+#endif
-struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+static inline u32 jr_start_reg(u8 jrid)
+{
+ return (1 << jrid);
+}
-static inline void start_jr0(uint8_t sec_idx)
+static inline void start_jr(struct caam_regs *caam)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+ ccsr_sec_t *sec = caam->sec;
u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
u32 scfgr = sec_in32(&sec->scfgr);
+ u32 jrstart = jr_start_reg(caam->jrid);
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
*/
if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
(scfgr & SEC_SCFGR_VIRT_EN))
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
} else {
/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
}
}
-static inline void jr_reset_liodn(uint8_t sec_idx)
-{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- sec_out32(&sec->jrliodnr[0].ls, 0);
-}
-
-static inline void jr_disable_irq(uint8_t sec_idx)
+static inline void jr_disable_irq(struct jr_regs *regs)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
uint32_t jrcfg = sec_in32(®s->jrcfg1);
jrcfg = jrcfg | JR_INTMASK;
sec_out32(®s->jrcfg1, jrcfg);
}
-static void jr_initregs(uint8_t sec_idx)
+static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
sec_out32(®s->irs, JR_SIZE);
if (!jr->irq)
- jr_disable_irq(sec_idx);
+ jr_disable_irq(regs);
}
-static int jr_init(uint8_t sec_idx)
+static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jobring *jr = &jr0[sec_idx];
-
+ struct jobring *jr = &caam->jr[sec_idx];
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+#endif
memset(jr, 0, sizeof(struct jobring));
- jr->jq_id = DEFAULT_JR_ID;
+ jr->jq_id = caam->jrid;
jr->irq = DEFAULT_IRQ;
#ifdef CONFIG_FSL_CORENET
memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->op_size);
- start_jr0(sec_idx);
-
- jr_initregs(sec_idx);
-
- return 0;
-}
-
-static int jr_sw_cleanup(uint8_t sec_idx)
-{
- struct jobring *jr = &jr0[sec_idx];
-
- jr->head = 0;
- jr->tail = 0;
- jr->read_idx = 0;
- jr->write_idx = 0;
- memset(jr->info, 0, sizeof(jr->info));
- memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
- memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
-
- return 0;
-}
-
-static int jr_hw_reset(uint8_t sec_idx)
-{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- uint32_t timeout = 100000;
- uint32_t jrint, jrcr;
-
- sec_out32(®s->jrcr, JRCR_RESET);
- do {
- jrint = sec_in32(®s->jrint);
- } while (((jrint & JRINT_ERR_HALT_MASK) ==
- JRINT_ERR_HALT_INPROGRESS) && --timeout);
-
- jrint = sec_in32(®s->jrint);
- if (((jrint & JRINT_ERR_HALT_MASK) !=
- JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
- return -1;
-
- timeout = 100000;
- sec_out32(®s->jrcr, JRCR_RESET);
- do {
- jrcr = sec_in32(®s->jrcr);
- } while ((jrcr & JRCR_RESET) && --timeout);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ if (!ofnode_valid(scu_node))
+#endif
+ start_jr(caam);
- if (timeout == 0)
- return -1;
+ jr_initregs(sec_idx, caam);
return 0;
}
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
void (*callback)(uint32_t status, void *arg),
- void *arg, uint8_t sec_idx)
+ void *arg, uint8_t sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
int head = jr->head;
uint32_t desc_word;
int length = desc_len(desc_addr);
return 0;
}
-static int jr_dequeue(int sec_idx)
+static int jr_dequeue(int sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
int head = jr->head;
int tail = jr->tail;
int idx, i, found;
{
struct result *x = arg;
x->status = status;
-#ifndef CONFIG_SPL_BUILD
caam_jr_strstatus(status);
-#endif
x->done = 1;
}
static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
{
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
unsigned long long timeval = 0;
unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
struct result op;
memset(&op, 0, sizeof(op));
- ret = jr_enqueue(desc, desc_done, &op, sec_idx);
+ ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
if (ret) {
debug("Error in SEC enq\n");
ret = JQ_ENQ_ERR;
udelay(1);
timeval += 1;
- ret = jr_dequeue(sec_idx);
+ ret = jr_dequeue(sec_idx, caam);
if (ret) {
debug("Error in SEC deq\n");
ret = JQ_DEQ_ERR;
return run_descriptor_jr_idx(desc, 0);
}
+static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
+{
+ struct jobring *jr = &caam->jr[sec_idx];
+
+ jr->head = 0;
+ jr->tail = 0;
+ jr->read_idx = 0;
+ jr->write_idx = 0;
+ memset(jr->info, 0, sizeof(jr->info));
+ memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
+ memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
+
+ return 0;
+}
+
+static int jr_hw_reset(struct jr_regs *regs)
+{
+ uint32_t timeout = 100000;
+ uint32_t jrint, jrcr;
+
+ sec_out32(®s->jrcr, JRCR_RESET);
+ do {
+ jrint = sec_in32(®s->jrint);
+ } while (((jrint & JRINT_ERR_HALT_MASK) ==
+ JRINT_ERR_HALT_INPROGRESS) && --timeout);
+
+ jrint = sec_in32(®s->jrint);
+ if (((jrint & JRINT_ERR_HALT_MASK) !=
+ JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
+ return -1;
+
+ timeout = 100000;
+ sec_out32(®s->jrcr, JRCR_RESET);
+ do {
+ jrcr = sec_in32(®s->jrcr);
+ } while ((jrcr & JRCR_RESET) && --timeout);
+
+ if (timeout == 0)
+ return -1;
+
+ return 0;
+}
+
static inline int jr_reset_sec(uint8_t sec_idx)
{
- if (jr_hw_reset(sec_idx) < 0)
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
+ if (jr_hw_reset(caam->regs) < 0)
return -1;
/* Clean up the jobring structure maintained by software */
- jr_sw_cleanup(sec_idx);
+ jr_sw_cleanup(sec_idx, caam);
return 0;
}
return jr_reset_sec(0);
}
-static inline int sec_reset_idx(uint8_t sec_idx)
+int sec_reset(void)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
+ ccsr_sec_t *sec = caam->sec;
uint32_t mcfgr = sec_in32(&sec->mcfgr);
uint32_t timeout = 100000;
return 0;
}
-int sec_reset(void)
-{
- return sec_reset_idx(0);
-}
-#ifndef CONFIG_SPL_BUILD
+
static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
{
u32 *desc;
return ret;
}
-static int instantiate_rng(u8 sec_idx, int gen_sk)
+static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk)
{
u32 *desc;
u32 rdsta_val;
int ret = 0, sh_idx, size;
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
return ret;
}
-static u8 get_rng_vid(uint8_t sec_idx)
+static u8 get_rng_vid(ccsr_sec_t *sec)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
u8 vid;
if (caam_get_era() < 10) {
* By default, the TRNG runs for 200 clocks per sample;
* 1200 clocks per sample generates better entropy.
*/
-static void kick_trng(int ent_delay, uint8_t sec_idx)
+static void kick_trng(int ent_delay, ccsr_sec_t *sec)
{
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 val;
sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
}
-static int rng_init(uint8_t sec_idx)
+static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
{
int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 inst_handles;
* the TRNG parameters.
*/
if (!inst_handles) {
- kick_trng(ent_delay, sec_idx);
+ kick_trng(ent_delay, sec);
ent_delay += 400;
}
/*
* interval, leading to a sucessful initialization of
* the RNG.
*/
- ret = instantiate_rng(sec_idx, gen_sk);
+ ret = instantiate_rng(sec_idx, sec, gen_sk);
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
if (ret) {
printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
return ret;
}
-#endif
+
int sec_init_idx(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ if (!caam_dev) {
+ printf("caam_jr: caam not found\n");
+ return -1;
+ }
+ caam = dev_get_priv(caam_dev);
+#else
+ caam_st.sec = (void *)SEC_ADDR(sec_idx);
+ caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ caam_st.jrid = 0;
+ caam = &caam_st;
+#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+
+ if (ofnode_valid(scu_node))
+ goto init;
+#endif
+ ccsr_sec_t *sec = caam->sec;
+ uint32_t mcr = sec_in32(&sec->mcfgr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+ uint32_t jrdid_ms = 0;
+#endif
#ifdef CONFIG_FSL_CORENET
uint32_t liodnr;
uint32_t liodn_ns;
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+ jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
+ sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
+#endif
+ jr_reset();
#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SPL_BUILD
liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
- liodnr = sec_in32(&sec->jrliodnr[0].ls) &
+ liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
~(JRNSLIODN_MASK | JRSLIODN_MASK);
liodnr = liodnr |
(liodn_ns << JRNSLIODN_SHIFT) |
(liodn_s << JRSLIODN_SHIFT);
- sec_out32(&sec->jrliodnr[0].ls, liodnr);
+ sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
#else
- liodnr = sec_in32(&sec->jrliodnr[0].ls);
+ liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
#endif
-
- ret = jr_init(sec_idx);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+init:
+#endif
+ ret = jr_init(sec_idx, caam);
if (ret < 0) {
printf("SEC%u: initialization failed\n", sec_idx);
return -1;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ if (ofnode_valid(scu_node))
+ return ret;
+#endif
#ifdef CONFIG_FSL_CORENET
ret = sec_config_pamu_table(liodn_ns, liodn_s);
pamu_enable();
#endif
-#ifndef CONFIG_SPL_BUILD
- if (get_rng_vid(sec_idx) >= 4) {
- if (rng_init(sec_idx) < 0) {
+
+ if (get_rng_vid(caam->sec) >= 4) {
+ if (rng_init(sec_idx, caam->sec) < 0) {
printf("SEC%u: RNG instantiation failed\n", sec_idx);
return -1;
}
printf("SEC%u: RNG instantiated\n", sec_idx);
}
-#endif
return ret;
}
{
return sec_init_idx(0);
}
+
+#if CONFIG_IS_ENABLED(DM)
+static int jr_power_on(ofnode node)
+{
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+ struct udevice __maybe_unused jr_dev;
+ struct power_domain pd;
+
+ dev_set_ofnode(&jr_dev, node);
+
+ /* Power on Job Ring before access it */
+ if (!power_domain_get(&jr_dev, &pd)) {
+ if (power_domain_on(&pd))
+ return -EINVAL;
+ }
+#endif
+ return 0;
+}
+
+static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+ if (request != CAAM_JR_RUN_DESC)
+ return -ENOSYS;
+
+ return run_descriptor_jr(buf);
+}
+
+static int caam_jr_probe(struct udevice *dev)
+{
+ struct caam_regs *caam = dev_get_priv(dev);
+ fdt_addr_t addr;
+ ofnode node, scu_node;
+ unsigned int jr_node = 0;
+
+ caam_dev = dev;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("caam_jr: crypto not found\n");
+ return -EINVAL;
+ }
+ caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
+ caam->regs = (struct jr_regs *)caam->sec;
+
+ /* Check for enabled job ring node */
+ ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+ if (!ofnode_is_available(node))
+ continue;
+
+ jr_node = ofnode_read_u32_default(node, "reg", -1);
+ if (jr_node > 0) {
+ caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
+ while (!(jr_node & 0x0F))
+ jr_node = jr_node >> 4;
+
+ caam->jrid = jr_node - 1;
+ scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+ if (ofnode_valid(scu_node)) {
+ if (jr_power_on(node))
+ return -EINVAL;
+ }
+ break;
+ }
+ }
+
+ if (sec_init())
+ printf("\nsec_init failed!\n");
+
+ return 0;
+}
+
+static int caam_jr_bind(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct misc_ops caam_jr_ops = {
+ .ioctl = caam_jr_ioctl,
+};
+
+static const struct udevice_id caam_jr_match[] = {
+ { .compatible = "fsl,sec-v4.0" },
+ { }
+};
+
+U_BOOT_DRIVER(caam_jr) = {
+ .name = "caam_jr",
+ .id = UCLASS_MISC,
+ .of_match = caam_jr_match,
+ .ops = &caam_jr_ops,
+ .bind = caam_jr_bind,
+ .probe = caam_jr_probe,
+ .priv_auto = sizeof(struct caam_regs),
+};
+#endif
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*
*/
#define __JR_H
#include <linux/compiler.h>
+#include "fsl_sec.h"
#include "type.h"
+#include <misc.h>
#define JR_SIZE 4
/* Timeout currently defined as 10 sec */
#define JRSLIODN_SHIFT 0
#define JRSLIODN_MASK 0x00000fff
-#define JQ_DEQ_ERR -1
-#define JQ_DEQ_TO_ERR -2
-#define JQ_ENQ_ERR -3
+#define JRDID_MS_PRIM_DID BIT(0)
+#define JRDID_MS_PRIM_TZ BIT(4)
+#define JRDID_MS_TZ_OWN BIT(15)
+
+#define JQ_DEQ_ERR (-1)
+#define JQ_DEQ_TO_ERR (-2)
+#define JQ_ENQ_ERR (-3)
#define RNG4_MAX_HANDLES 2
+enum {
+ /* Run caam jobring descriptor(in buf) */
+ CAAM_JR_RUN_DESC,
+};
+
struct op_ring {
caam_dma_addr_t desc;
uint32_t status;
uint32_t status;
};
+/*
+ * struct caam_regs - CAAM initialization register interface
+ *
+ * Interface to caam memory map, jobring register, jobring storage.
+ */
+struct caam_regs {
+ ccsr_sec_t *sec; /*caam initialization registers*/
+ struct jr_regs *regs; /*jobring configuration registers*/
+ u8 jrid; /*id to identify a jobring*/
+ /*Private sub-storage for a single JobR*/
+ struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+};
+
void caam_jr_strstatus(u32 status);
int run_descriptor_jr(uint32_t *desc);
int "Number of chip selects per controller"
default 4
+config DIMM_SLOTS_PER_CTLR
+ int "Number of DIMM slots per controller"
+ default 1
+
config SYS_FSL_DDR_VER
int
default 50 if SYS_FSL_DDR_VER_50
dram_pll_init(MHZ(1000));
dram_disable_bypass();
break;
+ case 3732:
+ dram_pll_init(MHZ(933));
+ dram_disable_bypass();
+ break;
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();
return pm_api_version;
};
+int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value)
+{
+ int ret;
+
+ ret = xilinx_pm_request(PM_IOCTL, node, IOCTL_SET_GEM_CONFIG,
+ config, value, NULL);
+ if (ret)
+ printf("%s: node %d: set_gem_config %d failed\n",
+ __func__, node, config);
+
+ return ret;
+}
+
int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value)
{
int ret;
int ret;
struct udevice *child;
- if (IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) {
+ if ((IS_ENABLED(CONFIG_SPL_BUILD) &&
+ IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) &&
+ IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) ||
+ (!IS_ENABLED(CONFIG_SPL_BUILD) &&
+ IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN))) {
ret = device_bind_driver_to_node(dev, "zynqmp_power_domain",
"zynqmp_power_domain",
dev_ofnode(dev), &child);
is a mechanism providing automatic GPIO request and config-
uration as part of the gpio-controller's driver probe function.
+config SPL_GPIO_HOG
+ bool "Enable GPIO hog support in SPL"
+ depends on SPL_GPIO_SUPPORT
+ help
+ Enable gpio hog support in SPL
+ The GPIO chip may contain GPIO hog definitions. GPIO hogging
+ is a mechanism providing automatic GPIO request and config-
+ uration as part of the gpio-controller's driver probe function.
+
config DM_GPIO_LOOKUP_LABEL
bool "Enable searching for gpio labelnames"
depends on DM_GPIO
index, desc, flags, index > 0, NULL);
}
+int gpio_request_by_line_name(struct udevice *dev, const char *line_name,
+ struct gpio_desc *desc, int flags)
+{
+ int ret;
+
+ ret = dev_read_stringlist_search(dev, "gpio-line-names", line_name);
+ if (ret < 0)
+ return ret;
+
+ desc->dev = dev;
+ desc->offset = ret;
+ desc->flags = 0;
+
+ ret = dm_gpio_request(desc, line_name);
+ if (ret) {
+ debug("%s: dm_gpio_requestf failed\n", __func__);
+ return ret;
+ }
+
+ ret = dm_gpio_set_dir_flags(desc, flags | desc->flags);
+ if (ret)
+ debug("%s: dm_gpio_set_dir failed\n", __func__);
+
+ return ret;
+}
+
int gpio_request_list_by_name_nodev(ofnode node, const char *list_name,
struct gpio_desc *desc, int max_count,
int flags)
static int gpio_post_bind(struct udevice *dev)
{
- struct udevice *child;
- ofnode node;
-
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_gpio_ops *ops = (struct dm_gpio_ops *)device_get_ops(dev);
static int reloc_done;
}
#endif
- if (CONFIG_IS_ENABLED(OF_REAL) && IS_ENABLED(CONFIG_GPIO_HOG)) {
+ if (CONFIG_IS_ENABLED(GPIO_HOG)) {
+ struct udevice *child;
+ ofnode node;
+
dev_for_each_subnode(node, dev) {
if (ofnode_read_bool(node, "gpio-hog")) {
const char *name = ofnode_get_name(node);
#include <asm/gpio.h>
#include <dm.h>
#include <i2c.h>
+#include <dt-bindings/gpio/gpio.h>
#include <asm/arch/hardware.h>
#define SLG7XL45106_REG 0xdb
struct ofnode_phandle_args *args)
{
desc->offset = (unsigned int)args->args[0];
+ desc->flags = (args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
return 0;
}
#define PCA953X_INVERT 2
#define PCA953X_DIRECTION 3
+#define PCA957X_INPUT 0
+#define PCA957X_OUTPUT 5
+#define PCA957X_INVERT 1
+#define PCA957X_DIRECTION 4
+
+
#define PCA_GPIO_MASK 0x00FF
#define PCA_INT 0x0100
#define PCA953X_TYPE 0x1000
#define MAX_BANK 5
#define BANK_SZ 8
+struct pca95xx_reg {
+ int input;
+ int output;
+ int invert;
+ int direction;
+};
+
+static const struct pca95xx_reg pca953x_regs = {
+ .direction = PCA953X_DIRECTION,
+ .output = PCA953X_OUTPUT,
+ .input = PCA953X_INPUT,
+ .invert = PCA953X_INVERT,
+};
+
+static const struct pca95xx_reg pca957x_regs = {
+ .direction = PCA957X_DIRECTION,
+ .output = PCA957X_OUTPUT,
+ .input = PCA957X_INPUT,
+ .invert = PCA957X_INVERT,
+};
+
/*
- * struct pca953x_info - Data for pca953x
+ * struct pca953x_info - Data for pca953x/pca957x
*
* @dev: udevice structure for the device
* @addr: i2c slave address
* @bank_count: the number of banks that the device supports
* @reg_output: array to hold the value of output registers
* @reg_direction: array to hold the value of direction registers
+ * @regs: struct to hold the registers addresses
*/
struct pca953x_info {
struct udevice *dev;
int bank_count;
u8 reg_output[MAX_BANK];
u8 reg_direction[MAX_BANK];
+ const struct pca95xx_reg *regs;
};
static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
static int pca953x_get_value(struct udevice *dev, uint offset)
{
+ struct pca953x_info *info = dev_get_plat(dev);
int ret;
u8 val = 0;
int off = offset % BANK_SZ;
- ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
+ ret = pca953x_read_single(dev, info->regs->input, &val, offset);
if (ret)
return ret;
else
val = info->reg_output[bank] & ~(1 << off);
- ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset);
+ ret = pca953x_write_single(dev, info->regs->output, val, offset);
if (ret)
return ret;
else
val = info->reg_direction[bank] & ~(1 << off);
- ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset);
+ ret = pca953x_write_single(dev, info->regs->direction, val, offset);
if (ret)
return ret;
}
info->chip_type = PCA_CHIP_TYPE(driver_data);
- if (info->chip_type != PCA953X_TYPE) {
- dev_err(dev, "Only support PCA953X chip type now.\n");
- return -EINVAL;
- }
+ if (info->chip_type == PCA953X_TYPE)
+ info->regs = &pca953x_regs;
+ else
+ info->regs = &pca957x_regs;
info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
- ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
+ ret = pca953x_read_regs(dev, info->regs->output, info->reg_output);
if (ret) {
dev_err(dev, "Error reading output register\n");
return ret;
/* Clear the polarity registers to no invert */
memset(val, 0, MAX_BANK);
- ret = pca953x_write_regs(dev, PCA953X_INVERT, val);
+ ret = pca953x_write_regs(dev, info->regs->invert, val);
if (ret < 0) {
dev_err(dev, "Error writing invert register\n");
return ret;
#include <malloc.h>
#include <asm/io.h>
#include <asm/gpio.h>
-#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
-struct sunxi_gpio_plat {
- struct sunxi_gpio *regs;
- const char *bank_name; /* Name of bank, e.g. "B" */
- int gpio_count;
-};
-
#if !CONFIG_IS_ENABLED(DM_GPIO)
static int sunxi_gpio_output(u32 pin, u32 val)
{
.set_flags = sunxi_gpio_set_flags,
};
-/**
- * Returns the name of a GPIO bank
- *
- * GPIO banks are named A, B, C, ...
- *
- * @bank: Bank number (0, 1..n-1)
- * Return: allocated string containing the name
- */
-static char *gpio_bank_name(int bank)
-{
- char *name;
-
- name = malloc(3);
- if (name) {
- name[0] = 'P';
- name[1] = 'A' + bank;
- name[2] = '\0';
- }
-
- return name;
-}
-
static int gpio_sunxi_probe(struct udevice *dev)
{
struct sunxi_gpio_plat *plat = dev_get_plat(dev);
/* Tell the uclass how many GPIOs we have */
if (plat) {
- uc_priv->gpio_count = plat->gpio_count;
+ uc_priv->gpio_count = SUNXI_GPIOS_PER_BANK;
uc_priv->bank_name = plat->bank_name;
}
return 0;
}
-struct sunxi_gpio_soc_data {
- int start;
- int no_banks;
-};
-
-/**
- * We have a top-level GPIO device with no actual GPIOs. It has a child
- * device for each Sunxi bank.
- */
-static int gpio_sunxi_bind(struct udevice *parent)
-{
- struct sunxi_gpio_soc_data *soc_data =
- (struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
- struct sunxi_gpio_plat *plat = dev_get_plat(parent);
- struct sunxi_gpio_reg *ctlr;
- int bank, ret;
-
- /* If this is a child device, there is nothing to do here */
- if (plat)
- return 0;
-
- ctlr = dev_read_addr_ptr(parent);
- for (bank = 0; bank < soc_data->no_banks; bank++) {
- struct sunxi_gpio_plat *plat;
- struct udevice *dev;
-
- plat = calloc(1, sizeof(*plat));
- if (!plat)
- return -ENOMEM;
- plat->regs = &ctlr->gpio_bank[bank];
- plat->bank_name = gpio_bank_name(soc_data->start + bank);
- plat->gpio_count = SUNXI_GPIOS_PER_BANK;
-
- ret = device_bind(parent, parent->driver, plat->bank_name, plat,
- dev_ofnode(parent), &dev);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static const struct sunxi_gpio_soc_data soc_data_a_all = {
- .start = 0,
- .no_banks = SUNXI_GPIO_BANKS,
-};
-
-static const struct sunxi_gpio_soc_data soc_data_l_1 = {
- .start = 'L' - 'A',
- .no_banks = 1,
-};
-
-static const struct sunxi_gpio_soc_data soc_data_l_2 = {
- .start = 'L' - 'A',
- .no_banks = 2,
-};
-
-static const struct sunxi_gpio_soc_data soc_data_l_3 = {
- .start = 'L' - 'A',
- .no_banks = 3,
-};
-
-#define ID(_compat_, _soc_data_) \
- { .compatible = _compat_, .data = (ulong)&soc_data_##_soc_data_ }
-
-static const struct udevice_id sunxi_gpio_ids[] = {
- ID("allwinner,sun4i-a10-pinctrl", a_all),
- ID("allwinner,sun5i-a10s-pinctrl", a_all),
- ID("allwinner,sun5i-a13-pinctrl", a_all),
- ID("allwinner,sun50i-h5-pinctrl", a_all),
- ID("allwinner,sun6i-a31-pinctrl", a_all),
- ID("allwinner,sun6i-a31s-pinctrl", a_all),
- ID("allwinner,sun7i-a20-pinctrl", a_all),
- ID("allwinner,sun8i-a23-pinctrl", a_all),
- ID("allwinner,sun8i-a33-pinctrl", a_all),
- ID("allwinner,sun8i-a83t-pinctrl", a_all),
- ID("allwinner,sun8i-h3-pinctrl", a_all),
- ID("allwinner,sun8i-r40-pinctrl", a_all),
- ID("allwinner,sun8i-v3-pinctrl", a_all),
- ID("allwinner,sun8i-v3s-pinctrl", a_all),
- ID("allwinner,sun9i-a80-pinctrl", a_all),
- ID("allwinner,sun50i-a64-pinctrl", a_all),
- ID("allwinner,sun50i-h6-pinctrl", a_all),
- ID("allwinner,sun50i-h616-pinctrl", a_all),
- ID("allwinner,sun6i-a31-r-pinctrl", l_2),
- ID("allwinner,sun8i-a23-r-pinctrl", l_1),
- ID("allwinner,sun8i-a83t-r-pinctrl", l_1),
- ID("allwinner,sun8i-h3-r-pinctrl", l_1),
- ID("allwinner,sun9i-a80-r-pinctrl", l_3),
- ID("allwinner,sun50i-a64-r-pinctrl", l_1),
- ID("allwinner,sun50i-h6-r-pinctrl", l_2),
- ID("allwinner,sun50i-h616-r-pinctrl", l_1),
- { }
-};
-
U_BOOT_DRIVER(gpio_sunxi) = {
.name = "gpio_sunxi",
.id = UCLASS_GPIO,
- .ops = &gpio_sunxi_ops,
- .of_match = sunxi_gpio_ids,
- .bind = gpio_sunxi_bind,
.probe = gpio_sunxi_probe,
+ .ops = &gpio_sunxi_ops,
};
#endif /* DM_GPIO */
*/
#include <axp_pmic.h>
+#include <clk.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <i2c.h>
+#include <reset.h>
#include <time.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base)
{
- /* Enable p2wi and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
-
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
-
/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
writel(P2WI_CTRL_RESET, &base->ctrl);
sdelay(0x100);
{
struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+ /* Enable p2wi and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
+
sun6i_p2wi_init(base);
}
#endif
static int sun6i_p2wi_probe(struct udevice *bus)
{
struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+ struct reset_ctl *reset;
+ struct clk *clk;
priv->base = dev_read_addr_ptr(bus);
+ reset = devm_reset_control_get(bus, NULL);
+ if (!IS_ERR(reset))
+ reset_deassert(reset);
+
+ clk = devm_clk_get(bus, NULL);
+ if (!IS_ERR(clk))
+ clk_enable(clk);
+
sun6i_p2wi_init(priv->base);
return 0;
static int sun6i_p2wi_child_pre_probe(struct udevice *child)
{
struct dm_i2c_chip *chip = dev_get_parent_plat(child);
+ struct udevice *bus = child->parent;
/* Ensure each transfer is for a single register. */
chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
- return 0;
+ return sun6i_p2wi_probe_chip(bus, chip->chip_addr, 0);
}
static const struct dm_i2c_ops sun6i_p2wi_ops = {
*/
#include <axp_pmic.h>
+#include <clk.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <i2c.h>
+#include <reset.h>
#include <time.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
return sun8i_rsb_do_trans(base);
}
-static void sun8i_rsb_cfg_io(void)
-{
-#ifdef CONFIG_MACH_SUN8I
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
-#elif defined CONFIG_MACH_SUN9I
- sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
-#else
-#error unsupported MACH_SUNXI
-#endif
-}
-
static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
{
u32 div = 0;
static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
{
- /* Enable RSB and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
-
- /* Setup external pins */
- sun8i_rsb_cfg_io();
-
writel(RSB_CTRL_SOFT_RST, &base->ctrl);
sun8i_rsb_set_clk(base);
{
struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ /* Enable RSB and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+ if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
+ } else {
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+ }
+
return sun8i_rsb_init(base);
}
#endif
static int sun8i_rsb_probe(struct udevice *bus)
{
struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+ struct reset_ctl *reset;
+ struct clk *clk;
priv->base = dev_read_addr_ptr(bus);
+ reset = devm_reset_control_get(bus, NULL);
+ if (!IS_ERR(reset))
+ reset_deassert(reset);
+
+ clk = devm_clk_get(bus, NULL);
+ if (!IS_ERR(clk))
+ clk_enable(clk);
+
return sun8i_rsb_init(priv->base);
}
static int sun8i_rsb_child_pre_probe(struct udevice *child)
{
struct dm_i2c_chip *chip = dev_get_parent_plat(child);
+ struct udevice *bus = child->parent;
/* Ensure each transfer is for a single register. */
chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
- return 0;
+ return sun8i_rsb_probe_chip(bus, chip->chip_addr, 0);
}
static const struct dm_i2c_ops sun8i_rsb_ops = {
This option enables support for LEDs connected to the Cortina
Access CAxxxx SOCs.
+config LED_PWM
+ bool "LED PWM"
+ depends on LED && DM_PWM
+ help
+ Enable support for LEDs connected to PWM.
+ Linux compatible ofdata.
config LED_BLINK
bool "Support LED blinking"
obj-$(CONFIG_LED_BCM6358) += led_bcm6358.o
obj-$(CONFIG_LED_BCM6753) += led_bcm6753.o
obj-$(CONFIG_LED_BCM6858) += led_bcm6858.o
+obj-$(CONFIG_LED_PWM) += led_pwm.o
obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o
obj-$(CONFIG_LED_CORTINA) += led_cortina.o
}
#endif
+/* This is superseded by led_post_bind()/led_post_probe() below. */
int led_default_state(void)
{
- struct udevice *dev;
- struct uclass *uc;
+ return 0;
+}
+
+static int led_post_bind(struct udevice *dev)
+{
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
const char *default_state;
- int ret;
- ret = uclass_get(UCLASS_LED, &uc);
- if (ret)
- return ret;
- for (uclass_find_first_device(UCLASS_LED, &dev);
- dev;
- uclass_find_next_device(&dev)) {
- default_state = dev_read_string(dev, "default-state");
- if (!default_state)
- continue;
- ret = device_probe(dev);
- if (ret)
- return ret;
- if (!strncmp(default_state, "on", 2))
- led_set_state(dev, LEDST_ON);
- else if (!strncmp(default_state, "off", 3))
- led_set_state(dev, LEDST_OFF);
- /* default-state = "keep" : device is only probed */
- }
+ uc_plat->label = dev_read_string(dev, "label");
+ if (!uc_plat->label)
+ uc_plat->label = ofnode_get_name(dev_ofnode(dev));
+
+ uc_plat->default_state = LEDST_COUNT;
+
+ default_state = dev_read_string(dev, "default-state");
+ if (!default_state)
+ return 0;
+
+ if (!strncmp(default_state, "on", 2))
+ uc_plat->default_state = LEDST_ON;
+ else if (!strncmp(default_state, "off", 3))
+ uc_plat->default_state = LEDST_OFF;
+ else
+ return 0;
+
+ /*
+ * In case the LED has default-state DT property, trigger
+ * probe() to configure its default state during startup.
+ */
+ return device_probe(dev);
+}
+
+static int led_post_probe(struct udevice *dev)
+{
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+ if (uc_plat->default_state == LEDST_ON ||
+ uc_plat->default_state == LEDST_OFF)
+ led_set_state(dev, uc_plat->default_state);
- return ret;
+ return 0;
}
UCLASS_DRIVER(led) = {
.id = UCLASS_LED,
.name = "led",
.per_device_plat_auto = sizeof(struct led_uc_plat),
+ .post_bind = led_post_bind,
+ .post_probe = led_post_probe,
};
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "bcm6328-led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "bcm6358-led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "bcm6753-led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
#define LEDS_MAX 32
#define LEDS_WAIT 100
+#define LEDS_MAX_BRIGHTNESS 7
/* LED Mode register */
#define LED_MODE_REG 0x0
#define LED_HW_LED_EN_REG 0x08
/* LED Flash control register0 */
#define LED_FLASH_RATE_CONTROL_REG0 0x10
+/* LED Brightness control register0 */
+#define LED_BRIGHTNESS_CONTROL_REG0 0x20
/* Soft LED input register */
#define LED_SW_LED_IP_REG 0xb8
/* Parallel LED Output Polarity Register */
}
#endif
+static int led_set_brightness(struct udevice *dev, unsigned int brightness)
+{
+ struct bcm6858_led_priv *priv = dev_get_priv(dev);
+ u32 offset, shift, mask, value;
+
+ offset = (priv->pin / 8) * 4;
+ shift = (priv->pin % 8) * 4;
+ mask = 0xf << shift;
+
+ /* 8 levels of brightness achieved through PWM */
+ value = (brightness > LEDS_MAX_BRIGHTNESS ?
+ LEDS_MAX_BRIGHTNESS : brightness) << shift;
+
+ debug("%s: %s brightness set to %u\n", __func__, dev->name, value >> shift);
+
+ clrbits_32(priv->regs + LED_BRIGHTNESS_CONTROL_REG0 + offset, mask);
+ setbits_32(priv->regs + LED_BRIGHTNESS_CONTROL_REG0 + offset, value);
+
+ return 0;
+}
+
static enum led_state_t bcm6858_led_get_state(struct udevice *dev)
{
struct bcm6858_led_priv *priv = dev_get_priv(dev);
{
struct bcm6858_led_priv *priv = dev_get_priv(dev);
+ debug("%s: Set led %s to %d\n", __func__, dev->name, state);
+
switch (state) {
case LEDST_OFF:
clrbits_32(priv->regs + LED_SW_LED_IP_REG, (1 << priv->pin));
} else {
struct bcm6858_led_priv *priv = dev_get_priv(dev);
void __iomem *regs;
- unsigned int pin;
+ unsigned int pin, brightness;
regs = dev_remap_addr(dev_get_parent(dev));
if (!regs)
clrbits_32(regs + LED_PLED_OP_PPOL_REG, 1 << pin);
else
setbits_32(regs + LED_PLED_OP_PPOL_REG, 1 << pin);
+
+ brightness = dev_read_u32_default(dev, "default-brightness",
+ LEDS_MAX_BRIGHTNESS);
+ led_set_brightness(dev, brightness);
}
return 0;
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "bcm6858-led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "ca-leds",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
int ret;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
- const char *label;
-
- label = ofnode_read_string(node, "label");
- if (!label)
- label = ofnode_get_name(node);
ret = device_bind_driver_to_node(parent, "gpio_led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 VK
+ * Author: Ivan Vozvakhov <i.vozvakhov@vk.team>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <led.h>
+#include <malloc.h>
+#include <dm/lists.h>
+#include <pwm.h>
+
+#define LEDS_PWM_DRIVER_NAME "led_pwm"
+
+struct led_pwm_priv {
+ struct udevice *pwm;
+ uint period; /* period in ns */
+ uint duty; /* duty cycle in ns */
+ uint channel; /* pwm channel number */
+ bool active_low; /* pwm polarity */
+ bool enabled;
+};
+
+static int led_pwm_enable(struct udevice *dev)
+{
+ struct led_pwm_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = pwm_set_invert(priv->pwm, priv->channel, priv->active_low);
+ if (ret)
+ return ret;
+
+ ret = pwm_set_config(priv->pwm, priv->channel, priv->period, priv->duty);
+ if (ret)
+ return ret;
+
+ ret = pwm_set_enable(priv->pwm, priv->channel, true);
+ if (ret)
+ return ret;
+
+ priv->enabled = true;
+
+ return 0;
+}
+
+static int led_pwm_disable(struct udevice *dev)
+{
+ struct led_pwm_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = pwm_set_config(priv->pwm, priv->channel, priv->period, 0);
+ if (ret)
+ return ret;
+
+ ret = pwm_set_enable(priv->pwm, priv->channel, false);
+ if (ret)
+ return ret;
+
+ priv->enabled = false;
+
+ return 0;
+}
+
+static int led_pwm_set_state(struct udevice *dev, enum led_state_t state)
+{
+ struct led_pwm_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ switch (state) {
+ case LEDST_OFF:
+ ret = led_pwm_disable(dev);
+ break;
+ case LEDST_ON:
+ ret = led_pwm_enable(dev);
+ break;
+ case LEDST_TOGGLE:
+ ret = (priv->enabled) ? led_pwm_disable(dev) : led_pwm_enable(dev);
+ break;
+ default:
+ ret = -ENOSYS;
+ }
+
+ return ret;
+}
+
+static enum led_state_t led_pwm_get_state(struct udevice *dev)
+{
+ struct led_pwm_priv *priv = dev_get_priv(dev);
+
+ return (priv->enabled) ? LEDST_ON : LEDST_OFF;
+}
+
+static int led_pwm_probe(struct udevice *dev)
+{
+ struct led_pwm_priv *priv = dev_get_priv(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+ /* Ignore the top-level LED node */
+ if (!uc_plat->label)
+ return 0;
+
+ return led_pwm_set_state(dev, (priv->enabled) ? LEDST_ON : LEDST_OFF);
+}
+
+static int led_pwm_of_to_plat(struct udevice *dev)
+{
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ struct led_pwm_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
+ uint def_brightness, max_brightness;
+ int ret;
+
+ /* Ignore the top-level LED node */
+ if (!uc_plat->label)
+ return 0;
+
+ ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0, &args);
+ if (ret)
+ return ret;
+
+ ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, &priv->pwm);
+ if (ret)
+ return ret;
+
+ priv->channel = args.args[0];
+ priv->period = args.args[1];
+ priv->active_low = dev_read_bool(dev, "active-low");
+
+ def_brightness = dev_read_u32_default(dev, "u-boot,default-brightness", 0);
+ max_brightness = dev_read_u32_default(dev, "max-brightness", 255);
+ priv->enabled = !!def_brightness;
+
+ /*
+ * No need to handle pwm iverted case (active_low)
+ * because of pwm_set_invert function
+ */
+ if (def_brightness < max_brightness)
+ priv->duty = priv->period * def_brightness / max_brightness;
+ else
+ priv->duty = priv->period;
+
+ return 0;
+}
+
+static int led_pwm_bind(struct udevice *parent)
+{
+ struct udevice *dev;
+ ofnode node;
+ int ret;
+
+ dev_for_each_subnode(node, parent) {
+ ret = device_bind_driver_to_node(parent, LEDS_PWM_DRIVER_NAME,
+ ofnode_get_name(node),
+ node, &dev);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+
+static const struct led_ops led_pwm_ops = {
+ .set_state = led_pwm_set_state,
+ .get_state = led_pwm_get_state,
+};
+
+static const struct udevice_id led_pwm_ids[] = {
+ { .compatible = "pwm-leds" },
+ { }
+};
+
+U_BOOT_DRIVER(led_pwm) = {
+ .name = LEDS_PWM_DRIVER_NAME,
+ .id = UCLASS_LED,
+ .of_match = led_pwm_ids,
+ .ops = &led_pwm_ops,
+ .priv_auto = sizeof(struct led_pwm_priv),
+ .bind = led_pwm_bind,
+ .probe = led_pwm_probe,
+ .of_to_plat = led_pwm_of_to_plat,
+};
CryptoAuthentication module found for example on the Turris Omnia
board.
+config GATEWORKS_SC
+ bool "Gateworks System Controller Support"
+ depends on MISC
+ help
+ Enable access for the Gateworks System Controller used on Gateworks
+ boards to provide a boot watchdog, power control, temperature monitor,
+ voltage ADCs, and EEPROM.
+
config ROCKCHIP_EFUSE
bool "Rockchip e-fuse support"
depends on MISC
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o
+obj-$(CONFIG_GATEWORKS_SC) += gsc.o
obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
while (len--)
crc = crc16_byte(crc, *buffer++);
- return cpu_to_le16(crc);
+ return crc;
}
static int atsha204a_send(struct udevice *dev, const u8 *buf, u8 len)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include <command.h>
+#include <gsc.h>
+#include <i2c.h>
+#include <rtc.h>
+#include <asm/unaligned.h>
+#include <linux/delay.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/ofnode.h>
+#include <dm/read.h>
+
+#define GSC_BUSNO 0
+#define GSC_SC_ADDR 0x20
+#define GSC_HWMON_ADDR 0x29
+#define GSC_RTC_ADDR 0x68
+
+/* System Controller registers */
+enum {
+ GSC_SC_CTRL0 = 0,
+ GSC_SC_CTRL1 = 1,
+ GSC_SC_TIME = 2,
+ GSC_SC_TIME_ADD = 6,
+ GSC_SC_STATUS = 10,
+ GSC_SC_FWCRC = 12,
+ GSC_SC_FWVER = 14,
+ GSC_SC_WP = 15,
+ GSC_SC_RST_CAUSE = 16,
+ GSC_SC_THERM_PROTECT = 19,
+};
+
+/* System Controller Control1 bits */
+enum {
+ GSC_SC_CTRL1_SLEEP_EN = 0, /* 1 = enable sleep */
+ GSC_SC_CTRL1_SLEEP_ACTIVATE = 1, /* 1 = activate sleep */
+ GSC_SC_CTRL1_SLEEP_ADD = 2, /* 1 = latch and add sleep time */
+ GSC_SC_CTRL1_SLEEP_NOWAKEPB = 3, /* 1 = do not wake on sleep on button press */
+ GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */
+ GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */
+ GSC_SC_CTRL1_BOOT_CHK = 6, /* 1 = enable alt boot check */
+ GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */
+};
+
+/* System Controller Interrupt bits */
+enum {
+ GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
+ GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
+ GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
+ GSC_SC_IRQ_GPIO = 4, /* GPIO change */
+ GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
+ GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
+ GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
+};
+
+/* System Controller WP bits */
+enum {
+ GSC_SC_WP_ALL = 0, /* Write Protect All EEPROM regions */
+ GSC_SC_WP_BOARDINFO = 1, /* Write Protect Board Info region */
+};
+
+/* System Controller Reset Cause */
+enum {
+ GSC_SC_RST_CAUSE_VIN = 0,
+ GSC_SC_RST_CAUSE_PB = 1,
+ GSC_SC_RST_CAUSE_WDT = 2,
+ GSC_SC_RST_CAUSE_CPU = 3,
+ GSC_SC_RST_CAUSE_TEMP_LOCAL = 4,
+ GSC_SC_RST_CAUSE_TEMP_REMOTE = 5,
+ GSC_SC_RST_CAUSE_SLEEP = 6,
+ GSC_SC_RST_CAUSE_BOOT_WDT = 7,
+ GSC_SC_RST_CAUSE_BOOT_WDT_MAN = 8,
+ GSC_SC_RST_CAUSE_SOFT_PWR = 9,
+ GSC_SC_RST_CAUSE_MAX = 10,
+};
+
+#if (IS_ENABLED(CONFIG_DM_I2C))
+
+struct gsc_priv {
+ int gscver;
+ int fwver;
+ int fwcrc;
+ struct udevice *hwmon;
+ struct udevice *rtc;
+};
+
+/*
+ * GSCv2 will fail to ACK an I2C transaction if it is busy, which can occur
+ * during its 1HZ timer tick while reading ADC's. When this does occur,
+ * it will never be busy longer than 2 back-to-back transfers so retry 3 times.
+ */
+static int gsc_i2c_read(struct udevice *dev, uint addr, u8 *buf, int len)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+ int retry = (priv->gscver == 3) ? 1 : 3;
+ int n = 0;
+ int ret;
+
+ while (n++ < retry) {
+ ret = dm_i2c_read(dev, addr, buf, len);
+ if (!ret)
+ break;
+ if (ret != -EREMOTEIO)
+ break;
+ mdelay(10);
+ }
+ return ret;
+}
+
+static int gsc_i2c_write(struct udevice *dev, uint addr, const u8 *buf, int len)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+ int retry = (priv->gscver == 3) ? 1 : 3;
+ int n = 0;
+ int ret;
+
+ while (n++ < retry) {
+ ret = dm_i2c_write(dev, addr, buf, len);
+ if (!ret)
+ break;
+ if (ret != -EREMOTEIO)
+ break;
+ mdelay(10);
+ }
+ return ret;
+}
+
+static struct udevice *gsc_get_dev(int busno, int slave)
+{
+ struct udevice *dev, *bus;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
+ if (ret)
+ return NULL;
+ ret = dm_i2c_probe(bus, slave, 0, &dev);
+ if (ret)
+ return NULL;
+
+ return dev;
+}
+
+static int gsc_thermal_get_info(struct udevice *dev, u8 *outreg, int *tmax, bool *enable)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+ int ret;
+ u8 reg;
+
+ if (priv->gscver > 2 && priv->fwver > 52) {
+ ret = gsc_i2c_read(dev, GSC_SC_THERM_PROTECT, ®, 1);
+ if (!ret) {
+ if (outreg)
+ *outreg = reg;
+ if (tmax) {
+ *tmax = ((reg & 0xf8) >> 3) * 2;
+ if (*tmax)
+ *tmax += 70;
+ else
+ *tmax = 120;
+ }
+ if (enable)
+ *enable = reg & 1;
+ }
+ } else {
+ ret = -ENODEV;
+ }
+
+ return ret;
+}
+
+static int gsc_thermal_get_temp(struct udevice *dev)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+ u32 reg, mode, val;
+ const char *label;
+ ofnode node;
+ u8 buf[2];
+
+ ofnode_for_each_subnode(node, dev_read_subnode(dev, "adc")) {
+ if (ofnode_read_u32(node, "reg", ®))
+ reg = -1;
+ if (ofnode_read_u32(node, "gw,mode", &mode))
+ mode = -1;
+ label = ofnode_read_string(node, "label");
+
+ if ((reg == -1) || (mode == -1) || !label)
+ continue;
+
+ if (mode != 0 || strcmp(label, "temp"))
+ continue;
+
+ memset(buf, 0, sizeof(buf));
+ if (!gsc_i2c_read(priv->hwmon, reg, buf, sizeof(buf))) {
+ val = buf[0] | buf[1] << 8;
+ if (val > 0x8000)
+ val -= 0xffff;
+ return val;
+ }
+ }
+
+ return 0;
+}
+
+static void gsc_thermal_info(struct udevice *dev)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+
+ switch (priv->gscver) {
+ case 2:
+ printf("board_temp:%dC ", gsc_thermal_get_temp(dev) / 10);
+ break;
+ case 3:
+ if (priv->fwver > 52) {
+ bool enabled;
+ int tmax;
+
+ if (!gsc_thermal_get_info(dev, NULL, &tmax, &enabled)) {
+ puts("Thermal protection:");
+ if (enabled)
+ printf("enabled at %dC ", tmax);
+ else
+ puts("disabled ");
+ }
+ }
+ break;
+ }
+}
+
+static void gsc_reset_info(struct udevice *dev)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+ static const char * const names[] = {
+ "VIN",
+ "PB",
+ "WDT",
+ "CPU",
+ "TEMP_L",
+ "TEMP_R",
+ "SLEEP",
+ "BOOT_WDT1",
+ "BOOT_WDT2",
+ "SOFT_PWR",
+ };
+ u8 reg;
+
+ /* reset cause */
+ switch (priv->gscver) {
+ case 2:
+ if (!gsc_i2c_read(dev, GSC_SC_STATUS, ®, 1)) {
+ if (reg & BIT(GSC_SC_IRQ_WATCHDOG)) {
+ puts("RST:WDT");
+ reg &= ~BIT(GSC_SC_IRQ_WATCHDOG);
+ gsc_i2c_write(dev, GSC_SC_STATUS, ®, 1);
+ } else {
+ puts("RST:VIN");
+ }
+ printf(" WDT:%sabled ",
+ (reg & BIT(GSC_SC_CTRL1_WDEN)) ? "en" : "dis");
+ }
+ break;
+ case 3:
+ if (priv->fwver > 52 &&
+ !gsc_i2c_read(dev, GSC_SC_RST_CAUSE, ®, 1)) {
+ puts("RST:");
+ if (reg < ARRAY_SIZE(names))
+ printf("%s ", names[reg]);
+ else
+ printf("0x%02x ", reg);
+ }
+ break;
+ }
+}
+
+/* display hardware monitor ADC channels */
+static int gsc_hwmon(struct udevice *dev)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+ u32 reg, mode, val, offset;
+ const char *label;
+ ofnode node;
+ u8 buf[2];
+ u32 r[2];
+ int ret;
+
+ /* iterate over hwmon nodes */
+ ofnode_for_each_subnode(node, dev_read_subnode(dev, "adc")) {
+ if (ofnode_read_u32(node, "reg", ®))
+ reg = -1;
+ if (ofnode_read_u32(node, "gw,mode", &mode))
+ mode = -1;
+ label = ofnode_read_string(node, "label");
+ if ((reg == -1) || (mode == -1) || !label)
+ continue;
+
+ memset(buf, 0, sizeof(buf));
+ ret = gsc_i2c_read(priv->hwmon, reg, buf, sizeof(buf));
+ if (ret) {
+ printf("i2c error: %d\n", ret);
+ continue;
+ }
+ val = buf[0] | buf[1] << 8;
+
+ switch (mode) {
+ case 0: /* temperature (C*10) */
+ if (val > 0x8000)
+ val -= 0xffff;
+ printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
+ break;
+ case 1: /* prescaled voltage */
+ if (val != 0xffff)
+ printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+ break;
+ case 2: /* scaled based on ref volt and resolution */
+ val *= 2500;
+ val /= 1 << 12;
+
+ /* apply pre-scaler voltage divider */
+ if (!ofnode_read_u32_index(node, "gw,voltage-divider-ohms", 0, &r[0]) &&
+ !ofnode_read_u32_index(node, "gw,voltage-divider-ohms", 1, &r[1]) &&
+ r[0] && r[1]) {
+ val *= (r[0] + r[1]);
+ val /= r[1];
+ }
+
+ /* adjust by offset */
+ val += (offset / 1000);
+
+ printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int gsc_banner(struct udevice *dev)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+
+ /* banner */
+ printf("GSCv%d : v%d 0x%04x ", priv->gscver, priv->fwver, priv->fwcrc);
+ gsc_reset_info(dev);
+ gsc_thermal_info(dev);
+ puts("\n");
+
+ /* Display RTC */
+ if (priv->rtc) {
+ u8 buf[4];
+ time_t timestamp;
+ struct rtc_time tm;
+
+ if (!gsc_i2c_read(priv->rtc, 0, buf, 4)) {
+ timestamp = get_unaligned_le32(buf);
+ rtc_to_tm(timestamp, &tm);
+ printf("RTC : %4d-%02d-%02d %2d:%02d:%02d UTC\n",
+ tm.tm_year, tm.tm_mon, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec);
+ }
+ }
+
+ return 0;
+}
+
+static int gsc_probe(struct udevice *dev)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+ u8 buf[32];
+ int ret;
+
+ ret = gsc_i2c_read(dev, 0, buf, sizeof(buf));
+ if (ret)
+ return ret;
+
+ /*
+ * GSC chip version:
+ * GSCv2 has 16 registers (which overlap)
+ * GSCv3 has 32 registers
+ */
+ priv->gscver = memcmp(buf, buf + 16, 16) ? 3 : 2;
+ priv->fwver = buf[GSC_SC_FWVER];
+ priv->fwcrc = buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8;
+ priv->hwmon = gsc_get_dev(GSC_BUSNO, GSC_HWMON_ADDR);
+ if (priv->hwmon)
+ dev_set_priv(priv->hwmon, priv);
+ priv->rtc = gsc_get_dev(GSC_BUSNO, GSC_RTC_ADDR);
+ if (priv->rtc)
+ dev_set_priv(priv->rtc, priv);
+
+#ifdef CONFIG_SPL_BUILD
+ gsc_banner(dev);
+#endif
+
+ return 0;
+};
+
+static const struct udevice_id gsc_ids[] = {
+ { .compatible = "gw,gsc", },
+ { }
+};
+
+U_BOOT_DRIVER(gsc) = {
+ .name = "gsc",
+ .id = UCLASS_MISC,
+ .of_match = gsc_ids,
+ .probe = gsc_probe,
+ .priv_auto = sizeof(struct gsc_priv),
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static int gsc_sleep(struct udevice *dev, unsigned long secs)
+{
+ u8 regs[4];
+ int ret;
+
+ printf("GSC Sleeping for %ld seconds\n", secs);
+ put_unaligned_le32(secs, regs);
+ ret = gsc_i2c_write(dev, GSC_SC_TIME_ADD, regs, sizeof(regs));
+ if (ret)
+ goto err;
+ ret = gsc_i2c_read(dev, GSC_SC_CTRL1, regs, 1);
+ if (ret)
+ goto err;
+ regs[0] |= BIT(GSC_SC_CTRL1_SLEEP_ADD);
+ ret = gsc_i2c_write(dev, GSC_SC_CTRL1, regs, 1);
+ if (ret)
+ goto err;
+ regs[0] &= ~BIT(GSC_SC_CTRL1_SLEEP_ADD);
+ regs[0] |= BIT(GSC_SC_CTRL1_SLEEP_EN) | BIT(GSC_SC_CTRL1_SLEEP_ACTIVATE);
+ ret = gsc_i2c_write(dev, GSC_SC_CTRL1, regs, 1);
+ if (ret)
+ goto err;
+
+ return 0;
+
+err:
+ printf("i2c error: %d\n", ret);
+ return ret;
+}
+
+static int gsc_wd_disable(struct udevice *dev)
+{
+ int ret;
+ u8 reg;
+
+ ret = gsc_i2c_read(dev, GSC_SC_CTRL1, ®, 1);
+ if (ret)
+ goto err;
+ reg |= BIT(GSC_SC_CTRL1_WDDIS);
+ reg &= ~BIT(GSC_SC_CTRL1_BOOT_CHK);
+ ret = gsc_i2c_write(dev, GSC_SC_CTRL1, ®, 1);
+ if (ret)
+ goto err;
+ puts("GSC : boot watchdog disabled\n");
+
+ return 0;
+
+err:
+ puts("i2c error");
+ return ret;
+}
+
+static int gsc_thermal(struct udevice *dev, const char *cmd, const char *val)
+{
+ struct gsc_priv *priv = dev_get_priv(dev);
+ int ret, tmax;
+ bool enabled;
+ u8 reg;
+
+ if (priv->gscver < 3 || priv->fwver < 53)
+ return -EINVAL;
+ ret = gsc_thermal_get_info(dev, ®, &tmax, &enabled);
+ if (ret)
+ return ret;
+ if (cmd && !strcmp(cmd, "enable")) {
+ if (val && *val) {
+ tmax = clamp((int)simple_strtoul(val, NULL, 0), 72, 122);
+ reg &= ~0xf8;
+ reg |= ((tmax - 70) / 2) << 3;
+ }
+ reg |= BIT(0);
+ gsc_i2c_write(dev, GSC_SC_THERM_PROTECT, ®, 1);
+ } else if (cmd && !strcmp(cmd, "disable")) {
+ reg &= ~BIT(0);
+ gsc_i2c_write(dev, GSC_SC_THERM_PROTECT, ®, 1);
+ } else if (cmd) {
+ return -EINVAL;
+ }
+
+ /* show status */
+ gsc_thermal_info(dev);
+ puts("\n");
+
+ return 0;
+}
+
+/* override in board files to display additional board EEPROM info */
+__weak void board_gsc_info(void)
+{
+}
+
+static void gsc_info(struct udevice *dev)
+{
+ gsc_banner(dev);
+ board_gsc_info();
+}
+
+static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *dev;
+ int ret;
+
+ /* get/probe driver */
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev);
+ if (ret)
+ return CMD_RET_USAGE;
+ if (argc < 2) {
+ gsc_info(dev);
+ return CMD_RET_SUCCESS;
+ } else if (strcasecmp(argv[1], "sleep") == 0) {
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ if (!gsc_sleep(dev, dectoul(argv[2], NULL)))
+ return CMD_RET_SUCCESS;
+ } else if (strcasecmp(argv[1], "hwmon") == 0) {
+ if (!gsc_hwmon(dev))
+ return CMD_RET_SUCCESS;
+ } else if (strcasecmp(argv[1], "wd-disable") == 0) {
+ if (!gsc_wd_disable(dev))
+ return CMD_RET_SUCCESS;
+ } else if (strcasecmp(argv[1], "thermal") == 0) {
+ char *cmd, *val;
+
+ cmd = (argc > 2) ? argv[2] : NULL;
+ val = (argc > 3) ? argv[3] : NULL;
+ if (!gsc_thermal(dev, cmd, val))
+ return CMD_RET_SUCCESS;
+ }
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(gsc, 4, 1, do_gsc, "Gateworks System Controller",
+ "[sleep <secs>]|[hwmon]|[wd-disable][thermal [disable|enable [temp]]]\n");
+
+/* disable boot watchdog - useful for an SPL that wants to use falcon mode */
+int gsc_boot_wd_disable(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ /* get/probe driver */
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev);
+ if (!ret)
+ ret = gsc_wd_disable(dev);
+
+ return ret;
+}
+
+# else
+
+/*
+ * GSCv2 will fail to ACK an I2C transaction if it is busy, which can occur
+ * during its 1HZ timer tick while reading ADC's. When this does occur,
+ * it will never be busy longer than 2 back-to-back transfers so retry 3 times.
+ */
+static int gsc_i2c_read(uint chip, uint addr, u8 *buf, int len)
+{
+ int retry = 3;
+ int n = 0;
+ int ret;
+
+ while (n++ < retry) {
+ ret = i2c_read(chip, addr, 1, buf, len);
+ if (!ret)
+ break;
+ if (ret != -EREMOTEIO)
+ break;
+printf("%s 0x%02x retry %d\n", __func__, addr, n);
+ mdelay(10);
+ }
+ return ret;
+}
+
+static int gsc_i2c_write(uint chip, uint addr, u8 *buf, int len)
+{
+ int retry = 3;
+ int n = 0;
+ int ret;
+
+ while (n++ < retry) {
+ ret = i2c_write(chip, addr, 1, buf, len);
+ if (!ret)
+ break;
+ if (ret != -EREMOTEIO)
+ break;
+printf("%s 0x%02x retry %d\n", __func__, addr, n);
+ mdelay(10);
+ }
+ return ret;
+}
+
+/* disable boot watchdog - useful for an SPL that wants to use falcon mode */
+int gsc_boot_wd_disable(void)
+{
+ u8 buf[32];
+ int ret;
+
+ i2c_set_bus_num(GSC_BUSNO);
+ ret = gsc_i2c_read(GSC_SC_ADDR, 0, buf, sizeof(buf));
+ if (!ret) {
+ buf[GSC_SC_CTRL1] |= BIT(GSC_SC_CTRL1_WDDIS);
+ ret = gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, &buf[GSC_SC_CTRL1], 1);
+ printf("GSCv%d: v%d 0x%04x ",
+ memcmp(buf, buf + 16, 16) ? 3 : 2,
+ buf[GSC_SC_FWVER],
+ buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8);
+ if (buf[GSC_SC_STATUS] & BIT(GSC_SC_IRQ_WATCHDOG)) {
+ puts("RST:WDT ");
+ buf[GSC_SC_STATUS] &= ~BIT(GSC_SC_IRQ_WATCHDOG);
+ gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, &buf[GSC_SC_STATUS], 1);
+ } else {
+ puts("RST:VIN ");
+ }
+ puts("WDT:disabled\n");
+ }
+
+ return ret;
+}
+
+#endif
struct fsb_map_entry fsb_mapping_table[] = {
{ 3, 8 },
{ 4, 8 },
+ { -1, 48 }, /* Reserve 48 words */
{ 5, 8 },
{ 6, 8 },
- { -1, 48 }, /* Reserve 48 words */
{ 8, 4, true },
{ 24, 4, true },
{ 26, 4, true },
{ 1, 8 }, /* LOCK */
{ 2, 8 }, /* ECID */
{ 7, 4, 0, 1 }, /* OTP_UNIQ_ID */
+ { 15, 8 }, /* OEM SRK HASH */
{ 23, 1, 4, 2 }, /* OTFAD */
+ { 25, 8 }, /* Test config2 */
};
static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
return ret;
}
+
+int ahab_release_caam(u32 core_did, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_CAAM_RELEASE_CID;
+ msg.data[0] = core_did;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret, i = 0;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_LOG_CID;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret) {
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ return ret;
+ }
+
+ if (buffer) {
+ buffer[i++] = *(u32 *)&msg; /* Need dump the response header */
+ for (; i < buffer_length && i < msg.size; i++)
+ buffer[i] = msg.data[i - 1];
+ }
+
+ return i;
+}
#define ESM_SFT_RST 0x0c
#define ESM_SFT_RST_KEY 0x0f
+#define ESM_EN 0x08
+#define ESM_EN_KEY 0x0f
#define ESM_STS(i) (0x404 + (i) / 32 * 0x20)
+#define ESM_STS_MASK(i) (1 << ((i) % 32))
#define ESM_PIN_EN_SET_OFFSET(i) (0x414 + (i) / 32 * 0x20)
-#define ESM_PIN_MASK(i) BIT((i) & 0x1f)
+#define ESM_PIN_MASK(i) (1 << ((i) % 32))
+#define ESM_INTR_EN_SET_OFFSET(i) (0x408 + (i) / 32 * 0x20)
+#define ESM_INTR_MASK(i) (1 << ((i) % 32))
+#define ESM_INTR_PRIO_SET_OFFSET(i) (0x410 + (i) / 32 * 0x20)
+#define ESM_INTR_PRIO_MASK(i) (1 << ((i) % 32))
static void esm_pin_enable(void __iomem *base, int pin)
{
+ u32 value;
+
+ value = readl(base + ESM_PIN_EN_SET_OFFSET(pin));
+ value |= ESM_PIN_MASK(pin);
/* Enable event */
- writel(ESM_PIN_MASK(pin), base + ESM_PIN_EN_SET_OFFSET(pin));
+ writel(value, base + ESM_PIN_EN_SET_OFFSET(pin));
+}
+
+static void esm_intr_enable(void __iomem *base, int pin)
+{
+ u32 value;
+
+ value = readl(base + ESM_INTR_EN_SET_OFFSET(pin));
+ value |= ESM_INTR_MASK(pin);
+ /* Enable Interrupt event */
+ writel(value, base + ESM_INTR_EN_SET_OFFSET(pin));
+}
+
+static void esm_intr_prio_set(void __iomem *base, int pin)
+{
+ u32 value;
+
+ value = readl(base + ESM_INTR_PRIO_SET_OFFSET(pin));
+ value |= ESM_INTR_PRIO_MASK(pin);
+ /* Set to priority */
+ writel(value, base + ESM_INTR_PRIO_SET_OFFSET(pin));
}
+static void esm_clear_raw_status(void __iomem *base, int pin)
+{
+ u32 value;
+
+ value = readl(base + ESM_STS(pin));
+ value |= ESM_STS_MASK(pin);
+ /* Clear Event status */
+ writel(value, base + ESM_STS(pin));
+}
/**
* k3_esm_probe: configures ESM based on DT data
*
/* Clear any pending events */
writel(ESM_SFT_RST_KEY, base + ESM_SFT_RST);
- for (i = 0; i < num_pins; i++)
+ for (i = 0; i < num_pins; i++) {
+ esm_intr_prio_set(base, pins[i]);
+ esm_clear_raw_status(base, pins[i]);
esm_pin_enable(base, pins[i]);
+ esm_intr_enable(base, pins[i]);
+ }
+
+ /* Enable ESM */
+ writel(ESM_EN_KEY, base + ESM_EN);
free_pins:
kfree(pins);
#include <dm.h>
#include <misc.h>
#include <tables_csum.h>
-#ifdef CONFIG_GENERATE_ACPI_TABLE
-#include <asm/tables.h>
-#endif
#if defined(CONFIG_GENERATE_ACPI_TABLE) && !defined(CONFIG_SANDBOX)
/*
{ .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
+ { .compatible = "fsl,imx8mp-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imxrt-usdhc", },
{ .compatible = "fsl,esdhc", },
return ret;
}
+ ret = device_probe(dev);
+ if (ret) {
+ debug("Probing %s failed (err=%d)\n", dev->name, ret);
+
+ if (CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ||
+ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) ||
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT))
+ mmc_deinit(mmc);
+
+ return ret;
+ }
+
return 0;
}
/* REN Enable on STRB Line for HS400 */
writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]);
- read_poll_timeout(readl, &phy->emmcphy_status, dllrdy,
- PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
+ read_poll_timeout(readl, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1,
+ 5000, &phy->emmcphy_status);
}
static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
DWCMSHC_EMMC_DLL_START;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
- ret = read_poll_timeout(readl, host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
- val, DLL_LOCK_WO_TMOUT(val), 1, 500);
+ ret = read_poll_timeout(readl, val, DLL_LOCK_WO_TMOUT(val), 1,
+ 500,
+ host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0);
if (ret)
return ret;
mhz = DIV64_U64_ROUND_UP(clock, 1000000);
+ if (mhz > 100 && mhz <= 200)
+ mhz = 200;
+ else if (mhz > 50 && mhz <= 100)
+ mhz = 100;
+ else if (mhz > 25 && mhz <= 50)
+ mhz = 50;
+ else
+ mhz = 25;
+
ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);
if (ret) {
dev_err(dev, "SD_CONFIG_BASECLK failed\n");
ofnode parts, child;
int i = 0;
- if (!master->dev)
+ if (!master->dev && !ofnode_valid(master->flash_node))
return 0;
- parts = ofnode_find_subnode(mtd_get_ofnode(master), "partitions");
+ if (master->dev)
+ parts = ofnode_find_subnode(mtd_get_ofnode(master), "partitions");
+ else
+ parts = ofnode_find_subnode(master->flash_node, "partitions");
+
if (!ofnode_valid(parts) || !ofnode_is_available(parts) ||
!ofnode_device_is_compatible(parts, "fixed-partitions"))
return 0;
return 0;
}
-struct mtd_info *nand_get_mtd(void)
-{
- return mtd;
-}
-
int nand_default_bbt(struct mtd_info *mtd)
{
return 0;
break;
}
+ mtd->flash_node = chip->flash_node;
/* Fill in remaining MTD driver data */
mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
while (len) {
WATCHDOG_RESET();
- if (ctrlc()) {
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) {
addr_known = false;
ret = -EINTR;
goto erase_err;
obj-$(CONFIG_AG7XXX) += ag7xxx.o
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
-obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o
obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o
obj-$(CONFIG_BNXT_ETH) += bnxt/
obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o
-obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
-obj-$(CONFIG_DNET) += dnet.o
-obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
-obj-$(CONFIG_EP93XX) += ep93xx_eth.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-$(CONFIG_FTGMAC100) += ftgmac100.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
-obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_KSZ9477) += ksz9477.o
-obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MVMDIO) += mvmdio.o
obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
-obj-$(CONFIG_NATSEMI) += natsemi.o
obj-$(CONFIG_NETCONSOLE) += netconsole.o
obj-$(CONFIG_NET_OCTEONTX) += octeontx/
obj-$(CONFIG_NET_OCTEONTX2) += octeontx2/
-obj-$(CONFIG_NS8382X) += ns8382x.o
obj-$(CONFIG_OCTEONTX2_CGX_INTF) += octeontx2/cgx_intf.o
obj-$(CONFIG_OCTEONTX_SMI) += octeontx/smi.o
obj-$(CONFIG_PCH_GBE) += pch_gbe.o
obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_TULIP) += dc2114x.o
-obj-$(CONFIG_ULI526X) += uli526x.o
obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/types.h>
-#include <asm/byteorder.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/mii.h>
-#include <asm/io.h>
-#include <asm/arch/armada100.h>
-#include "armada100_fec.h"
-
-#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
-
-#ifdef DEBUG
-static int eth_dump_regs(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- unsigned int i = 0;
-
- printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
- printf("offset: smi, value: 0x%x\n", readl(®s->smi));
- for (i = 0x400; i <= 0x4e4; i += 4)
- printf("offset: 0x%x, value: 0x%x\n",
- i, readl(ARMD1_FEC_BASE + i));
- return 0;
-}
-#endif
-
-static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
-{
- u32 timeout = PHY_WAIT_ITERATIONS;
- u32 reg_val;
-
- while (--timeout) {
- reg_val = readl(reg);
- if (cond && (reg_val & flag))
- break;
- else if (!cond && !(reg_val & flag))
- break;
- udelay(PHY_WAIT_MICRO_SECONDS);
- }
- return !timeout;
-}
-
-static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad,
- int phy_reg)
-{
- u16 value = 0;
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- u32 val;
-
- if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
- val = readl(®s->phyadr);
- value = val & 0x1f;
- return value;
- }
-
- /* check parameters */
- if (phy_addr > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
- __func__, phy_addr);
- return -EINVAL;
- }
- if (phy_reg > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
- __func__, phy_reg);
- return -EINVAL;
- }
-
- /* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
- printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
- return -1;
- }
-
- writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
-
- /* now wait for the data to be valid */
- if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) {
- val = readl(®s->smi);
- printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
- __func__, val);
- return -1;
- }
- val = readl(®s->smi);
- value = val & 0xffff;
-
- return value;
-}
-
-static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad,
- int phy_reg, u16 value)
-{
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
-
- if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
- clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f);
- return 0;
- }
-
- /* check parameters */
- if (phy_addr > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
- return -EINVAL;
- }
- if (phy_reg > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
- return -EINVAL;
- }
-
- /* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
- printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
- return -1;
- }
-
- writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
- ®s->smi);
- return 0;
-}
-
-/*
- * Abort any transmit and receive operations and put DMA
- * in idle state. AT and AR bits are cleared upon entering
- * in IDLE state. So poll those bits to verify operation.
- */
-static void abortdma(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- int delay;
- int maxretries = 40;
- u32 tmp;
-
- while (--maxretries) {
- writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
- udelay(100);
-
- delay = 10;
- while (--delay) {
- tmp = readl(®s->sdma_cmd);
- if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
- break;
- udelay(10);
- }
- if (delay)
- break;
- }
-
- if (!maxretries)
- printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
-}
-
-static inline u32 nibble_swapping_32_bit(u32 x)
-{
- return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
-}
-
-static inline u32 nibble_swapping_16_bit(u32 x)
-{
- return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
-}
-
-static inline u32 flip_4_bits(u32 x)
-{
- return ((x & 0x01) << 3) | ((x & 0x002) << 1)
- | ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
-}
-
-/*
- * This function will calculate the hash function of the address.
- * depends on the hash mode and hash size.
- * Inputs
- * mach - the 2 most significant bytes of the MAC address.
- * macl - the 4 least significant bytes of the MAC address.
- * Outputs
- * return the calculated entry.
- */
-static u32 hash_function(u32 mach, u32 macl)
-{
- u32 hashresult;
- u32 addrh;
- u32 addrl;
- u32 addr0;
- u32 addr1;
- u32 addr2;
- u32 addr3;
- u32 addrhswapped;
- u32 addrlswapped;
-
- addrh = nibble_swapping_16_bit(mach);
- addrl = nibble_swapping_32_bit(macl);
-
- addrhswapped = flip_4_bits(addrh & 0xf)
- + ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
- + ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
- + ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
-
- addrlswapped = flip_4_bits(addrl & 0xf)
- + ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
- + ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
- + ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
- + ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
- + ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
- + ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
- + ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
-
- addrh = addrhswapped;
- addrl = addrlswapped;
-
- addr0 = (addrl >> 2) & 0x03f;
- addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
- addr2 = (addrl >> 15) & 0x1ff;
- addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
-
- hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
- hashresult = hashresult & 0x07ff;
- return hashresult;
-}
-
-/*
- * This function will add an entry to the address table.
- * depends on the hash mode and hash size that was initialized.
- * Inputs
- * mach - the 2 most significant bytes of the MAC address.
- * macl - the 4 least significant bytes of the MAC address.
- * skip - if 1, skip this address.
- * rd - the RD field in the address table.
- * Outputs
- * address table entry is added.
- * 0 if success.
- * -ENOSPC if table full
- */
-static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
- u32 macl, u32 rd, u32 skip, int del)
-{
- struct addr_table_entry_t *entry, *start;
- u32 newhi;
- u32 newlo;
- u32 i;
-
- newlo = (((mach >> 4) & 0xf) << 15)
- | (((mach >> 0) & 0xf) << 11)
- | (((mach >> 12) & 0xf) << 7)
- | (((mach >> 8) & 0xf) << 3)
- | (((macl >> 20) & 0x1) << 31)
- | (((macl >> 16) & 0xf) << 27)
- | (((macl >> 28) & 0xf) << 23)
- | (((macl >> 24) & 0xf) << 19)
- | (skip << HTESKIP) | (rd << HTERDBIT)
- | HTEVALID;
-
- newhi = (((macl >> 4) & 0xf) << 15)
- | (((macl >> 0) & 0xf) << 11)
- | (((macl >> 12) & 0xf) << 7)
- | (((macl >> 8) & 0xf) << 3)
- | (((macl >> 21) & 0x7) << 0);
-
- /*
- * Pick the appropriate table, start scanning for free/reusable
- * entries at the index obtained by hashing the specified MAC address
- */
- start = (struct addr_table_entry_t *)(darmdfec->htpr);
- entry = start + hash_function(mach, macl);
- for (i = 0; i < HOP_NUMBER; i++) {
- if (!(entry->lo & HTEVALID)) {
- break;
- } else {
- /* if same address put in same position */
- if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
- && (entry->hi == newhi))
- break;
- }
- if (entry == start + 0x7ff)
- entry = start;
- else
- entry++;
- }
-
- if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
- (entry->hi != newhi) && del)
- return 0;
-
- if (i == HOP_NUMBER) {
- if (!del) {
- printf("ARMD100 FEC: (%s) table section is full\n",
- __func__);
- return -ENOSPC;
- } else {
- return 0;
- }
- }
-
- /*
- * Update the selected entry
- */
- if (del) {
- entry->hi = 0;
- entry->lo = 0;
- } else {
- entry->hi = newhi;
- entry->lo = newlo;
- }
-
- return 0;
-}
-
-/*
- * Create an addressTable entry from MAC address info
- * found in the specifed net_device struct
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- */
-static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
- u8 *oaddr, u8 *addr)
-{
- u32 mach;
- u32 macl;
-
- /* Delete old entry */
- if (oaddr) {
- mach = (oaddr[0] << 8) | oaddr[1];
- macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
- (oaddr[4] << 8) | oaddr[5];
- add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
- }
-
- /* Add new entry */
- mach = (addr[0] << 8) | addr[1];
- macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
- add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
-}
-
-/* Address Table Initialization */
-static void init_hashtable(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
- writel((u32)darmdfec->htpr, ®s->htpr);
-}
-
-/*
- * This detects PHY chip from address 0-31 by reading PHY status
- * registers. PHY chip can be connected at any of this address.
- */
-static int ethernet_phy_detect(struct eth_device *dev)
-{
- u32 val;
- u16 tmp, mii_status;
- u8 addr;
-
- for (addr = 0; addr < 32; addr++) {
- if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
- /* try next phy */
- continue;
-
- /* invalid MII status. More validation required here... */
- if (mii_status == 0 || mii_status == 0xffff)
- /* try next phy */
- continue;
-
- if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
- /* try next phy */
- continue;
-
- val = tmp << 16;
- if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
- /* try next phy */
- continue;
-
- val |= tmp;
-
- if ((val & 0xfffffff0) != 0)
- return addr;
- }
- return -1;
-}
-
-static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
-{
- struct rx_desc *p_rx_desc;
- int i;
-
- /* initialize the Rx descriptors ring */
- p_rx_desc = darmdfec->p_rxdesc;
- for (i = 0; i < RINGSZ; i++) {
- p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
- p_rx_desc->buf_size = PKTSIZE_ALIGN;
- p_rx_desc->byte_cnt = 0;
- p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
- if (i == (RINGSZ - 1)) {
- p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
- } else {
- p_rx_desc->nxtdesc_p = (struct rx_desc *)
- ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
- p_rx_desc = p_rx_desc->nxtdesc_p;
- }
- }
- darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
-}
-
-static int armdfec_init(struct eth_device *dev, struct bd_info *bd)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- int phy_adr;
- u32 temp;
-
- armdfec_init_rx_desc_ring(darmdfec);
-
- /* Disable interrupts */
- writel(0, ®s->im);
- writel(0, ®s->ic);
- /* Write to ICR to clear interrupts. */
- writel(0, ®s->iwc);
-
- /*
- * Abort any transmit and receive operations and put DMA
- * in idle state.
- */
- abortdma(dev);
-
- /* Initialize address hash table */
- init_hashtable(dev);
-
- /* SDMA configuration */
- writel(SDCR_BSZ8 | /* Burst size = 32 bytes */
- SDCR_RIFB | /* Rx interrupt on frame */
- SDCR_BLMT | /* Little endian transmit */
- SDCR_BLMR | /* Little endian receive */
- SDCR_RC_MAX_RETRANS, /* Max retransmit count */
- ®s->sdma_conf);
- /* Port Configuration */
- writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */
-
- /* Set extended port configuration */
- writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */
- PCXR_DSCP_EN | /* Enable DSCP in IP */
- PCXR_MFL_1536 | /* Set MTU = 1536 */
- PCXR_FLP | /* do not force link pass */
- PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
- ®s->pconf_ext);
-
- update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
-
- /* Update TX and RX queue descriptor register */
- temp = (u32)®s->txcdp[TXQ];
- writel((u32)darmdfec->p_txdesc, temp);
- temp = (u32)®s->rxfdp[RXQ];
- writel((u32)darmdfec->p_rxdesc, temp);
- temp = (u32)®s->rxcdp[RXQ];
- writel((u32)darmdfec->p_rxdesc_curr, temp);
-
- /* Enable Interrupts */
- writel(ALL_INTS, ®s->im);
-
- /* Enable Ethernet Port */
- setbits_le32(®s->pconf, PCR_EN);
-
- /* Enable RX DMA engine */
- setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
-
-#ifdef DEBUG
- eth_dump_regs(dev);
-#endif
-
-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-
-#if defined(CONFIG_PHY_BASE_ADR)
- miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
-#else
- /* Search phy address from range 0-31 */
- phy_adr = ethernet_phy_detect(dev);
- if (phy_adr < 0) {
- printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
- return -1;
- } else {
- debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
- miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
- }
-#endif
-
-#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
- /* Wait up to 5s for the link status */
- for (i = 0; i < 5; i++) {
- u16 phy_adr;
-
- miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
- /* Return if we get link up */
- if (miiphy_link(dev->name, phy_adr))
- return 0;
- udelay(1000000);
- }
-
- printf("ARMD100 FEC: No link on %s\n", dev->name);
- return -1;
-#endif
-#endif
- return 0;
-}
-
-static void armdfec_halt(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
-
- /* Stop RX DMA */
- clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
-
- /*
- * Abort any transmit and receive operations and put DMA
- * in idle state.
- */
- abortdma(dev);
-
- /* Disable interrupts */
- writel(0, ®s->im);
- writel(0, ®s->ic);
- writel(0, ®s->iwc);
-
- /* Disable Port */
- clrbits_le32(®s->pconf, PCR_EN);
-}
-
-static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- struct tx_desc *p_txdesc = darmdfec->p_txdesc;
- void *p = (void *)dataptr;
- int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
- u32 cmd_sts, temp;
-
- /* Copy buffer if it's misaligned */
- if ((u32)dataptr & 0x07) {
- if (datasize > PKTSIZE_ALIGN) {
- printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
- datasize);
- return -1;
- }
- memcpy(darmdfec->p_aligned_txbuf, p, datasize);
- p = darmdfec->p_aligned_txbuf;
- }
-
- p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
- p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
- p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
- p_txdesc->cmd_sts |= TX_EN_INT;
- p_txdesc->buf_ptr = p;
- p_txdesc->byte_cnt = datasize;
-
- /* Apply send command using high priority TX queue */
- temp = (u32)®s->txcdp[TXQ];
- writel((u32)p_txdesc, temp);
- writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd);
-
- /*
- * wait for packet xmit completion
- */
- cmd_sts = readl(&p_txdesc->cmd_sts);
- while (cmd_sts & BUF_OWNED_BY_DMA) {
- /* return fail if error is detected */
- if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
- (TX_ERROR | TX_LAST_DESC)) {
- printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
- return -1;
- }
- cmd_sts = readl(&p_txdesc->cmd_sts);
- if (!(retry--)) {
- printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
- __func__);
- return -1;
- }
- }
-
- return 0;
-}
-
-static int armdfec_recv(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
- u32 cmd_sts;
- u32 timeout = 0;
- u32 temp;
-
- /* wait untill rx packet available or timeout */
- do {
- if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
- timeout++;
- } else {
- debug("ARMD100 FEC: %s time out...\n", __func__);
- return -1;
- }
- } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
-
- if (p_rxdesc_curr->byte_cnt != 0) {
- debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
- "(cmd_sts= %08x)\n", __func__,
- (u32)p_rxdesc_curr->byte_cnt,
- (u32)p_rxdesc_curr->buf_ptr,
- (u32)p_rxdesc_curr->cmd_sts);
- }
-
- /*
- * In case received a packet without first/last bits on
- * OR the error summary bit is on,
- * the packets needs to be dropeed.
- */
- cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
-
- if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
- (RX_FIRST_DESC | RX_LAST_DESC)) {
- printf("ARMD100 FEC: (%s) Dropping packet spread on"
- " multiple descriptors\n", __func__);
- } else if (cmd_sts & RX_ERROR) {
- printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
- __func__);
- } else {
- /* !!! call higher layer processing */
- debug("ARMD100 FEC: (%s) Sending Received packet to"
- " upper layer (net_process_received_packet)\n", __func__);
-
- /*
- * let the upper layer handle the packet, subtract offset
- * as two dummy bytes are added in received buffer see
- * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
- */
- net_process_received_packet(
- p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET,
- (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
- }
- /*
- * free these descriptors and point next in the ring
- */
- p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
- p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
- p_rxdesc_curr->byte_cnt = 0;
-
- temp = (u32)&darmdfec->p_rxdesc_curr;
- writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
-
- return 0;
-}
-
-int armada100_fec_register(unsigned long base_addr)
-{
- struct armdfec_device *darmdfec;
- struct eth_device *dev;
-
- darmdfec = malloc(sizeof(struct armdfec_device));
- if (!darmdfec)
- goto error;
-
- memset(darmdfec, 0, sizeof(struct armdfec_device));
-
- darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
- if (!darmdfec->htpr)
- goto error1;
-
- darmdfec->p_rxdesc = memalign(PKTALIGN,
- ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
-
- if (!darmdfec->p_rxdesc)
- goto error1;
-
- darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
- if (!darmdfec->p_rxbuf)
- goto error1;
-
- darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
- if (!darmdfec->p_aligned_txbuf)
- goto error1;
-
- darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
- if (!darmdfec->p_txdesc)
- goto error1;
-
- dev = &darmdfec->dev;
- /* Assign ARMADA100 Fast Ethernet Controller Base Address */
- darmdfec->regs = (void *)base_addr;
-
- /* must be less than sizeof(dev->name) */
- strcpy(dev->name, "armd-fec0");
-
- dev->init = armdfec_init;
- dev->halt = armdfec_halt;
- dev->send = armdfec_send;
- dev->recv = armdfec_recv;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = smi_reg_read;
- mdiodev->write = smi_reg_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
- return 0;
-
-error1:
- free(darmdfec->p_aligned_txbuf);
- free(darmdfec->p_rxbuf);
- free(darmdfec->p_rxdesc);
- free(darmdfec->htpr);
-error:
- free(darmdfec);
- printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
- return -1;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef __ARMADA100_FEC_H__
-#define __ARMADA100_FEC_H__
-
-#define PORT_NUM 0x0
-
-/* RX & TX descriptor command */
-#define BUF_OWNED_BY_DMA (1<<31)
-
-/* RX descriptor status */
-#define RX_EN_INT (1<<23)
-#define RX_FIRST_DESC (1<<17)
-#define RX_LAST_DESC (1<<16)
-#define RX_ERROR (1<<15)
-
-/* TX descriptor command */
-#define TX_EN_INT (1<<23)
-#define TX_GEN_CRC (1<<22)
-#define TX_ZERO_PADDING (1<<18)
-#define TX_FIRST_DESC (1<<17)
-#define TX_LAST_DESC (1<<16)
-#define TX_ERROR (1<<15)
-
-/* smi register */
-#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */
-#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */
-#define SMI_OP_W (0<<26) /* Write operation */
-#define SMI_OP_R (1<<26) /* Read operation */
-
-#define HASH_ADD 0
-#define HASH_DELETE 1
-#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
-#define HOP_NUMBER 12
-
-#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
-#define PHY_WAIT_MICRO_SECONDS 10
-
-#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
-#define ETH_EXTRA_HEADER (6+6+2+4)
- /* dest+src addr+protocol id+crc */
-#define MAX_PKT_SIZE 1536
-
-
-/* Bit definitions of the SDMA Config Reg */
-#define SDCR_BSZ_OFF 12
-#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF)
-#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF)
-#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF)
-#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF)
-#define SDCR_BLMR (1<<6)
-#define SDCR_BLMT (1<<7)
-#define SDCR_RIFB (1<<9)
-#define SDCR_RC_OFF 2
-#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
-
-/* SDMA_CMD */
-#define SDMA_CMD_AT (1<<31)
-#define SDMA_CMD_TXDL (1<<24)
-#define SDMA_CMD_TXDH (1<<23)
-#define SDMA_CMD_AR (1<<15)
-#define SDMA_CMD_ERD (1<<7)
-
-
-/* Bit definitions of the Port Config Reg */
-#define PCR_HS (1<<12)
-#define PCR_EN (1<<7)
-#define PCR_PM (1<<0)
-
-/* Bit definitions of the Port Config Extend Reg */
-#define PCXR_2BSM (1<<28)
-#define PCXR_DSCP_EN (1<<21)
-#define PCXR_MFL_1518 (0<<14)
-#define PCXR_MFL_1536 (1<<14)
-#define PCXR_MFL_2048 (2<<14)
-#define PCXR_MFL_64K (3<<14)
-#define PCXR_FLP (1<<11)
-#define PCXR_PRIO_TX_OFF 3
-#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF)
-
-/*
- * * Bit definitions of the Interrupt Cause Reg
- * * and Interrupt MASK Reg is the same
- * */
-#define ICR_RXBUF (1<<0)
-#define ICR_TXBUF_H (1<<2)
-#define ICR_TXBUF_L (1<<3)
-#define ICR_TXEND_H (1<<6)
-#define ICR_TXEND_L (1<<7)
-#define ICR_RXERR (1<<8)
-#define ICR_TXERR_H (1<<10)
-#define ICR_TXERR_L (1<<11)
-#define ICR_TX_UDR (1<<13)
-#define ICR_MII_CH (1<<28)
-
-#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
- ICR_TXERR_H | ICR_TXERR_L |\
- ICR_TXEND_H | ICR_TXEND_L |\
- ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
-
-#define PHY_MASK 0x0000001f
-
-#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
- (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
-
-#define RX_BUF_OFFSET 0x2
-#define RXQ 0x0 /* RX Queue 0 */
-#define TXQ 0x1 /* TX Queue 1 */
-
-struct addr_table_entry_t {
- u32 lo;
- u32 hi;
-};
-
-/* Bit fields of a Hash Table Entry */
-enum hash_table_entry {
- HTEVALID = 1,
- HTESKIP = 2,
- HTERD = 4,
- HTERDBIT = 2
-};
-
-struct tx_desc {
- u32 cmd_sts; /* Command/status field */
- u16 reserved;
- u16 byte_cnt; /* buffer byte count */
- u8 *buf_ptr; /* pointer to buffer for this descriptor */
- struct tx_desc *nextdesc_p; /* Pointer to next descriptor */
-};
-
-struct rx_desc {
- u32 cmd_sts; /* Descriptor command status */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u16 buf_size; /* Buffer size */
- u8 *buf_ptr; /* Descriptor buffer pointer */
- struct rx_desc *nxtdesc_p; /* Next descriptor pointer */
-};
-
-/*
- * Armada100 Fast Ethernet controller Registers
- * Refer Datasheet Appendix A.22
- */
-struct armdfec_reg {
- u32 phyadr; /* PHY Address */
- u32 pad1[3];
- u32 smi; /* SMI */
- u32 pad2[0xFB];
- u32 pconf; /* Port configuration */
- u32 pad3;
- u32 pconf_ext; /* Port configuration extend */
- u32 pad4;
- u32 pcmd; /* Port Command */
- u32 pad5;
- u32 pstatus; /* Port Status */
- u32 pad6;
- u32 spar; /* Serial Parameters */
- u32 pad7;
- u32 htpr; /* Hash table pointer */
- u32 pad8;
- u32 fcsal; /* Flow control source address low */
- u32 pad9;
- u32 fcsah; /* Flow control source address high */
- u32 pad10;
- u32 sdma_conf; /* SDMA configuration */
- u32 pad11;
- u32 sdma_cmd; /* SDMA command */
- u32 pad12;
- u32 ic; /* Interrupt cause */
- u32 iwc; /* Interrupt write to clear */
- u32 im; /* Interrupt mask */
- u32 pad13;
- u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code
- Point to Priority 0 Low */
- u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */
- u32 pad14[3];
- struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor
- Pointer */
- u32 pad15[4];
- struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor
- Pointer */
- u32 pad16[0x0C];
- struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor
- Pointer */
-};
-
-struct armdfec_device {
- struct eth_device dev;
- struct armdfec_reg *regs;
- struct tx_desc *p_txdesc;
- struct rx_desc *p_rxdesc;
- struct rx_desc *p_rxdesc_curr;
- u8 *p_rxbuf;
- u8 *p_aligned_txbuf;
- u8 *htpr; /* hash pointer */
-};
-
-#endif /* __ARMADA100_FEC_H__ */
+++ /dev/null
-/*
- * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
- *
- * This program is free software; you can distribute it and/or modify
- * it under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- * This program is distributed in the hope it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
- * USA.
- */
-
-/*
- * ========================================================================
- * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
- *
- * The AX88180 Ethernet controller is a high performance and highly
- * integrated local CPU bus Ethernet controller with embedded 40K bytes
- * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
- * embedded systems.
- * The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet
- * controller that supports both MII and RGMII interfaces and is
- * compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards.
- *
- * Please visit ASIX's web site (http://www.asix.com.tw) for more
- * details.
- *
- * Module Name : ax88180.c
- * Date : 2008-07-07
- * History
- * 09/06/2006 : New release for AX88180 US2 chip.
- * 07/07/2008 : Fix up the coding style and using inline functions
- * instead of macros
- * ========================================================================
- */
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <net.h>
-#include <malloc.h>
-#include <linux/delay.h>
-#include <linux/mii.h>
-#include "ax88180.h"
-
-/*
- * ===========================================================================
- * Local SubProgram Declaration
- * ===========================================================================
- */
-static void ax88180_rx_handler (struct eth_device *dev);
-static int ax88180_phy_initial (struct eth_device *dev);
-static void ax88180_media_config (struct eth_device *dev);
-static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev);
-static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev);
-static unsigned short ax88180_mdio_read (struct eth_device *dev,
- unsigned long regaddr);
-static void ax88180_mdio_write (struct eth_device *dev,
- unsigned long regaddr, unsigned short regdata);
-
-/*
- * ===========================================================================
- * Local SubProgram Bodies
- * ===========================================================================
- */
-static int ax88180_mdio_check_complete (struct eth_device *dev)
-{
- int us_cnt = 10000;
- unsigned short tmpval;
-
- /* MDIO read/write should not take more than 10 ms */
- while (--us_cnt) {
- tmpval = INW (dev, MDIOCTRL);
- if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0))
- break;
- }
-
- return us_cnt;
-}
-
-static unsigned short
-ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long tmpval = 0;
-
- OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
-
- if (ax88180_mdio_check_complete (dev))
- tmpval = INW (dev, MDIODP);
- else
- printf ("Failed to read PHY register!\n");
-
- return (unsigned short)(tmpval & 0xFFFF);
-}
-
-static void
-ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr,
- unsigned short regdata)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
-
- OUTW (dev, regdata, MDIODP);
-
- OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
-
- if (!ax88180_mdio_check_complete (dev))
- printf ("Failed to write PHY register!\n");
-}
-
-static int ax88180_phy_reset (struct eth_device *dev)
-{
- unsigned short delay_cnt = 500;
-
- ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE));
-
- /* Wait for the reset to complete, or time out (500 ms) */
- while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
- udelay(1000);
- if (--delay_cnt == 0) {
- printf ("Failed to reset PHY!\n");
- return -1;
- }
- }
-
- return 0;
-}
-
-static void ax88180_mac_reset (struct eth_device *dev)
-{
- unsigned long tmpval;
- unsigned char i;
-
- struct {
- unsigned short offset, value;
- } program_seq[] = {
- {
- MISC, MISC_NORMAL}, {
- RXINDICATOR, DEFAULT_RXINDICATOR}, {
- TXCMD, DEFAULT_TXCMD}, {
- TXBS, DEFAULT_TXBS}, {
- TXDES0, DEFAULT_TXDES0}, {
- TXDES1, DEFAULT_TXDES1}, {
- TXDES2, DEFAULT_TXDES2}, {
- TXDES3, DEFAULT_TXDES3}, {
- TXCFG, DEFAULT_TXCFG}, {
- MACCFG2, DEFAULT_MACCFG2}, {
- MACCFG3, DEFAULT_MACCFG3}, {
- TXLEN, DEFAULT_TXLEN}, {
- RXBTHD0, DEFAULT_RXBTHD0}, {
- RXBTHD1, DEFAULT_RXBTHD1}, {
- RXFULTHD, DEFAULT_RXFULTHD}, {
- DOGTHD0, DEFAULT_DOGTHD0}, {
- DOGTHD1, DEFAULT_DOGTHD1},};
-
- OUTW (dev, MISC_RESET_MAC, MISC);
- tmpval = INW (dev, MISC);
-
- for (i = 0; i < ARRAY_SIZE(program_seq); i++)
- OUTW (dev, program_seq[i].value, program_seq[i].offset);
-}
-
-static int ax88180_poll_tx_complete (struct eth_device *dev)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long tmpval, txbs_txdp;
- int TimeOutCnt = 10000;
-
- txbs_txdp = 1 << priv->NextTxDesc;
-
- while (TimeOutCnt--) {
-
- tmpval = INW (dev, TXBS);
-
- if ((tmpval & txbs_txdp) == 0)
- break;
-
- udelay(100);
- }
-
- if (TimeOutCnt)
- return 0;
- else
- return -TimeOutCnt;
-}
-
-static void ax88180_rx_handler (struct eth_device *dev)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long data_size;
- unsigned short rxcurt_ptr, rxbound_ptr, next_ptr;
- int i;
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
- unsigned short *rxdata = (unsigned short *)net_rx_packets[0];
-#else
- unsigned long *rxdata = (unsigned long *)net_rx_packets[0];
-#endif
- unsigned short count;
-
- rxcurt_ptr = INW (dev, RXCURT);
- rxbound_ptr = INW (dev, RXBOUND);
- next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
-
- debug ("ax88180: RX original RXBOUND=0x%04x,"
- " RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
-
- while (next_ptr != rxcurt_ptr) {
-
- OUTW (dev, RX_START_READ, RXINDICATOR);
-
- data_size = READ_RXBUF (dev) & 0xFFFF;
-
- if ((data_size == 0) || (data_size > MAX_RX_SIZE)) {
-
- OUTW (dev, RX_STOP_READ, RXINDICATOR);
-
- ax88180_mac_reset (dev);
- printf ("ax88180: Invalid Rx packet length!"
- " (len=0x%04lx)\n", data_size);
-
- debug ("ax88180: RX RXBOUND=0x%04x,"
- "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
- return;
- }
-
- rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1;
- rxbound_ptr &= RX_PAGE_NUM_MASK;
-
- /* Comput access times */
- count = (data_size + priv->PadSize) >> priv->BusWidth;
-
- for (i = 0; i < count; i++) {
- *(rxdata + i) = READ_RXBUF (dev);
- }
-
- OUTW (dev, RX_STOP_READ, RXINDICATOR);
-
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[0], data_size);
-
- OUTW (dev, rxbound_ptr, RXBOUND);
-
- rxcurt_ptr = INW (dev, RXCURT);
- rxbound_ptr = INW (dev, RXBOUND);
- next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
-
- debug ("ax88180: RX updated RXBOUND=0x%04x,"
- "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
- }
-
- return;
-}
-
-static int ax88180_phy_initial (struct eth_device *dev)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long tmp_regval;
- unsigned short phyaddr;
-
- /* Search for first avaliable PHY chipset */
-#ifdef CONFIG_PHY_ADDR
- phyaddr = CONFIG_PHY_ADDR;
-#else
- for (phyaddr = 0; phyaddr < 32; ++phyaddr)
-#endif
- {
- priv->PhyAddr = phyaddr;
- priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
- priv->PhyID1 = ax88180_mdio_read(dev, MII_PHYSID2);
-
- switch (priv->PhyID0) {
- case MARVELL_ALASKA_PHYSID0:
- debug("ax88180: Found Marvell Alaska PHY family."
- " (PHY Addr=0x%x)\n", priv->PhyAddr);
-
- switch (priv->PhyID1) {
- case MARVELL_88E1118_PHYSID1:
- ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 2);
- ax88180_mdio_write(dev, M88E1118_CR,
- M88E1118_CR_DEFAULT);
- ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 3);
- ax88180_mdio_write(dev, M88E1118_LEDCTL,
- M88E1118_LEDCTL_DEFAULT);
- ax88180_mdio_write(dev, M88E1118_LEDMIX,
- M88E1118_LEDMIX_LED050 | M88E1118_LEDMIX_LED150 | 0x15);
- ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 0);
- default: /* Default to 88E1111 Phy */
- tmp_regval = ax88180_mdio_read(dev, M88E1111_EXT_SSR);
- if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE)
- ax88180_mdio_write(dev, M88E1111_EXT_SCR,
- DEFAULT_EXT_SCR);
- }
-
- if (ax88180_phy_reset(dev) < 0)
- return 0;
- ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
-
- return 1;
-
- case CICADA_CIS8201_PHYSID0:
- debug("ax88180: Found CICADA CIS8201 PHY"
- " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
-
- ax88180_mdio_write(dev, CIS_IMR,
- (CIS_INT_ENABLE | LINK_CHANGE_INT));
-
- /* Set CIS_SMI_PRIORITY bit before force the media mode */
- tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS);
- tmp_regval &= ~CIS_SMI_PRIORITY;
- ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval);
-
- return 1;
-
- case 0xffff:
- /* No PHY at this addr */
- break;
-
- default:
- printf("ax88180: Unknown PHY chipset %#x at addr %#x\n",
- priv->PhyID0, priv->PhyAddr);
- break;
- }
- }
-
- printf("ax88180: Unknown PHY chipset!!\n");
- return 0;
-}
-
-static void ax88180_media_config (struct eth_device *dev)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long bmcr_val, bmsr_val;
- unsigned long rxcfg_val, maccfg0_val, maccfg1_val;
- unsigned long RealMediaMode;
- int i;
-
- /* Waiting 2 seconds for PHY link stable */
- for (i = 0; i < 20000; i++) {
- bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
- if (bmsr_val & BMSR_LSTATUS) {
- break;
- }
- udelay(100);
- }
-
- bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
- debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
-
- if (bmsr_val & BMSR_LSTATUS) {
- bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
-
- if (bmcr_val & BMCR_ANENABLE) {
-
- /*
- * Waiting for Auto-negotiation completion, this may
- * take up to 5 seconds.
- */
- debug ("ax88180: Auto-negotiation is "
- "enabled. Waiting for NWay completion..\n");
- for (i = 0; i < 50000; i++) {
- bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
- if (bmsr_val & BMSR_ANEGCOMPLETE) {
- break;
- }
- udelay(100);
- }
- } else
- debug ("ax88180: Auto-negotiation is disabled.\n");
-
- debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n",
- (unsigned int)bmcr_val, (unsigned int)bmsr_val);
-
- /* Get real media mode here */
- switch (priv->PhyID0) {
- case MARVELL_ALASKA_PHYSID0:
- RealMediaMode = get_MarvellPHY_media_mode(dev);
- break;
- case CICADA_CIS8201_PHYSID0:
- RealMediaMode = get_CicadaPHY_media_mode(dev);
- break;
- default:
- RealMediaMode = MEDIA_1000FULL;
- break;
- }
-
- priv->LinkState = INS_LINK_UP;
-
- switch (RealMediaMode) {
- case MEDIA_1000FULL:
- debug ("ax88180: 1000Mbps Full-duplex mode.\n");
- rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
- maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
- maccfg1_val = GIGA_MODE_EN | RXFLOW_EN |
- FULLDUPLEX | DEFAULT_MACCFG1;
- break;
-
- case MEDIA_1000HALF:
- debug ("ax88180: 1000Mbps Half-duplex mode.\n");
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = DEFAULT_MACCFG0;
- maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1;
- break;
-
- case MEDIA_100FULL:
- debug ("ax88180: 100Mbps Full-duplex mode.\n");
- rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
- maccfg0_val = SPEED100 | TXFLOW_ENABLE
- | DEFAULT_MACCFG0;
- maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
- break;
-
- case MEDIA_100HALF:
- debug ("ax88180: 100Mbps Half-duplex mode.\n");
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = SPEED100 | DEFAULT_MACCFG0;
- maccfg1_val = DEFAULT_MACCFG1;
- break;
-
- case MEDIA_10FULL:
- debug ("ax88180: 10Mbps Full-duplex mode.\n");
- rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
- maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
- maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
- break;
-
- case MEDIA_10HALF:
- debug ("ax88180: 10Mbps Half-duplex mode.\n");
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = DEFAULT_MACCFG0;
- maccfg1_val = DEFAULT_MACCFG1;
- break;
- default:
- debug ("ax88180: Unknow media mode.\n");
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = DEFAULT_MACCFG0;
- maccfg1_val = DEFAULT_MACCFG1;
-
- priv->LinkState = INS_LINK_DOWN;
- break;
- }
-
- } else {
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = DEFAULT_MACCFG0;
- maccfg1_val = DEFAULT_MACCFG1;
-
- priv->LinkState = INS_LINK_DOWN;
- }
-
- OUTW (dev, rxcfg_val, RXCFG);
- OUTW (dev, maccfg0_val, MACCFG0);
- OUTW (dev, maccfg1_val, MACCFG1);
-
- return;
-}
-
-static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev)
-{
- unsigned long m88_ssr;
- unsigned long MediaMode;
-
- m88_ssr = ax88180_mdio_read (dev, M88_SSR);
- switch (m88_ssr & SSR_MEDIA_MASK) {
- case SSR_1000FULL:
- MediaMode = MEDIA_1000FULL;
- break;
- case SSR_1000HALF:
- MediaMode = MEDIA_1000HALF;
- break;
- case SSR_100FULL:
- MediaMode = MEDIA_100FULL;
- break;
- case SSR_100HALF:
- MediaMode = MEDIA_100HALF;
- break;
- case SSR_10FULL:
- MediaMode = MEDIA_10FULL;
- break;
- case SSR_10HALF:
- MediaMode = MEDIA_10HALF;
- break;
- default:
- MediaMode = MEDIA_UNKNOWN;
- break;
- }
-
- return MediaMode;
-}
-
-static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev)
-{
- unsigned long tmp_regval;
- unsigned long MediaMode;
-
- tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
- switch (tmp_regval & CIS_MEDIA_MASK) {
- case CIS_1000FULL:
- MediaMode = MEDIA_1000FULL;
- break;
- case CIS_1000HALF:
- MediaMode = MEDIA_1000HALF;
- break;
- case CIS_100FULL:
- MediaMode = MEDIA_100FULL;
- break;
- case CIS_100HALF:
- MediaMode = MEDIA_100HALF;
- break;
- case CIS_10FULL:
- MediaMode = MEDIA_10FULL;
- break;
- case CIS_10HALF:
- MediaMode = MEDIA_10HALF;
- break;
- default:
- MediaMode = MEDIA_UNKNOWN;
- break;
- }
-
- return MediaMode;
-}
-
-static void ax88180_halt (struct eth_device *dev)
-{
- /* Disable AX88180 TX/RX functions */
- OUTW (dev, WAKEMOD, CMD);
-}
-
-static int ax88180_init (struct eth_device *dev, struct bd_info * bd)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned short tmp_regval;
-
- ax88180_mac_reset (dev);
-
- /* Disable interrupt */
- OUTW (dev, CLEAR_IMR, IMR);
-
- /* Disable AX88180 TX/RX functions */
- OUTW (dev, WAKEMOD, CMD);
-
- /* Fill the MAC address */
- tmp_regval =
- dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8);
- OUTW (dev, tmp_regval, MACID0);
-
- tmp_regval =
- dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8);
- OUTW (dev, tmp_regval, MACID1);
-
- tmp_regval =
- dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
- OUTW (dev, tmp_regval, MACID2);
-
- ax88180_media_config (dev);
-
- OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
-
- /* Initial variables here */
- priv->FirstTxDesc = TXDP0;
- priv->NextTxDesc = TXDP0;
-
- /* Check if there is any invalid interrupt status and clear it. */
- OUTW (dev, INW (dev, ISR), ISR);
-
- /* Start AX88180 TX/RX functions */
- OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD);
-
- return 0;
-}
-
-/* Get a data block via Ethernet */
-static int ax88180_recv (struct eth_device *dev)
-{
- unsigned short ISR_Status;
- unsigned short tmp_regval;
-
- /* Read and check interrupt status here. */
- ISR_Status = INW (dev, ISR);
-
- while (ISR_Status) {
- /* Clear the interrupt status */
- OUTW (dev, ISR_Status, ISR);
-
- debug ("\nax88180: The interrupt status = 0x%04x\n",
- ISR_Status);
-
- if (ISR_Status & ISR_PHY) {
- /* Read ISR register once to clear PHY interrupt bit */
- tmp_regval = ax88180_mdio_read (dev, M88_ISR);
- ax88180_media_config (dev);
- }
-
- if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
- ax88180_rx_handler (dev);
- }
-
- /* Read and check interrupt status again */
- ISR_Status = INW (dev, ISR);
- }
-
- return 0;
-}
-
-/* Send a data block via Ethernet. */
-static int ax88180_send(struct eth_device *dev, void *packet, int length)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned short TXDES_addr;
- unsigned short txcmd_txdp, txbs_txdp;
- unsigned short tmp_data;
- int i;
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
- volatile unsigned short *txdata = (volatile unsigned short *)packet;
-#else
- volatile unsigned long *txdata = (volatile unsigned long *)packet;
-#endif
- unsigned short count;
-
- if (priv->LinkState != INS_LINK_UP) {
- return 0;
- }
-
- priv->FirstTxDesc = priv->NextTxDesc;
- txbs_txdp = 1 << priv->FirstTxDesc;
-
- debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc);
-
- txcmd_txdp = priv->FirstTxDesc << 13;
- TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2);
-
- OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD);
-
- /* Comput access times */
- count = (length + priv->PadSize) >> priv->BusWidth;
-
- for (i = 0; i < count; i++) {
- WRITE_TXBUF (dev, *(txdata + i));
- }
-
- OUTW (dev, txcmd_txdp | length, TXCMD);
- OUTW (dev, txbs_txdp, TXBS);
- OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr);
-
- priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK;
-
- /*
- * Check the available transmit descriptor, if we had exhausted all
- * transmit descriptor ,then we have to wait for at least one free
- * descriptor
- */
- txbs_txdp = 1 << priv->NextTxDesc;
- tmp_data = INW (dev, TXBS);
-
- if (tmp_data & txbs_txdp) {
- if (ax88180_poll_tx_complete (dev) < 0) {
- ax88180_mac_reset (dev);
- priv->FirstTxDesc = TXDP0;
- priv->NextTxDesc = TXDP0;
- printf ("ax88180: Transmit time out occurred!\n");
- }
- }
-
- return 0;
-}
-
-static void ax88180_read_mac_addr (struct eth_device *dev)
-{
- unsigned short macid0_val, macid1_val, macid2_val;
- unsigned short tmp_regval;
- unsigned short i;
-
- /* Reload MAC address from EEPROM */
- OUTW (dev, RELOAD_EEPROM, PROMCTRL);
-
- /* Waiting for reload eeprom completion */
- for (i = 0; i < 500; i++) {
- tmp_regval = INW (dev, PROMCTRL);
- if ((tmp_regval & RELOAD_EEPROM) == 0)
- break;
- udelay(1000);
- }
-
- /* Get MAC addresses */
- macid0_val = INW (dev, MACID0);
- macid1_val = INW (dev, MACID1);
- macid2_val = INW (dev, MACID2);
-
- if (((macid0_val | macid1_val | macid2_val) != 0) &&
- ((macid0_val & 0x01) == 0)) {
- dev->enetaddr[0] = (unsigned char)macid0_val;
- dev->enetaddr[1] = (unsigned char)(macid0_val >> 8);
- dev->enetaddr[2] = (unsigned char)macid1_val;
- dev->enetaddr[3] = (unsigned char)(macid1_val >> 8);
- dev->enetaddr[4] = (unsigned char)macid2_val;
- dev->enetaddr[5] = (unsigned char)(macid2_val >> 8);
- }
-}
-
-/* Exported SubProgram Bodies */
-int ax88180_initialize (struct bd_info * bis)
-{
- struct eth_device *dev;
- struct ax88180_private *priv;
-
- dev = (struct eth_device *)malloc (sizeof *dev);
-
- if (NULL == dev)
- return 0;
-
- memset (dev, 0, sizeof *dev);
-
- priv = (struct ax88180_private *)malloc (sizeof (*priv));
-
- if (NULL == priv)
- return 0;
-
- memset (priv, 0, sizeof *priv);
-
- strcpy(dev->name, "ax88180");
- dev->iobase = AX88180_BASE;
- dev->priv = priv;
- dev->init = ax88180_init;
- dev->halt = ax88180_halt;
- dev->send = ax88180_send;
- dev->recv = ax88180_recv;
-
- priv->BusWidth = BUS_WIDTH_32;
- priv->PadSize = 3;
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
- OUTW (dev, (START_BASE >> 8), BASE);
- OUTW (dev, DECODE_EN, DECODE);
-
- priv->BusWidth = BUS_WIDTH_16;
- priv->PadSize = 1;
-#endif
-
- ax88180_mac_reset (dev);
-
- /* Disable interrupt */
- OUTW (dev, CLEAR_IMR, IMR);
-
- /* Disable AX88180 TX/RX functions */
- OUTW (dev, WAKEMOD, CMD);
-
- ax88180_read_mac_addr (dev);
-
- eth_register (dev);
-
- return ax88180_phy_initial (dev);
-
-}
+++ /dev/null
-/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
-/*
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- */
-
-#ifndef _AX88180_H_
-#define _AX88180_H_
-
-#include <asm/io.h>
-#include <asm/types.h>
-#include <config.h>
-
-typedef enum _ax88180_link_state {
- INS_LINK_DOWN,
- INS_LINK_UP,
- INS_LINK_UNKNOWN
-} ax88180_link_state;
-
-struct ax88180_private {
- unsigned char BusWidth;
- unsigned char PadSize;
- unsigned short PhyAddr;
- unsigned short PhyID0;
- unsigned short PhyID1;
- unsigned short FirstTxDesc;
- unsigned short NextTxDesc;
- ax88180_link_state LinkState;
-};
-
-#define BUS_WIDTH_16 1
-#define BUS_WIDTH_32 2
-
-#define ENABLE_JUMBO 1
-#define DISABLE_JUMBO 0
-
-#define ENABLE_BURST 1
-#define DISABLE_BURST 0
-
-#define NORMAL_RX_MODE 0
-#define RX_LOOPBACK_MODE 1
-#define RX_INIFINIT_LOOP_MODE 2
-#define TX_INIFINIT_LOOP_MODE 3
-
-#define DEFAULT_ETH_MTU 1500
-
-/* Jumbo packet size 4086 bytes included 4 bytes CRC*/
-#define MAX_JUMBO_MTU 4072
-
-/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
-#define MAX_TX_JUMBO_SIZE 4086
-
-/* Max Rx Jumbo size is 15K Bytes */
-#define MAX_RX_SIZE 0x3C00
-
-#define MARVELL_ALASKA_PHYSID0 0x141
-#define MARVELL_88E1118_PHYSID1 0xE40
-
-#define CICADA_CIS8201_PHYSID0 0x000F
-
-#define MEDIA_AUTO 0
-#define MEDIA_1000FULL 1
-#define MEDIA_1000HALF 2
-#define MEDIA_100FULL 3
-#define MEDIA_100HALF 4
-#define MEDIA_10FULL 5
-#define MEDIA_10HALF 6
-#define MEDIA_UNKNOWN 7
-
-#define AUTO_MEDIA 0
-#define FORCE_MEDIA 1
-
-#define TXDP_MASK 3
-#define TXDP0 0
-#define TXDP1 1
-#define TXDP2 2
-#define TXDP3 3
-
-#define CMD_MAP_SIZE 0x100
-
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
- #define AX88180_MEMORY_SIZE 0x00004000
- #define START_BASE 0x1000
-
- #define RX_BUF_SIZE 0x1000
- #define TX_BUF_SIZE 0x0F00
-
- #define TX_BASE START_BASE
- #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
- #define RX_BASE (CMD_BASE + CMD_MAP_SIZE)
-#else
- #define AX88180_MEMORY_SIZE 0x00010000
-
- #define RX_BUF_SIZE 0x8000
- #define TX_BUF_SIZE 0x7C00
-
- #define RX_BASE 0x0000
- #define TX_BASE (RX_BASE + RX_BUF_SIZE)
- #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
-#endif
-
-/* AX88180 Memory Mapping Definition */
-#define RXBUFFER_START RX_BASE
- #define RX_PACKET_LEN_OFFSET 0
- #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
-#define TXBUFFER_START TX_BASE
-
-/* AX88180 MAC Register Definition */
-#define DECODE (0)
- #define DECODE_EN 0x00000001
-#define BASE (6)
-#define CMD (CMD_BASE + 0x0000)
- #define WAKEMOD 0x00000001
- #define TXEN 0x00000100
- #define RXEN 0x00000200
- #define DEFAULT_CMD WAKEMOD
-#define IMR (CMD_BASE + 0x0004)
- #define IMR_RXBUFFOVR 0x00000001
- #define IMR_WATCHDOG 0x00000002
- #define IMR_TX 0x00000008
- #define IMR_RX 0x00000010
- #define IMR_PHY 0x00000020
- #define CLEAR_IMR 0x00000000
- #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\
- IMR_RXBUFFOVR | IMR_WATCHDOG)
-#define ISR (CMD_BASE + 0x0008)
- #define ISR_RXBUFFOVR 0x00000001
- #define ISR_WATCHDOG 0x00000002
- #define ISR_TX 0x00000008
- #define ISR_RX 0x00000010
- #define ISR_PHY 0x00000020
-#define TXCFG (CMD_BASE + 0x0010)
- #define AUTOPAD_CRC 0x00000050
- #define DEFAULT_TXCFG AUTOPAD_CRC
-#define TXCMD (CMD_BASE + 0x0014)
- #define TXCMD_TXDP_MASK 0x00006000
- #define TXCMD_TXDP0 0x00000000
- #define TXCMD_TXDP1 0x00002000
- #define TXCMD_TXDP2 0x00004000
- #define TXCMD_TXDP3 0x00006000
- #define TX_START_WRITE 0x00008000
- #define TX_STOP_WRITE 0x00000000
- #define DEFAULT_TXCMD 0x00000000
-#define TXBS (CMD_BASE + 0x0018)
- #define TXDP0_USED 0x00000001
- #define TXDP1_USED 0x00000002
- #define TXDP2_USED 0x00000004
- #define TXDP3_USED 0x00000008
- #define DEFAULT_TXBS 0x00000000
-#define TXDES0 (CMD_BASE + 0x0020)
- #define TXDPx_ENABLE 0x00008000
- #define TXDPx_LEN_MASK 0x00001FFF
- #define DEFAULT_TXDES0 0x00000000
-#define TXDES1 (CMD_BASE + 0x0024)
- #define TXDPx_ENABLE 0x00008000
- #define TXDPx_LEN_MASK 0x00001FFF
- #define DEFAULT_TXDES1 0x00000000
-#define TXDES2 (CMD_BASE + 0x0028)
- #define TXDPx_ENABLE 0x00008000
- #define TXDPx_LEN_MASK 0x00001FFF
- #define DEFAULT_TXDES2 0x00000000
-#define TXDES3 (CMD_BASE + 0x002C)
- #define TXDPx_ENABLE 0x00008000
- #define TXDPx_LEN_MASK 0x00001FFF
- #define DEFAULT_TXDES3 0x00000000
-#define RXCFG (CMD_BASE + 0x0030)
- #define RXBUFF_PROTECT 0x00000001
- #define RXTCPCRC_CHECK 0x00000010
- #define RXFLOW_ENABLE 0x00000100
- #define DEFAULT_RXCFG RXBUFF_PROTECT
-#define RXCURT (CMD_BASE + 0x0034)
- #define DEFAULT_RXCURT 0x00000000
-#define RXBOUND (CMD_BASE + 0x0038)
- #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */
-#define MACCFG0 (CMD_BASE + 0x0040)
- #define MACCFG0_BIT3_0 0x00000007
- #define IPGT_VAL 0x00000150
- #define TXFLOW_ENABLE 0x00001000
- #define SPEED100 0x00008000
- #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0)
-#define MACCFG1 (CMD_BASE + 0x0044)
- #define RGMII_EN 0x00000002
- #define RXFLOW_EN 0x00000020
- #define FULLDUPLEX 0x00000040
- #define MAX_JUMBO_LEN 0x00000780
- #define RXJUMBO_EN 0x00000800
- #define GIGA_MODE_EN 0x00001000
- #define RXCRC_CHECK 0x00002000
- #define RXPAUSE_DA_CHECK 0x00004000
-
- #define JUMBO_LEN_4K 0x00000200
- #define JUMBO_LEN_15K 0x00000780
- #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \
- RGMII_EN)
- #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK)
-#define MACCFG2 (CMD_BASE + 0x0048)
- #define MACCFG2_BIT15_8 0x00000100
- #define JAM_LIMIT_MASK 0x000000FC
- #define DEFAULT_JAM_LIMIT 0x00000064
- #define DEFAULT_MACCFG2 MACCFG2_BIT15_8
-#define MACCFG3 (CMD_BASE + 0x004C)
- #define IPGR2_VAL 0x0000000E
- #define IPGR1_VAL 0x00000600
- #define NOABORT 0x00008000
- #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL)
-#define TXPAUT (CMD_BASE + 0x0054)
- #define DEFAULT_TXPAUT 0x001FE000
-#define RXBTHD0 (CMD_BASE + 0x0058)
- #define DEFAULT_RXBTHD0 0x00000300
-#define RXBTHD1 (CMD_BASE + 0x005C)
- #define DEFAULT_RXBTHD1 0x00000600
-#define RXFULTHD (CMD_BASE + 0x0060)
- #define DEFAULT_RXFULTHD 0x00000100
-#define MISC (CMD_BASE + 0x0068)
- /* Normal operation mode */
- #define MISC_NORMAL 0x00000003
- /* Clear bit 0 to reset MAC */
- #define MISC_RESET_MAC 0x00000002
- /* Clear bit 1 to reset PHY */
- #define MISC_RESET_PHY 0x00000001
- /* Clear bit 0 and 1 to reset MAC and PHY */
- #define MISC_RESET_MAC_PHY 0x00000000
- #define DEFAULT_MISC MISC_NORMAL
-#define MACID0 (CMD_BASE + 0x0070)
-#define MACID1 (CMD_BASE + 0x0074)
-#define MACID2 (CMD_BASE + 0x0078)
-#define TXLEN (CMD_BASE + 0x007C)
- #define DEFAULT_TXLEN 0x000005FC
-#define RXFILTER (CMD_BASE + 0x0080)
- #define RX_RXANY 0x00000001
- #define RX_MULTICAST 0x00000002
- #define RX_UNICAST 0x00000004
- #define RX_BROADCAST 0x00000008
- #define RX_MULTI_HASH 0x00000010
- #define DISABLE_RXFILTER 0x00000000
- #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST)
-#define MDIOCTRL (CMD_BASE + 0x0084)
- #define PHY_ADDR_MASK 0x0000001F
- #define REG_ADDR_MASK 0x00001F00
- #define READ_PHY 0x00004000
- #define WRITE_PHY 0x00008000
-#define MDIODP (CMD_BASE + 0x0088)
-#define GPIOCTRL (CMD_BASE + 0x008C)
-#define RXINDICATOR (CMD_BASE + 0x0090)
- #define RX_START_READ 0x00000001
- #define RX_STOP_READ 0x00000000
- #define DEFAULT_RXINDICATOR RX_STOP_READ
-#define TXST (CMD_BASE + 0x0094)
-#define MDCCLKPAT (CMD_BASE + 0x00A0)
-#define RXIPCRCCNT (CMD_BASE + 0x00A4)
-#define RXCRCCNT (CMD_BASE + 0x00A8)
-#define TXFAILCNT (CMD_BASE + 0x00AC)
-#define PROMDP (CMD_BASE + 0x00B0)
-#define PROMCTRL (CMD_BASE + 0x00B4)
- #define RELOAD_EEPROM 0x00000200
-#define MAXRXLEN (CMD_BASE + 0x00B8)
-#define HASHTAB0 (CMD_BASE + 0x00C0)
-#define HASHTAB1 (CMD_BASE + 0x00C4)
-#define HASHTAB2 (CMD_BASE + 0x00C8)
-#define HASHTAB3 (CMD_BASE + 0x00CC)
-#define DOGTHD0 (CMD_BASE + 0x00E0)
- #define DEFAULT_DOGTHD0 0x0000FFFF
-#define DOGTHD1 (CMD_BASE + 0x00E4)
- #define START_WATCHDOG_TIMER 0x00008000
- #define DEFAULT_DOGTHD1 0x00000FFF
-#define SOFTRST (CMD_BASE + 0x00EC)
- #define SOFTRST_NORMAL 0x00000003
- #define SOFTRST_RESET_MAC 0x00000002
-
-/* Marvell 88E1111 Gigabit PHY Register Definition */
-#define M88_SSR 0x0011
- #define SSR_SPEED_MASK 0xC000
- #define SSR_SPEED_1000 0x8000
- #define SSR_SPEED_100 0x4000
- #define SSR_SPEED_10 0x0000
- #define SSR_DUPLEX 0x2000
- #define SSR_MEDIA_RESOLVED_OK 0x0800
-
- #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX)
- #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX)
- #define SSR_1000HALF SSR_SPEED_1000
- #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX)
- #define SSR_100HALF SSR_SPEED_100
- #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX)
- #define SSR_10HALF SSR_SPEED_10
-#define M88_IER 0x0012
- #define LINK_CHANGE_INT 0x0400
-#define M88_ISR 0x0013
- #define LINK_CHANGE_STATUS 0x0400
-#define M88E1111_EXT_SCR 0x0014
- #define RGMII_RXCLK_DELAY 0x0080
- #define RGMII_TXCLK_DELAY 0x0002
- #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
-#define M88E1111_EXT_SSR 0x001B
- #define HWCFG_MODE_MASK 0x000F
- #define RGMII_COPPER_MODE 0x000B
-
-/* Marvell 88E1118 Gigabit PHY Register Definition */
-#define M88E1118_CR 0x14
- #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
- #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
- #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
- M88E1118_CR_RGMII_RXCLK_DELAY)
-#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
- #define M88E1118_LEDCTL_LED2INT 0x200
- #define M88E1118_LEDCTL_LED2BLNK 0x400
- #define M88E1118_LEDCTL_LED0DUALMODE1 0xc
- #define M88E1118_LEDCTL_LED0DUALMODE2 0xd
- #define M88E1118_LEDCTL_LED0DUALMODE3 0xe
- #define M88E1118_LEDCTL_LED0DUALMODE4 0xf
- #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
- M88E1118_LEDCTL_LED0DUALMODE4)
-
-#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
- #define M88E1118_LEDMIX_LED050 0x4
- #define M88E1118_LEDMIX_LED150 0x8
-
-#define M88E1118_PAGE_SEL 0x16 /* Reg page select */
-
-/* CICADA CIS8201 Gigabit PHY Register Definition */
-#define CIS_IMR 0x0019
- #define CIS_INT_ENABLE 0x8000
- #define CIS_LINK_CHANGE_INT 0x2000
-#define CIS_ISR 0x001A
- #define CIS_INT_PENDING 0x8000
- #define CIS_LINK_CHANGE_STATUS 0x2000
-#define CIS_AUX_CTRL_STATUS 0x001C
- #define CIS_AUTONEG_COMPLETE 0x8000
- #define CIS_SPEED_MASK 0x0018
- #define CIS_SPEED_1000 0x0010
- #define CIS_SPEED_100 0x0008
- #define CIS_SPEED_10 0x0000
- #define CIS_DUPLEX 0x0020
-
- #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX)
- #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX)
- #define CIS_1000HALF CIS_SPEED_1000
- #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX)
- #define CIS_100HALF CIS_SPEED_100
- #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX)
- #define CIS_10HALF CIS_SPEED_10
- #define CIS_SMI_PRIORITY 0x0004
-
-static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
-{
- return le16_to_cpu(readw(addr + (void *)dev->iobase));
-}
-
-/*
- Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
-*/
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
-static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
-{
- writew(cpu_to_le16(command), addr + (void *)dev->iobase);
-}
-
-static inline unsigned short READ_RXBUF (struct eth_device *dev)
-{
- return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase));
-}
-
-static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
-{
- writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase);
-}
-#else
-static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
-{
- writel(cpu_to_le32(command), addr + (void *)dev->iobase);
-}
-
-static inline unsigned long READ_RXBUF (struct eth_device *dev)
-{
- return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase));
-}
-
-static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
-{
- writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase);
-}
-#endif
-
-#endif /* _AX88180_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic CS8900A Ethernet
- *
- * (C) 2009 Ben Warren , biggerbadderben@gmail.com
- * Converted to use CONFIG_NET_MULTI API
- *
- * (C) 2003 Wolfgang Denk, wd@denx.de
- * Extension to synchronize ethaddr environment variable
- * against value in EEPROM
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
- *
- * This program is loaded into SRAM in bootstrap mode, where it waits
- * for commands on UART1 to read and write memory, jump to code etc.
- * A design goal for this program is to be entirely independent of the
- * target board. Anything with a CL-PS7111 or EP7211 should be able to run
- * this code in bootstrap mode. All the board specifics can be handled on
- * the host.
- */
-
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <asm/io.h>
-#include <net.h>
-#include <malloc.h>
-#include <linux/delay.h>
-#include "cs8900.h"
-
-#undef DEBUG
-
-/* packet page register access functions */
-
-#ifdef CONFIG_CS8900_BUS32
-
-#define REG_WRITE(v, a) writel((v),(a))
-#define REG_READ(a) readl((a))
-
-/* we don't need 16 bit initialisation on 32 bit bus */
-#define get_reg_init_bus(r,d) get_reg((r),(d))
-
-#else
-
-#define REG_WRITE(v, a) writew((v),(a))
-#define REG_READ(a) readw((a))
-
-static u16 get_reg_init_bus(struct eth_device *dev, int regno)
-{
- /* force 16 bit busmode */
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
- uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
-
- readb(iob);
- readb(iob + 1);
- readb(iob);
- readb(iob + 1);
- readb(iob);
-
- REG_WRITE(regno, &priv->regs->pptr);
- return REG_READ(&priv->regs->pdata);
-}
-#endif
-
-static u16 get_reg(struct eth_device *dev, int regno)
-{
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
- REG_WRITE(regno, &priv->regs->pptr);
- return REG_READ(&priv->regs->pdata);
-}
-
-
-static void put_reg(struct eth_device *dev, int regno, u16 val)
-{
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
- REG_WRITE(regno, &priv->regs->pptr);
- REG_WRITE(val, &priv->regs->pdata);
-}
-
-static void cs8900_reset(struct eth_device *dev)
-{
- int tmo;
- u16 us;
-
- /* reset NIC */
- put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
-
- /* wait for 200ms */
- udelay(200000);
- /* Wait until the chip is reset */
-
- tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
- while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
- PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
- /*NOP*/;
-}
-
-static void cs8900_reginit(struct eth_device *dev)
-{
- /* receive only error free packets addressed to this card */
- put_reg(dev, PP_RxCTL,
- PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
- /* do not generate any interrupts on receive operations */
- put_reg(dev, PP_RxCFG, 0);
- /* do not generate any interrupts on transmit operations */
- put_reg(dev, PP_TxCFG, 0);
- /* do not generate any interrupts on buffer operations */
- put_reg(dev, PP_BufCFG, 0);
- /* enable transmitter/receiver mode */
- put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
-}
-
-void cs8900_get_enetaddr(struct eth_device *dev)
-{
- int i;
-
- /* verify chip id */
- if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
- return;
- cs8900_reset(dev);
- if ((get_reg(dev, PP_SelfSTAT) &
- (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
- (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
-
- /* Load the MAC from EEPROM */
- for (i = 0; i < 3; i++) {
- u32 Addr;
-
- Addr = get_reg(dev, PP_IA + i * 2);
- dev->enetaddr[i * 2] = Addr & 0xFF;
- dev->enetaddr[i * 2 + 1] = Addr >> 8;
- }
- }
-}
-
-void cs8900_halt(struct eth_device *dev)
-{
- /* disable transmitter/receiver mode */
- put_reg(dev, PP_LineCTL, 0);
-
- /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
- get_reg_init_bus(dev, PP_ChipID);
-}
-
-static int cs8900_init(struct eth_device *dev, struct bd_info * bd)
-{
- uchar *enetaddr = dev->enetaddr;
- u16 id;
-
- /* verify chip id */
- id = get_reg_init_bus(dev, PP_ChipID);
- if (id != 0x630e) {
- printf ("CS8900 Ethernet chip not found: "
- "ID=0x%04x instead 0x%04x\n", id, 0x630e);
- return 1;
- }
-
- cs8900_reset (dev);
- /* set the ethernet address */
- put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
- put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
- put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
-
- cs8900_reginit(dev);
- return 0;
-}
-
-/* Get a data block via Ethernet */
-static int cs8900_recv(struct eth_device *dev)
-{
- int i;
- u16 rxlen;
- u16 *addr;
- u16 status;
-
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
-
- status = get_reg(dev, PP_RER);
-
- if ((status & PP_RER_RxOK) == 0)
- return 0;
-
- status = REG_READ(&priv->regs->rtdata);
- rxlen = REG_READ(&priv->regs->rtdata);
-
- if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
- debug("packet too big!\n");
- for (addr = (u16 *)net_rx_packets[0], i = rxlen >> 1; i > 0; i--)
- *addr++ = REG_READ(&priv->regs->rtdata);
- if (rxlen & 1)
- *addr++ = REG_READ(&priv->regs->rtdata);
-
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[0], rxlen);
- return rxlen;
-}
-
-/* Send a data block via Ethernet. */
-static int cs8900_send(struct eth_device *dev, void *packet, int length)
-{
- volatile u16 *addr;
- int tmo;
- u16 s;
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
-
-retry:
- /* initiate a transmit sequence */
- REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
- REG_WRITE(length, &priv->regs->txlen);
-
- /* Test to see if the chip has allocated memory for the packet */
- if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
- /* Oops... this should not happen! */
- debug("cs: unable to send packet; retrying...\n");
- for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
- get_timer(0) < tmo;)
- /*NOP*/;
- cs8900_reset(dev);
- cs8900_reginit(dev);
- goto retry;
- }
-
- /* Write the contents of the packet */
- /* assume even number of bytes */
- for (addr = packet; length > 0; length -= 2)
- REG_WRITE(*addr++, &priv->regs->rtdata);
-
- /* wait for transfer to succeed */
- tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
- while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
- if (get_timer(0) >= tmo)
- break;
- }
-
- /* nothing */ ;
- if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
- debug("\ntransmission error %#x\n", s);
- }
-
- return 0;
-}
-
-static void cs8900_e2prom_ready(struct eth_device *dev)
-{
- while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
- ;
-}
-
-/***********************************************************/
-/* read a 16-bit word out of the EEPROM */
-/***********************************************************/
-
-int cs8900_e2prom_read(struct eth_device *dev,
- u8 addr, u16 *value)
-{
- cs8900_e2prom_ready(dev);
- put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
- cs8900_e2prom_ready(dev);
- *value = get_reg(dev, PP_EEData);
-
- return 0;
-}
-
-
-/***********************************************************/
-/* write a 16-bit word into the EEPROM */
-/***********************************************************/
-
-int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
-{
- cs8900_e2prom_ready(dev);
- put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
- cs8900_e2prom_ready(dev);
- put_reg(dev, PP_EEData, value);
- put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
- cs8900_e2prom_ready(dev);
- put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
- cs8900_e2prom_ready(dev);
-
- return 0;
-}
-
-int cs8900_initialize(u8 dev_num, int base_addr)
-{
- struct eth_device *dev;
- struct cs8900_priv *priv;
-
- dev = malloc(sizeof(*dev));
- if (!dev) {
- return 0;
- }
- memset(dev, 0, sizeof(*dev));
-
- priv = malloc(sizeof(*priv));
- if (!priv) {
- free(dev);
- return 0;
- }
- memset(priv, 0, sizeof(*priv));
- priv->regs = (struct cs8900_regs *)base_addr;
-
- dev->iobase = base_addr;
- dev->priv = priv;
- dev->init = cs8900_init;
- dev->halt = cs8900_halt;
- dev->send = cs8900_send;
- dev->recv = cs8900_recv;
-
- /* Load MAC address from EEPROM */
- cs8900_get_enetaddr(dev);
-
- sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
-
- eth_register(dev);
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef CS8900_H
-#define CS8900_H
-/*
- * Cirrus Logic CS8900A Ethernet
- *
- * (C) 2009 Ben Warren , biggerbadderben@gmail.com
- * Converted to use CONFIG_NET_MULTI API
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
- *
- * This program is loaded into SRAM in bootstrap mode, where it waits
- * for commands on UART1 to read and write memory, jump to code etc.
- * A design goal for this program is to be entirely independent of the
- * target board. Anything with a CL-PS7111 or EP7211 should be able to run
- * this code in bootstrap mode. All the board specifics can be handled on
- * the host.
- */
-
-#include <asm/types.h>
-#include <config.h>
-
-#define CS8900_DRIVERNAME "CS8900"
-/* although the registers are 16 bit, they are 32-bit aligned on the
- EDB7111. so we have to read them as 32-bit registers and ignore the
- upper 16-bits. i'm not sure if this holds for the EDB7211. */
-
-#ifdef CONFIG_CS8900_BUS16
- /* 16 bit aligned registers, 16 bit wide */
- #define CS8900_REG u16
-#elif defined(CONFIG_CS8900_BUS32)
- /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
- #define CS8900_REG u32
-#else
- #error unknown bussize ...
-#endif
-
-struct cs8900_regs {
- CS8900_REG rtdata;
- CS8900_REG pad0;
- CS8900_REG txcmd;
- CS8900_REG txlen;
- CS8900_REG isq;
- CS8900_REG pptr;
- CS8900_REG pdata;
-};
-
-struct cs8900_priv {
- struct cs8900_regs *regs;
-};
-
-#define ISQ_RxEvent 0x04
-#define ISQ_TxEvent 0x08
-#define ISQ_BufEvent 0x0C
-#define ISQ_RxMissEvent 0x10
-#define ISQ_TxColEvent 0x12
-#define ISQ_EventMask 0x3F
-
-/* packet page register offsets */
-
-/* bus interface registers */
-#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */
-#define PP_ChipRev 0x0002 /* Chip revision, model codes */
-
-#define PP_IntReg 0x0022 /* Interrupt configuration */
-#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */
-#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */
-#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */
-#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */
-
-/* status and control registers */
-
-#define PP_RxCFG 0x0102 /* Receiver configuration */
-#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */
-#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */
-#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */
-#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */
-#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */
-#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */
-#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */
-#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */
-#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */
-
-#define PP_RxCTL 0x0104 /* Receiver control */
-#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */
-#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */
-#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */
-#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */
-#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */
-#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */
-#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */
-#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */
-#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */
-
-#define PP_TxCFG 0x0106 /* Transmit configuration */
-#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */
-#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */
-#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */
-#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */
-#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */
-#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */
-#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */
-
-#define PP_TxCmd 0x0108 /* Transmit command status */
-#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */
-#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */
-#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */
-#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */
-#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */
-#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */
-#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */
-#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */
-
-#define PP_BufCFG 0x010A /* Buffer configuration */
-#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */
-#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */
-#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */
-#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */
-#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */
-#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */
-#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */
-#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */
-#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */
-
-#define PP_LineCTL 0x0112 /* Line control */
-#define PP_LineCTL_Rx 0x0040 /* Enable receiver */
-#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */
-#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */
-#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */
-#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */
-#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */
-#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */
-#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */
-
-#define PP_SelfCTL 0x0114 /* Chip self control */
-#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */
-#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */
-#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */
-#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */
-#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */
-#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */
-#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */
-#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */
-
-#define PP_BusCTL 0x0116 /* Bus control */
-#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */
-#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */
-#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */
-#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */
-#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */
-#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */
-#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */
-#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */
-
-#define PP_TestCTL 0x0118 /* Test control */
-#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */
-#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */
-#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */
-#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */
-#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */
-
-#define PP_ISQ 0x0120 /* Interrupt Status Queue */
-
-#define PP_RER 0x0124 /* Receive event */
-#define PP_RER_IAHash 0x0040 /* Frame hash match */
-#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */
-#define PP_RER_RxOK 0x0100 /* Frame received with no errors */
-#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */
-#define PP_RER_IA 0x0400 /* Frame address matched IA */
-#define PP_RER_Broadcast 0x0800 /* Broadcast frame */
-#define PP_RER_CRC 0x1000 /* Frame had CRC error */
-#define PP_RER_RUNT 0x2000 /* Runt frame */
-#define PP_RER_EXTRA 0x4000 /* Frame was too long */
-
-#define PP_TER 0x0128 /* Transmit event */
-#define PP_TER_CRS 0x0040 /* Carrier lost */
-#define PP_TER_SQE 0x0080 /* Signal Quality Error */
-#define PP_TER_TxOK 0x0100 /* Packet sent without error */
-#define PP_TER_Late 0x0200 /* Out of window */
-#define PP_TER_Jabber 0x0400 /* Stuck transmit? */
-#define PP_TER_NumCollisions 0x7800 /* Number of collisions */
-#define PP_TER_16Collisions 0x8000 /* > 16 collisions */
-
-#define PP_BER 0x012C /* Buffer event */
-#define PP_BER_SWint 0x0040 /* Software interrupt */
-#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */
-#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */
-#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */
-#define PP_BER_RxMiss 0x0400 /* Received frame missed */
-#define PP_BER_Rx128 0x0800 /* 128 bytes received */
-#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */
-
-#define PP_RxMiss 0x0130 /* Receiver miss counter */
-
-#define PP_TxCol 0x0132 /* Transmit collision counter */
-
-#define PP_LineSTAT 0x0134 /* Line status */
-#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */
-#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */
-#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */
-#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */
-#define PP_LineSTAT_CRS 0x4000 /* Frame being received */
-
-#define PP_SelfSTAT 0x0136 /* Chip self status */
-#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */
-#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */
-#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */
-#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */
-#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */
-#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */
-#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */
-
-#define PP_BusSTAT 0x0138 /* Bus status */
-#define PP_BusSTAT_TxBid 0x0080 /* Tx error */
-#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */
-
-#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */
-
-/* initiate transmit registers */
-
-#define PP_TxCommand 0x0144 /* Tx Command */
-#define PP_TxLength 0x0146 /* Tx Length */
-
-
-/* address filter registers */
-
-#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */
-#define PP_IA 0x0158 /* Individual address (MAC) */
-
-/* EEPROM Kram */
-#define SI_BUSY 0x0100
-#define PP_EECMD 0x0040 /* NVR Interface Command register */
-#define PP_EEData 0x0042 /* NVR Interface Data Register */
-#define EEPROM_WRITE_EN 0x00F0
-#define EEPROM_WRITE_DIS 0x0000
-#define EEPROM_WRITE_CMD 0x0100
-#define EEPROM_READ_CMD 0x0200
-#define EEPROM_ERASE_CMD 0x0300
-
-/* Exported functions */
-int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *);
-int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort);
-
-#endif /* CS8900_H */
+++ /dev/null
-/*
- * Dave Ethernet Controller driver
- *
- * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <log.h>
-#include <linux/delay.h>
-
-#ifndef CONFIG_DNET_AUTONEG_TIMEOUT
-#define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */
-#endif
-
-#include <net.h>
-#include <malloc.h>
-#include <linux/mii.h>
-
-#include <miiphy.h>
-#include <asm/io.h>
-#include <asm/unaligned.h>
-
-#include "dnet.h"
-
-struct dnet_device {
- struct dnet_registers *regs;
- const struct device *dev;
- struct eth_device netdev;
- unsigned short phy_addr;
-};
-
-/* get struct dnet_device from given struct netdev */
-#define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev)
-
-/* function for reading internal MAC register */
-u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg)
-{
- u16 data_read;
-
- /* issue a read */
- writel(reg, &dnet->regs->MACREG_ADDR);
-
- /* since a read/write op to the MAC is very slow,
- * we must wait before reading the data */
- udelay(1);
-
- /* read data read from the MAC register */
- data_read = readl(&dnet->regs->MACREG_DATA);
-
- /* all done */
- return data_read;
-}
-
-/* function for writing internal MAC register */
-void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val)
-{
- /* load data to write */
- writel(val, &dnet->regs->MACREG_DATA);
-
- /* issue a write */
- writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR);
-
- /* since a read/write op to the MAC is very slow,
- * we must wait before exiting */
- udelay(1);
-}
-
-static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value)
-{
- u16 tmp;
-
- debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n",
- dnet->phy_addr, reg, value);
-
- while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
- DNET_INTERNAL_GMII_MNG_CMD_FIN))
- ;
-
- /* prepare for a write operation */
- tmp = (1 << 13);
-
- /* only 5 bits allowed for register offset */
- reg &= 0x1f;
-
- /* prepare reg_value for a write */
- tmp |= (dnet->phy_addr << 8);
- tmp |= reg;
-
- /* write data to write first */
- dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
-
- /* write control word */
- dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
-
- while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
- DNET_INTERNAL_GMII_MNG_CMD_FIN))
- ;
-}
-
-static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg)
-{
- u16 value;
-
- while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
- DNET_INTERNAL_GMII_MNG_CMD_FIN))
- ;
-
- /* only 5 bits allowed for register offset*/
- reg &= 0x1f;
-
- /* prepare reg_value for a read */
- value = (dnet->phy_addr << 8);
- value |= reg;
-
- /* write control word */
- dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
-
- /* wait for end of transfer */
- while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
- DNET_INTERNAL_GMII_MNG_CMD_FIN))
- ;
-
- value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG);
-
- debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n",
- dnet->phy_addr, reg, value);
-
- return value;
-}
-
-static int dnet_send(struct eth_device *netdev, void *packet, int length)
-{
- struct dnet_device *dnet = to_dnet(netdev);
- int i, wrsz;
- unsigned int *bufp;
- unsigned int tx_cmd;
-
- debug(DRIVERNAME "[%s] Sending %u bytes\n", __func__, length);
-
- bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC);
- wrsz = (u32)length + 3;
- wrsz += ((u32)packet) & 0x3;
- wrsz >>= 2;
- tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length;
-
- /* check if there is enough room for the current frame */
- if (wrsz < (DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT))) {
- for (i = 0; i < wrsz; i++)
- writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
- /*
- * inform MAC that a packet's written and ready
- * to be shipped out
- */
- writel(tx_cmd, &dnet->regs->TX_LEN_FIFO);
- } else {
- printf(DRIVERNAME "No free space (actual %d, required %d "
- "(words))\n", DNET_FIFO_SIZE -
- readl(&dnet->regs->TX_FIFO_WCNT), wrsz);
- }
-
- /* No one cares anyway */
- return 0;
-}
-
-
-static int dnet_recv(struct eth_device *netdev)
-{
- struct dnet_device *dnet = to_dnet(netdev);
- unsigned int *data_ptr;
- int pkt_len, poll, i;
- u32 cmd_word;
-
- debug("Waiting for pkt (polling)\n");
- poll = 50;
- while ((readl(&dnet->regs->RX_FIFO_WCNT) >> 16) == 0) {
- udelay(10); /* wait 10 usec */
- if (--poll == 0)
- return 0; /* no pkt available */
- }
-
- cmd_word = readl(&dnet->regs->RX_LEN_FIFO);
- pkt_len = cmd_word & 0xFFFF;
-
- debug("Got pkt with size %d bytes\n", pkt_len);
-
- if (cmd_word & 0xDF180000)
- printf("%s packet receive error %x\n", __func__, cmd_word);
-
- data_ptr = (unsigned int *)net_rx_packets[0];
-
- for (i = 0; i < (pkt_len + 3) >> 2; i++)
- *data_ptr++ = readl(&dnet->regs->RX_DATA_FIFO);
-
- /* ok + 5 ?? */
- net_process_received_packet(net_rx_packets[0], pkt_len + 5);
-
- return 0;
-}
-
-static void dnet_set_hwaddr(struct eth_device *netdev)
-{
- struct dnet_device *dnet = to_dnet(netdev);
- u16 tmp;
-
- tmp = get_unaligned_be16(netdev->enetaddr);
- dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
- tmp = get_unaligned_be16(&netdev->enetaddr[2]);
- dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
- tmp = get_unaligned_be16(&netdev->enetaddr[4]);
- dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
-}
-
-static void dnet_phy_reset(struct dnet_device *dnet)
-{
- struct eth_device *netdev = &dnet->netdev;
- int i;
- u16 status, adv;
-
- adv = ADVERTISE_CSMA | ADVERTISE_ALL;
- dnet_mdio_write(dnet, MII_ADVERTISE, adv);
- printf("%s: Starting autonegotiation...\n", netdev->name);
- dnet_mdio_write(dnet, MII_BMCR, (BMCR_ANENABLE
- | BMCR_ANRESTART));
-
- for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
- status = dnet_mdio_read(dnet, MII_BMSR);
- if (status & BMSR_ANEGCOMPLETE)
- break;
- udelay(100);
- }
-
- if (status & BMSR_ANEGCOMPLETE)
- printf("%s: Autonegotiation complete\n", netdev->name);
- else
- printf("%s: Autonegotiation timed out (status=0x%04x)\n",
- netdev->name, status);
-}
-
-static int dnet_phy_init(struct dnet_device *dnet)
-{
- struct eth_device *netdev = &dnet->netdev;
- u16 phy_id, status, adv, lpa;
- int media, speed, duplex;
- int i;
- u32 ctl_reg;
-
- /* Find a PHY */
- for (i = 0; i < 32; i++) {
- dnet->phy_addr = i;
- phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
- if (phy_id != 0xffff) {
- /* ok we found it */
- printf("Found PHY at address %d PHYID (%04x:%04x)\n",
- i, phy_id,
- dnet_mdio_read(dnet, MII_PHYSID2));
- break;
- }
- }
-
- /* Check if the PHY is up to snuff... */
- phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
- if (phy_id == 0xffff) {
- printf("%s: No PHY present\n", netdev->name);
- return -1;
- }
-
- status = dnet_mdio_read(dnet, MII_BMSR);
- if (!(status & BMSR_LSTATUS)) {
- /* Try to re-negotiate if we don't have link already. */
- dnet_phy_reset(dnet);
-
- for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
- status = dnet_mdio_read(dnet, MII_BMSR);
- if (status & BMSR_LSTATUS)
- break;
- udelay(100);
- }
- }
-
- if (!(status & BMSR_LSTATUS)) {
- printf("%s: link down (status: 0x%04x)\n",
- netdev->name, status);
- return -1;
- } else {
- adv = dnet_mdio_read(dnet, MII_ADVERTISE);
- lpa = dnet_mdio_read(dnet, MII_LPA);
- media = mii_nway_result(lpa & adv);
- speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
- ? 1 : 0);
- duplex = (media & ADVERTISE_FULL) ? 1 : 0;
- /* 1000BaseT ethernet is not supported */
- printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
- netdev->name,
- speed ? "100" : "10",
- duplex ? "full" : "half",
- lpa);
-
- ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
-
- if (duplex)
- ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
- else
- ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
-
- dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
-
- return 0;
- }
-}
-
-static int dnet_init(struct eth_device *netdev, struct bd_info *bd)
-{
- struct dnet_device *dnet = to_dnet(netdev);
- u32 config;
-
- /*
- * dnet_halt should have been called at some point before now,
- * so we'll assume the controller is idle.
- */
-
- /* set hardware address */
- dnet_set_hwaddr(netdev);
-
- if (dnet_phy_init(dnet) < 0)
- return -1;
-
- /* flush rx/tx fifos */
- writel(DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
- &dnet->regs->SYS_CTL);
- udelay(1000);
- writel(0, &dnet->regs->SYS_CTL);
-
- config = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
-
- config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
- DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
- DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
- DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
-
- dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, config);
-
- /* Enable TX and RX */
- dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG,
- DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
-
- return 0;
-}
-
-static void dnet_halt(struct eth_device *netdev)
-{
- struct dnet_device *dnet = to_dnet(netdev);
-
- /* Disable TX and RX */
- dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, 0);
-}
-
-int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr)
-{
- struct dnet_device *dnet;
- struct eth_device *netdev;
- unsigned int dev_capa;
-
- dnet = malloc(sizeof(struct dnet_device));
- if (!dnet) {
- printf("Error: Failed to allocate memory for DNET%d\n", id);
- return -1;
- }
- memset(dnet, 0, sizeof(struct dnet_device));
-
- netdev = &dnet->netdev;
-
- dnet->regs = (struct dnet_registers *)regs;
- dnet->phy_addr = phy_addr;
-
- sprintf(netdev->name, "dnet%d", id);
- netdev->init = dnet_init;
- netdev->halt = dnet_halt;
- netdev->send = dnet_send;
- netdev->recv = dnet_recv;
-
- dev_capa = readl(&dnet->regs->VERCAPS) & 0xFFFF;
- debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev->name,
- (dev_capa & DNET_HAS_MDIO) ? "" : "no ",
- (dev_capa & DNET_HAS_IRQ) ? "" : "no ",
- (dev_capa & DNET_HAS_GIGABIT) ? "" : "no ",
- (dev_capa & DNET_HAS_DMA) ? "" : "no ");
-
- eth_register(netdev);
-
- return 0;
-}
+++ /dev/null
-/*
- * Dave Ethernet Controller driver
- *
- * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DRIVERS_DNET_H__
-#define __DRIVERS_DNET_H__
-
-#define DRIVERNAME "dnet"
-
-struct dnet_registers {
- /* ALL DNET FIFO REGISTERS */
- u32 RX_LEN_FIFO;
- u32 RX_DATA_FIFO;
- u32 TX_LEN_FIFO;
- u32 TX_DATA_FIFO;
- u32 pad1[0x3c];
- /* ALL DNET CONTROL/STATUS REGISTERS */
- u32 VERCAPS;
- u32 INTR_SRC;
- u32 INTR_ENB;
- u32 RX_STATUS;
- u32 TX_STATUS;
- u32 RX_FRAMES_CNT;
- u32 TX_FRAMES_CNT;
- u32 RX_FIFO_TH;
- u32 TX_FIFO_TH;
- u32 SYS_CTL;
- u32 PAUSE_TMR;
- u32 RX_FIFO_WCNT;
- u32 TX_FIFO_WCNT;
- u32 pad2[0x33];
- /* ALL DNET MAC REGISTERS */
- u32 MACREG_DATA; /* Mac-Reg Data */
- u32 MACREG_ADDR; /* Mac-Reg Addr */
- u32 pad3[0x3e];
- /* ALL DNET RX STATISTICS COUNTERS */
- u32 RX_PKT_IGNR_CNT;
- u32 RX_LEN_CHK_ERR_CNT;
- u32 RX_LNG_FRM_CNT;
- u32 RX_SHRT_FRM_CNT;
- u32 RX_IPG_VIOL_CNT;
- u32 RX_CRC_ERR_CNT;
- u32 RX_OK_PKT_CNT;
- u32 RX_CTL_FRM_CNT;
- u32 RX_PAUSE_FRM_CNT;
- u32 RX_MULTICAST_CNT;
- u32 RX_BROADCAST_CNT;
- u32 RX_VLAN_TAG_CNT;
- u32 RX_PRE_SHRINK_CNT;
- u32 RX_DRIB_NIB_CNT;
- u32 RX_UNSUP_OPCD_CNT;
- u32 RX_BYTE_CNT;
- u32 pad4[0x30];
- /* DNET TX STATISTICS COUNTERS */
- u32 TX_UNICAST_CNT;
- u32 TX_PAUSE_FRM_CNT;
- u32 TX_MULTICAST_CNT;
- u32 TX_BRDCAST_CNT;
- u32 TX_VLAN_TAG_CNT;
- u32 TX_BAD_FCS_CNT;
- u32 TX_JUMBO_CNT;
- u32 TX_BYTE_CNT;
-};
-
-/* SOME INTERNAL MAC-CORE REGISTER */
-#define DNET_INTERNAL_MODE_REG 0x0
-#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
-#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
-#define DNET_INTERNAL_IGP_REG 0x8
-#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
-#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
-#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
-#define DNET_INTERNAL_TX_RX_STS_REG 0x12
-#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
-#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
-
-#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
-
-#define DNET_INTERNAL_WRITE (1 << 31)
-
-/* MAC-CORE REGISTER FIELDS */
-
-/* MAC-CORE MODE REGISTER FIELDS */
-#define DNET_INTERNAL_MODE_GBITEN (1 << 0)
-#define DNET_INTERNAL_MODE_FCEN (1 << 1)
-#define DNET_INTERNAL_MODE_RXEN (1 << 2)
-#define DNET_INTERNAL_MODE_TXEN (1 << 3)
-
-/* MAC-CORE RXTX CONTROL REGISTER FIELDS */
-#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
-#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
-#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
-#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
-#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
-#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
-#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
-#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
-#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
-
-/* SYSTEM CONTROL REGISTER FIELDS */
-#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
-#define DNET_SYS_CTL_SENDPAUSE (1 << 2)
-#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
-#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
-
-/* TX STATUS REGISTER FIELDS */
-#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
-#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
-
-/* INTERRUPT SOURCE REGISTER FIELDS */
-#define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
-#define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
-#define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
-#define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
-#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
-#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
-#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
-#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
-#define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
-#define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
-#define DNET_INTR_SRC_PHY (1 << 19)
-
-/* INTERRUPT ENABLE REGISTER FIELDS */
-#define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
-#define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
-#define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
-#define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
-#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
-#define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
-#define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
-#define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
-#define DNET_INTR_ENB_RX_ERROR (1 << 11)
-#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
-#define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
-#define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
-#define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
-#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
-
-/*
- * Capabilities. Used by the driver to know the capabilities that
- * the ethernet controller inside the FPGA have.
- */
-
-#define DNET_HAS_MDIO (1 << 0)
-#define DNET_HAS_IRQ (1 << 1)
-#define DNET_HAS_GIGABIT (1 << 2)
-#define DNET_HAS_DMA (1 << 3)
-
-#define DNET_HAS_MII (1 << 4) /* or GMII */
-#define DNET_HAS_RMII (1 << 5) /* or RGMII */
-
-#define DNET_CAPS_MASK 0xFFFF
-
-#define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */
-#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
-#define DNET_FIFO_TX_DATA_AE_TH (384)
-
-#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
-
-#endif
#endif
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX)
{
- .compatible = "fsl,imx-eqos",
+ .compatible = "nxp,imx8mp-dwmac-eqos",
.data = (ulong)&eqos_imx_config
},
#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic EP93xx ethernet MAC / MII driver.
- *
- * Copyright (C) 2010, 2009
- * Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
- * which is
- *
- * (C) Copyright 2002 2003
- * Adam Bezanson, Network Audio Technologies, Inc.
- * <bezanson@netaudiotech.com>
- */
-
-#include <command.h>
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <linux/bug.h>
-#include <linux/types.h>
-#include "ep93xx_eth.h"
-
-#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
-#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
-
-/* ep93xx_miiphy ops forward declarations */
-static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad,
- int reg);
-static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad,
- int reg, u16 value);
-
-#if defined(EP93XX_MAC_DEBUG)
-/**
- * Dump ep93xx_mac values to the terminal.
- */
-static void dump_dev(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_dev()\n");
- printf(" rx_dq.base %p\n", priv->rx_dq.base);
- printf(" rx_dq.current %p\n", priv->rx_dq.current);
- printf(" rx_dq.end %p\n", priv->rx_dq.end);
- printf(" rx_sq.base %p\n", priv->rx_sq.base);
- printf(" rx_sq.current %p\n", priv->rx_sq.current);
- printf(" rx_sq.end %p\n", priv->rx_sq.end);
-
- for (i = 0; i < NUMRXDESC; i++)
- printf(" rx_buffer[%2.d] %p\n", i, net_rx_packets[i]);
-
- printf(" tx_dq.base %p\n", priv->tx_dq.base);
- printf(" tx_dq.current %p\n", priv->tx_dq.current);
- printf(" tx_dq.end %p\n", priv->tx_dq.end);
- printf(" tx_sq.base %p\n", priv->tx_sq.base);
- printf(" tx_sq.current %p\n", priv->tx_sq.current);
- printf(" tx_sq.end %p\n", priv->tx_sq.end);
-}
-
-/**
- * Dump all RX status queue entries to the terminal.
- */
-static void dump_rx_status_queue(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_rx_status_queue()\n");
- printf(" descriptor address word1 word2\n");
- for (i = 0; i < NUMRXDESC; i++) {
- printf(" [ %p ] %08X %08X\n",
- priv->rx_sq.base + i,
- (priv->rx_sq.base + i)->word1,
- (priv->rx_sq.base + i)->word2);
- }
-}
-
-/**
- * Dump all RX descriptor queue entries to the terminal.
- */
-static void dump_rx_descriptor_queue(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_rx_descriptor_queue()\n");
- printf(" descriptor address word1 word2\n");
- for (i = 0; i < NUMRXDESC; i++) {
- printf(" [ %p ] %08X %08X\n",
- priv->rx_dq.base + i,
- (priv->rx_dq.base + i)->word1,
- (priv->rx_dq.base + i)->word2);
- }
-}
-
-/**
- * Dump all TX descriptor queue entries to the terminal.
- */
-static void dump_tx_descriptor_queue(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_tx_descriptor_queue()\n");
- printf(" descriptor address word1 word2\n");
- for (i = 0; i < NUMTXDESC; i++) {
- printf(" [ %p ] %08X %08X\n",
- priv->tx_dq.base + i,
- (priv->tx_dq.base + i)->word1,
- (priv->tx_dq.base + i)->word2);
- }
-}
-
-/**
- * Dump all TX status queue entries to the terminal.
- */
-static void dump_tx_status_queue(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_tx_status_queue()\n");
- printf(" descriptor address word1\n");
- for (i = 0; i < NUMTXDESC; i++) {
- printf(" [ %p ] %08X\n",
- priv->rx_sq.base + i,
- (priv->rx_sq.base + i)->word1);
- }
-}
-#else
-#define dump_dev(x)
-#define dump_rx_descriptor_queue(x)
-#define dump_rx_status_queue(x)
-#define dump_tx_descriptor_queue(x)
-#define dump_tx_status_queue(x)
-#endif /* defined(EP93XX_MAC_DEBUG) */
-
-/**
- * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
- * it's cleared.
- */
-static void ep93xx_mac_reset(struct eth_device *dev)
-{
- struct mac_regs *mac = GET_REGS(dev);
- uint32_t value;
-
- debug("+ep93xx_mac_reset");
-
- value = readl(&mac->selfctl);
- value |= SELFCTL_RESET;
- writel(value, &mac->selfctl);
-
- while (readl(&mac->selfctl) & SELFCTL_RESET)
- ; /* noop */
-
- debug("-ep93xx_mac_reset");
-}
-
-/* Eth device open */
-static int ep93xx_eth_open(struct eth_device *dev, struct bd_info *bd)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- struct mac_regs *mac = GET_REGS(dev);
- uchar *mac_addr = dev->enetaddr;
- int i;
-
- debug("+ep93xx_eth_open");
-
- /* Reset the MAC */
- ep93xx_mac_reset(dev);
-
- /* Reset the descriptor queues' current and end address values */
- priv->tx_dq.current = priv->tx_dq.base;
- priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
-
- priv->tx_sq.current = priv->tx_sq.base;
- priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
-
- priv->rx_dq.current = priv->rx_dq.base;
- priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
-
- priv->rx_sq.current = priv->rx_sq.base;
- priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
-
- /*
- * Set the transmit descriptor and status queues' base address,
- * current address, and length registers. Set the maximum frame
- * length and threshold. Enable the transmit descriptor processor.
- */
- writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
- writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
- writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
-
- writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
- writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
- writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
-
- writel(0x00040000, &mac->txdthrshld);
- writel(0x00040000, &mac->txststhrshld);
-
- writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
- writel(BMCTL_TXEN, &mac->bmctl);
-
- /*
- * Set the receive descriptor and status queues' base address,
- * current address, and length registers. Enable the receive
- * descriptor processor.
- */
- writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
- writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
- writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
-
- writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
- writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
- writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
-
- writel(0x00040000, &mac->rxdthrshld);
-
- writel(BMCTL_RXEN, &mac->bmctl);
-
- writel(0x00040000, &mac->rxststhrshld);
-
- /* Wait until the receive descriptor processor is active */
- while (!(readl(&mac->bmsts) & BMSTS_RXACT))
- ; /* noop */
-
- /*
- * Initialize the RX descriptor queue. Clear the TX descriptor queue.
- * Clear the RX and TX status queues. Enqueue the RX descriptor and
- * status entries to the MAC.
- */
- for (i = 0; i < NUMRXDESC; i++) {
- /* set buffer address */
- (priv->rx_dq.base + i)->word1 = (uint32_t)net_rx_packets[i];
-
- /* set buffer length, clear buffer index and NSOF */
- (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
- }
-
- memset(priv->tx_dq.base, 0,
- (sizeof(struct tx_descriptor) * NUMTXDESC));
- memset(priv->rx_sq.base, 0,
- (sizeof(struct rx_status) * NUMRXDESC));
- memset(priv->tx_sq.base, 0,
- (sizeof(struct tx_status) * NUMTXDESC));
-
- writel(NUMRXDESC, &mac->rxdqenq);
- writel(NUMRXDESC, &mac->rxstsqenq);
-
- /* Set the primary MAC address */
- writel(AFP_IAPRIMARY, &mac->afp);
- writel(mac_addr[0] | (mac_addr[1] << 8) |
- (mac_addr[2] << 16) | (mac_addr[3] << 24),
- &mac->indad);
- writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
-
- /* Turn on RX and TX */
- writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
- RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
- writel(TXCTL_STXON, &mac->txctl);
-
- /* Dump data structures if we're debugging */
- dump_dev(dev);
- dump_rx_descriptor_queue(dev);
- dump_rx_status_queue(dev);
- dump_tx_descriptor_queue(dev);
- dump_tx_status_queue(dev);
-
- debug("-ep93xx_eth_open");
-
- return 1;
-}
-
-/**
- * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
- * registers.
- */
-static void ep93xx_eth_close(struct eth_device *dev)
-{
- struct mac_regs *mac = GET_REGS(dev);
-
- debug("+ep93xx_eth_close");
-
- writel(0x00000000, &mac->rxctl);
- writel(0x00000000, &mac->txctl);
-
- debug("-ep93xx_eth_close");
-}
-
-/**
- * Copy a frame of data from the MAC into the protocol layer for further
- * processing.
- */
-static int ep93xx_eth_rcv_packet(struct eth_device *dev)
-{
- struct mac_regs *mac = GET_REGS(dev);
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int len = -1;
-
- debug("+ep93xx_eth_rcv_packet");
-
- if (RX_STATUS_RFP(priv->rx_sq.current)) {
- if (RX_STATUS_RWE(priv->rx_sq.current)) {
- /*
- * We have a good frame. Extract the frame's length
- * from the current rx_status_queue entry, and copy
- * the frame's data into net_rx_packets[] of the
- * protocol stack. We track the total number of
- * bytes in the frame (nbytes_frame) which will be
- * used when we pass the data off to the protocol
- * layer via net_process_received_packet().
- */
- len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
-
- net_process_received_packet(
- (uchar *)priv->rx_dq.current->word1, len);
-
- debug("reporting %d bytes...\n", len);
- } else {
- /* Do we have an erroneous packet? */
- pr_err("packet rx error, status %08X %08X",
- priv->rx_sq.current->word1,
- priv->rx_sq.current->word2);
- dump_rx_descriptor_queue(dev);
- dump_rx_status_queue(dev);
- }
-
- /*
- * Clear the associated status queue entry, and
- * increment our current pointers to the next RX
- * descriptor and status queue entries (making sure
- * we wrap properly).
- */
- memset((void *)priv->rx_sq.current, 0,
- sizeof(struct rx_status));
-
- priv->rx_sq.current++;
- if (priv->rx_sq.current >= priv->rx_sq.end)
- priv->rx_sq.current = priv->rx_sq.base;
-
- priv->rx_dq.current++;
- if (priv->rx_dq.current >= priv->rx_dq.end)
- priv->rx_dq.current = priv->rx_dq.base;
-
- /*
- * Finally, return the RX descriptor and status entries
- * back to the MAC engine, and loop again, checking for
- * more descriptors to process.
- */
- writel(1, &mac->rxdqenq);
- writel(1, &mac->rxstsqenq);
- } else {
- len = 0;
- }
-
- debug("-ep93xx_eth_rcv_packet %d", len);
- return len;
-}
-
-/**
- * Send a block of data via ethernet.
- */
-static int ep93xx_eth_send_packet(struct eth_device *dev,
- void * const packet, int const length)
-{
- struct mac_regs *mac = GET_REGS(dev);
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int ret = -1;
-
- debug("+ep93xx_eth_send_packet");
-
- /* Parameter check */
- BUG_ON(packet == NULL);
-
- /*
- * Initialize the TX descriptor queue with the new packet's info.
- * Clear the associated status queue entry. Enqueue the packet
- * to the MAC for transmission.
- */
-
- /* set buffer address */
- priv->tx_dq.current->word1 = (uint32_t)packet;
-
- /* set buffer length and EOF bit */
- priv->tx_dq.current->word2 = length | TX_DESC_EOF;
-
- /* clear tx status */
- priv->tx_sq.current->word1 = 0;
-
- /* enqueue the TX descriptor */
- writel(1, &mac->txdqenq);
-
- /* wait for the frame to become processed */
- while (!TX_STATUS_TXFP(priv->tx_sq.current))
- ; /* noop */
-
- if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
- pr_err("packet tx error, status %08X",
- priv->tx_sq.current->word1);
- dump_tx_descriptor_queue(dev);
- dump_tx_status_queue(dev);
-
- /* TODO: Add better error handling? */
- goto eth_send_out;
- }
-
- ret = 0;
- /* Fall through */
-
-eth_send_out:
- debug("-ep93xx_eth_send_packet %d", ret);
- return ret;
-}
-
-#if defined(CONFIG_MII)
-int ep93xx_miiphy_initialize(struct bd_info * const bd)
-{
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
- mdiodev->read = ep93xx_miiphy_read;
- mdiodev->write = ep93xx_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
- return 0;
-}
-#endif
-
-/**
- * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
- * allocated, if necessary, for the TX and RX descriptor and status queues,
- * as well as for received packets. The EP93XX MAC hardware is initialized.
- * Transmit and receive operations are enabled.
- */
-int ep93xx_eth_initialize(u8 dev_num, int base_addr)
-{
- int ret = -1;
- struct eth_device *dev;
- struct ep93xx_priv *priv;
-
- debug("+ep93xx_eth_initialize");
-
- priv = malloc(sizeof(*priv));
- if (!priv) {
- pr_err("malloc() failed");
- goto eth_init_failed_0;
- }
- memset(priv, 0, sizeof(*priv));
-
- priv->regs = (struct mac_regs *)base_addr;
-
- priv->tx_dq.base = calloc(NUMTXDESC,
- sizeof(struct tx_descriptor));
- if (priv->tx_dq.base == NULL) {
- pr_err("calloc() failed");
- goto eth_init_failed_1;
- }
-
- priv->tx_sq.base = calloc(NUMTXDESC,
- sizeof(struct tx_status));
- if (priv->tx_sq.base == NULL) {
- pr_err("calloc() failed");
- goto eth_init_failed_2;
- }
-
- priv->rx_dq.base = calloc(NUMRXDESC,
- sizeof(struct rx_descriptor));
- if (priv->rx_dq.base == NULL) {
- pr_err("calloc() failed");
- goto eth_init_failed_3;
- }
-
- priv->rx_sq.base = calloc(NUMRXDESC,
- sizeof(struct rx_status));
- if (priv->rx_sq.base == NULL) {
- pr_err("calloc() failed");
- goto eth_init_failed_4;
- }
-
- dev = malloc(sizeof *dev);
- if (dev == NULL) {
- pr_err("malloc() failed");
- goto eth_init_failed_5;
- }
- memset(dev, 0, sizeof *dev);
-
- dev->iobase = base_addr;
- dev->priv = priv;
- dev->init = ep93xx_eth_open;
- dev->halt = ep93xx_eth_close;
- dev->send = ep93xx_eth_send_packet;
- dev->recv = ep93xx_eth_rcv_packet;
-
- sprintf(dev->name, "ep93xx_eth-%hu", dev_num);
-
- eth_register(dev);
-
- /* Done! */
- ret = 1;
- goto eth_init_done;
-
-eth_init_failed_5:
- free(priv->rx_sq.base);
- /* Fall through */
-
-eth_init_failed_4:
- free(priv->rx_dq.base);
- /* Fall through */
-
-eth_init_failed_3:
- free(priv->tx_sq.base);
- /* Fall through */
-
-eth_init_failed_2:
- free(priv->tx_dq.base);
- /* Fall through */
-
-eth_init_failed_1:
- free(priv);
- /* Fall through */
-
-eth_init_failed_0:
- /* Fall through */
-
-eth_init_done:
- debug("-ep93xx_eth_initialize %d", ret);
- return ret;
-}
-
-#if defined(CONFIG_MII)
-
-/**
- * Maximum MII address we support
- */
-#define MII_ADDRESS_MAX 31
-
-/**
- * Maximum MII register address we support
- */
-#define MII_REGISTER_MAX 31
-
-/**
- * Read a 16-bit value from an MII register.
- */
-static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad,
- int reg)
-{
- unsigned short value = 0;
- struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
- int ret = -1;
- uint32_t self_ctl;
-
- debug("+ep93xx_miiphy_read");
-
- /* Parameter checks */
- BUG_ON(bus->name == NULL);
- BUG_ON(addr > MII_ADDRESS_MAX);
- BUG_ON(reg > MII_REGISTER_MAX);
-
- /*
- * Save the current SelfCTL register value. Set MAC to suppress
- * preamble bits. Wait for any previous MII command to complete
- * before issuing the new command.
- */
- self_ctl = readl(&mac->selfctl);
-#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
- writel(self_ctl & ~(1 << 8), &mac->selfctl);
-#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
-
- while (readl(&mac->miists) & MIISTS_BUSY)
- ; /* noop */
-
- /*
- * Issue the MII 'read' command. Wait for the command to complete.
- * Read the MII data value.
- */
- writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
- &mac->miicmd);
- while (readl(&mac->miists) & MIISTS_BUSY)
- ; /* noop */
-
- value = (unsigned short)readl(&mac->miidata);
-
- /* Restore the saved SelfCTL value and return. */
- writel(self_ctl, &mac->selfctl);
-
- ret = 0;
- /* Fall through */
-
- debug("-ep93xx_miiphy_read");
- if (ret < 0)
- return ret;
- return value;
-}
-
-/**
- * Write a 16-bit value to an MII register.
- */
-static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad,
- int reg, u16 value)
-{
- struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
- int ret = -1;
- uint32_t self_ctl;
-
- debug("+ep93xx_miiphy_write");
-
- /* Parameter checks */
- BUG_ON(bus->name == NULL);
- BUG_ON(addr > MII_ADDRESS_MAX);
- BUG_ON(reg > MII_REGISTER_MAX);
-
- /*
- * Save the current SelfCTL register value. Set MAC to suppress
- * preamble bits. Wait for any previous MII command to complete
- * before issuing the new command.
- */
- self_ctl = readl(&mac->selfctl);
-#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
- writel(self_ctl & ~(1 << 8), &mac->selfctl);
-#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
-
- while (readl(&mac->miists) & MIISTS_BUSY)
- ; /* noop */
-
- /* Issue the MII 'write' command. Wait for the command to complete. */
- writel((uint32_t)value, &mac->miidata);
- writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
- &mac->miicmd);
- while (readl(&mac->miists) & MIISTS_BUSY)
- ; /* noop */
-
- /* Restore the saved SelfCTL value and return. */
- writel(self_ctl, &mac->selfctl);
-
- ret = 0;
- /* Fall through */
-
- debug("-ep93xx_miiphy_write");
- return ret;
-}
-#endif /* defined(CONFIG_MII) */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- */
-
-#ifndef _EP93XX_ETH_H
-#define _EP93XX_ETH_H
-
-#include <net.h>
-
-/**
- * #define this to dump device status and queue info during initialization and
- * following errors.
- */
-#undef EP93XX_MAC_DEBUG
-
-/**
- * Number of descriptor and status entries in our RX queues.
- * It must be power of 2 !
- */
-#define NUMRXDESC PKTBUFSRX
-
-/**
- * Number of descriptor and status entries in our TX queues.
- */
-#define NUMTXDESC 1
-
-/**
- * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
- */
-#define TXSTARTMAX 944
-
-/**
- * Receive descriptor queue entry
- */
-struct rx_descriptor {
- uint32_t word1;
- uint32_t word2;
-};
-
-/**
- * Receive status queue entry
- */
-struct rx_status {
- uint32_t word1;
- uint32_t word2;
-};
-
-#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
-#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
-#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
-
-/**
- * Transmit descriptor queue entry
- */
-struct tx_descriptor {
- uint32_t word1;
- uint32_t word2;
-};
-
-#define TX_DESC_EOF (1 << 31)
-
-/**
- * Transmit status queue entry
- */
-struct tx_status {
- uint32_t word1;
-};
-
-#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
-#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
-
-/**
- * Transmit descriptor queue
- */
-struct tx_descriptor_queue {
- struct tx_descriptor *base;
- struct tx_descriptor *current;
- struct tx_descriptor *end;
-};
-
-/**
- * Transmit status queue
- */
-struct tx_status_queue {
- struct tx_status *base;
- volatile struct tx_status *current;
- struct tx_status *end;
-};
-
-/**
- * Receive descriptor queue
- */
-struct rx_descriptor_queue {
- struct rx_descriptor *base;
- struct rx_descriptor *current;
- struct rx_descriptor *end;
-};
-
-/**
- * Receive status queue
- */
-struct rx_status_queue {
- struct rx_status *base;
- volatile struct rx_status *current;
- struct rx_status *end;
-};
-
-/**
- * EP93xx MAC private data structure
- */
-struct ep93xx_priv {
- struct rx_descriptor_queue rx_dq;
- struct rx_status_queue rx_sq;
- void *rx_buffer[NUMRXDESC];
-
- struct tx_descriptor_queue tx_dq;
- struct tx_status_queue tx_sq;
-
- struct mac_regs *regs;
-};
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Faraday 10/100Mbps Ethernet Controller
- *
- * (C) Copyright 2013 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/cache.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <linux/dma-mapping.h>
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-#include "ftmac110.h"
-
-#define CFG_RXDES_NUM 8
-#define CFG_TXDES_NUM 2
-#define CFG_XBUF_SIZE 1536
-
-#define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
-#define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
-#define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
-
-/*
- * FTMAC110 DMA design issue
- *
- * Its DMA engine has a weird restriction that its Rx DMA engine
- * accepts only 16-bits aligned address, 32-bits aligned is not
- * acceptable. However this restriction does not apply to Tx DMA.
- *
- * Conclusion:
- * (1) Tx DMA Buffer Address:
- * 1 bytes aligned: Invalid
- * 2 bytes aligned: O.K
- * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
- * (2) Rx DMA Buffer Address:
- * 1 bytes aligned: Invalid
- * 2 bytes aligned: O.K
- * 4 bytes aligned: Invalid
- */
-
-struct ftmac110_chip {
- void __iomem *regs;
- uint32_t imr;
- uint32_t maccr;
- uint32_t lnkup;
- uint32_t phy_addr;
-
- struct ftmac110_desc *rxd;
- ulong rxd_dma;
- uint32_t rxd_idx;
-
- struct ftmac110_desc *txd;
- ulong txd_dma;
- uint32_t txd_idx;
-};
-
-static int ftmac110_reset(struct eth_device *dev);
-
-static uint16_t mdio_read(struct eth_device *dev,
- uint8_t phyaddr, uint8_t phyreg)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
- uint32_t tmp, ts;
- uint16_t ret = 0xffff;
-
- tmp = PHYCR_READ
- | (phyaddr << PHYCR_ADDR_SHIFT)
- | (phyreg << PHYCR_REG_SHIFT);
-
- writel(tmp, ®s->phycr);
-
- for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
- tmp = readl(®s->phycr);
- if (tmp & PHYCR_READ)
- continue;
- break;
- }
-
- if (tmp & PHYCR_READ)
- printf("ftmac110: mdio read timeout\n");
- else
- ret = (uint16_t)(tmp & 0xffff);
-
- return ret;
-}
-
-static void mdio_write(struct eth_device *dev,
- uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
- uint32_t tmp, ts;
-
- tmp = PHYCR_WRITE
- | (phyaddr << PHYCR_ADDR_SHIFT)
- | (phyreg << PHYCR_REG_SHIFT);
-
- writel(phydata, ®s->phydr);
- writel(tmp, ®s->phycr);
-
- for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
- if (readl(®s->phycr) & PHYCR_WRITE)
- continue;
- break;
- }
-
- if (readl(®s->phycr) & PHYCR_WRITE)
- printf("ftmac110: mdio write timeout\n");
-}
-
-static uint32_t ftmac110_phyqry(struct eth_device *dev)
-{
- ulong ts;
- uint32_t maccr;
- uint16_t pa, tmp, bmsr, bmcr;
- struct ftmac110_chip *chip = dev->priv;
-
- /* Default = 100Mbps Full */
- maccr = MACCR_100M | MACCR_FD;
-
- /* 1. find the phy device */
- for (pa = 0; pa < 32; ++pa) {
- tmp = mdio_read(dev, pa, MII_PHYSID1);
- if (tmp == 0xFFFF || tmp == 0x0000)
- continue;
- chip->phy_addr = pa;
- break;
- }
- if (pa >= 32) {
- puts("ftmac110: phy device not found!\n");
- goto exit;
- }
-
- /* 2. wait until link-up & auto-negotiation complete */
- chip->lnkup = 0;
- bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
- ts = get_timer(0);
- do {
- bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
- chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
- if (!chip->lnkup)
- continue;
- if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
- break;
- } while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
- if (!chip->lnkup) {
- puts("ftmac110: link down\n");
- goto exit;
- }
- if (!(bmcr & BMCR_ANENABLE))
- puts("ftmac110: auto negotiation disabled\n");
- else if (!(bmsr & BMSR_ANEGCOMPLETE))
- puts("ftmac110: auto negotiation timeout\n");
-
- /* 3. derive MACCR */
- if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
- tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
- tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
- if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
- maccr = MACCR_100M | MACCR_FD;
- else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
- maccr = MACCR_100M;
- else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
- maccr = MACCR_FD;
- else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
- maccr = 0;
- } else {
- if (bmcr & BMCR_SPEED100)
- maccr = MACCR_100M;
- else
- maccr = 0;
- if (bmcr & BMCR_FULLDPLX)
- maccr |= MACCR_FD;
- }
-
-exit:
- printf("ftmac110: %d Mbps, %s\n",
- (maccr & MACCR_100M) ? 100 : 10,
- (maccr & MACCR_FD) ? "Full" : "half");
- return maccr;
-}
-
-static int ftmac110_reset(struct eth_device *dev)
-{
- uint8_t *a;
- uint32_t i, maccr;
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
-
- /* 1. MAC reset */
- writel(MACCR_RESET, ®s->maccr);
- for (i = get_timer(0); get_timer(i) < 1000; ) {
- if (readl(®s->maccr) & MACCR_RESET)
- continue;
- break;
- }
- if (readl(®s->maccr) & MACCR_RESET) {
- printf("ftmac110: reset failed\n");
- return -ENXIO;
- }
-
- /* 1-1. Init tx ring */
- for (i = 0; i < CFG_TXDES_NUM; ++i) {
- /* owned by SW */
- chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK);
- }
- chip->txd_idx = 0;
-
- /* 1-2. Init rx ring */
- for (i = 0; i < CFG_RXDES_NUM; ++i) {
- /* owned by HW */
- chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK);
- chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER);
- }
- chip->rxd_idx = 0;
-
- /* 2. PHY status query */
- maccr = ftmac110_phyqry(dev);
-
- /* 3. Fix up the MACCR value */
- chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
- | MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;
-
- /* 4. MAC address setup */
- a = dev->enetaddr;
- writel(a[1] | (a[0] << 8), ®s->mac[0]);
- writel(a[5] | (a[4] << 8) | (a[3] << 16)
- | (a[2] << 24), ®s->mac[1]);
-
- /* 5. MAC registers setup */
- writel(chip->rxd_dma, ®s->rxba);
- writel(chip->txd_dma, ®s->txba);
- /* interrupt at each tx/rx */
- writel(ITC_DEFAULT, ®s->itc);
- /* no tx pool, rx poll = 1 normal cycle */
- writel(APTC_DEFAULT, ®s->aptc);
- /* rx threshold = [6/8 fifo, 2/8 fifo] */
- writel(DBLAC_DEFAULT, ®s->dblac);
- /* disable & clear all interrupt status */
- chip->imr = 0;
- writel(ISR_ALL, ®s->isr);
- writel(chip->imr, ®s->imr);
- /* enable mac */
- writel(chip->maccr, ®s->maccr);
-
- return 0;
-}
-
-static int ftmac110_probe(struct eth_device *dev, struct bd_info *bis)
-{
- debug("ftmac110: probe\n");
-
- if (ftmac110_reset(dev))
- return -1;
-
- return 0;
-}
-
-static void ftmac110_halt(struct eth_device *dev)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
-
- writel(0, ®s->imr);
- writel(0, ®s->maccr);
-
- debug("ftmac110: halt\n");
-}
-
-static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
- struct ftmac110_desc *txd;
- uint64_t ctrl;
-
- if (!chip->lnkup)
- return 0;
-
- if (len <= 0 || len > CFG_XBUF_SIZE) {
- printf("ftmac110: bad tx pkt len(%d)\n", len);
- return 0;
- }
-
- len = max(60, len);
-
- txd = &chip->txd[chip->txd_idx];
- ctrl = le64_to_cpu(txd->ctrl);
- if (ctrl & FTMAC110_TXD_OWNER) {
- /* kick-off Tx DMA */
- writel(0xffffffff, ®s->txpd);
- printf("ftmac110: out of txd\n");
- return 0;
- }
-
- memcpy(txd->vbuf, (void *)pkt, len);
- dma_map_single(txd->vbuf, len, DMA_TO_DEVICE);
-
- /* clear control bits */
- ctrl &= FTMAC110_TXD_CLRMASK;
- /* set len, fts and lts */
- ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS;
- /* set owner bit */
- ctrl |= FTMAC110_TXD_OWNER;
- /* write back to descriptor */
- txd->ctrl = cpu_to_le64(ctrl);
-
- /* kick-off Tx DMA */
- writel(0xffffffff, ®s->txpd);
-
- chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
-
- return len;
-}
-
-static int ftmac110_recv(struct eth_device *dev)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_desc *rxd;
- uint32_t len, rlen = 0;
- uint64_t ctrl;
- uint8_t *buf;
-
- if (!chip->lnkup)
- return 0;
-
- do {
- rxd = &chip->rxd[chip->rxd_idx];
- ctrl = le64_to_cpu(rxd->ctrl);
- if (ctrl & FTMAC110_RXD_OWNER)
- break;
-
- len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
- buf = rxd->vbuf;
-
- if (ctrl & FTMAC110_RXD_ERRMASK) {
- printf("ftmac110: rx error\n");
- } else {
- dma_map_single(buf, len, DMA_FROM_DEVICE);
- net_process_received_packet(buf, len);
- rlen += len;
- }
-
- /* owned by hardware */
- ctrl &= FTMAC110_RXD_CLRMASK;
- ctrl |= FTMAC110_RXD_OWNER;
- rxd->ctrl |= cpu_to_le64(ctrl);
-
- chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
- } while (0);
-
- return rlen;
-}
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-
-static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad,
- int reg)
-{
- uint16_t value = 0;
- int ret = 0;
- struct eth_device *dev;
-
- dev = eth_get_dev_by_name(bus->name);
- if (dev == NULL) {
- printf("%s: no such device\n", bus->name);
- ret = -1;
- } else {
- value = mdio_read(dev, addr, reg);
- }
-
- if (ret < 0)
- return ret;
- return value;
-}
-
-static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
- int reg, u16 value)
-{
- int ret = 0;
- struct eth_device *dev;
-
- dev = eth_get_dev_by_name(bus->name);
- if (dev == NULL) {
- printf("%s: no such device\n", bus->name);
- ret = -1;
- } else {
- mdio_write(dev, addr, reg, value);
- }
-
- return ret;
-}
-
-#endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
-
-int ftmac110_initialize(struct bd_info *bis)
-{
- int i, card_nr = 0;
- struct eth_device *dev;
- struct ftmac110_chip *chip;
-
- dev = malloc(sizeof(*dev) + sizeof(*chip));
- if (dev == NULL) {
- panic("ftmac110: out of memory 1\n");
- return -1;
- }
- chip = (struct ftmac110_chip *)(dev + 1);
- memset(dev, 0, sizeof(*dev) + sizeof(*chip));
-
- sprintf(dev->name, "FTMAC110#%d", card_nr);
-
- dev->iobase = CONFIG_FTMAC110_BASE;
- chip->regs = (void __iomem *)dev->iobase;
- dev->priv = chip;
- dev->init = ftmac110_probe;
- dev->halt = ftmac110_halt;
- dev->send = ftmac110_send;
- dev->recv = ftmac110_recv;
-
- /* allocate tx descriptors (it must be 16 bytes aligned) */
- chip->txd = dma_alloc_coherent(
- sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma);
- if (!chip->txd)
- panic("ftmac110: out of memory 3\n");
- memset(chip->txd, 0,
- sizeof(struct ftmac110_desc) * CFG_TXDES_NUM);
- for (i = 0; i < CFG_TXDES_NUM; ++i) {
- void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
-
- if (!va)
- panic("ftmac110: out of memory 4\n");
- chip->txd[i].vbuf = va;
- chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va));
- chip->txd[i].ctrl = 0; /* owned by SW */
- }
- chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END);
- chip->txd_idx = 0;
-
- /* allocate rx descriptors (it must be 16 bytes aligned) */
- chip->rxd = dma_alloc_coherent(
- sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma);
- if (!chip->rxd)
- panic("ftmac110: out of memory 4\n");
- memset((void *)chip->rxd, 0,
- sizeof(struct ftmac110_desc) * CFG_RXDES_NUM);
- for (i = 0; i < CFG_RXDES_NUM; ++i) {
- void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
-
- if (!va)
- panic("ftmac110: out of memory 5\n");
- /* it needs to be exactly 2 bytes aligned */
- va = ((uint8_t *)va + 2);
- chip->rxd[i].vbuf = va;
- chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va));
- chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER
- | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE));
- }
- chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END);
- chip->rxd_idx = 0;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = ftmac110_mdio_read;
- mdiodev->write = ftmac110_mdio_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
-
- card_nr++;
-
- return card_nr;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Faraday 10/100Mbps Ethernet Controller
- *
- * (C) Copyright 2013 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- */
-
-#ifndef _FTMAC110_H
-#define _FTMAC110_H
-
-struct ftmac110_regs {
- uint32_t isr; /* 0x00: Interrups Status Register */
- uint32_t imr; /* 0x04: Interrupt Mask Register */
- uint32_t mac[2]; /* 0x08: MAC Address */
- uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */
- uint32_t txpd; /* 0x18: Tx Poll Demand Register */
- uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */
- uint32_t txba; /* 0x20: Tx Ring Base Address Register */
- uint32_t rxba; /* 0x24: Rx Ring Base Address Register */
- uint32_t itc; /* 0x28: Interrupt Timer Control Register */
- uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */
- uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */
- uint32_t revr; /* 0x34: Revision Register */
- uint32_t fear; /* 0x38: Feature Register */
- uint32_t rsvd[19];
- uint32_t maccr; /* 0x88: MAC Control Register */
- uint32_t macsr; /* 0x8C: MAC Status Register */
- uint32_t phycr; /* 0x90: PHY Control Register */
- uint32_t phydr; /* 0x94: PHY Data Register */
- uint32_t fcr; /* 0x98: Flow Control Register */
- uint32_t bpr; /* 0x9C: Back Pressure Register */
-};
-
-/*
- * Interrupt status/mask register(ISR/IMR) bits
- */
-#define ISR_ALL 0x3ff
-#define ISR_PHYSTCHG (1 << 9) /* phy status change */
-#define ISR_AHBERR (1 << 8) /* bus error */
-#define ISR_RXLOST (1 << 7) /* rx lost */
-#define ISR_RXFIFO (1 << 6) /* rx to fifo */
-#define ISR_TXLOST (1 << 5) /* tx lost */
-#define ISR_TXOK (1 << 4) /* tx to ethernet */
-#define ISR_NOTXBUF (1 << 3) /* out of tx buffer */
-#define ISR_TXFIFO (1 << 2) /* tx to fifo */
-#define ISR_NORXBUF (1 << 1) /* out of rx buffer */
-#define ISR_RXOK (1 << 0) /* rx to buffer */
-
-/*
- * MACCR control bits
- */
-#define MACCR_100M (1 << 18) /* 100Mbps mode */
-#define MACCR_RXBCST (1 << 17) /* rx broadcast packet */
-#define MACCR_RXMCST (1 << 16) /* rx multicast packet */
-#define MACCR_FD (1 << 15) /* full duplex */
-#define MACCR_CRCAPD (1 << 14) /* tx crc append */
-#define MACCR_RXALL (1 << 12) /* rx all packets */
-#define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */
-#define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */
-#define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */
-#define MACCR_RXEN (1 << 8) /* rx enable */
-#define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */
-#define MACCR_TXEN (1 << 5) /* tx enable */
-#define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */
-#define MACCR_LOOPBACK (1 << 3) /* loop-back */
-#define MACCR_RESET (1 << 2) /* reset */
-#define MACCR_RXDMAEN (1 << 1) /* rx dma enable */
-#define MACCR_TXDMAEN (1 << 0) /* tx dma enable */
-
-/*
- * PHYCR control bits
- */
-#define PHYCR_READ (1 << 26)
-#define PHYCR_WRITE (1 << 27)
-#define PHYCR_REG_SHIFT 21
-#define PHYCR_ADDR_SHIFT 16
-
-/*
- * ITC control bits
- */
-
-/* Tx Cycle Length */
-#define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */
-#define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */
-/* Tx Threshold: Aggregate n interrupts as 1 interrupt */
-#define ITC_TX_THR(n) (((n) & 0x7) << 12)
-/* Tx Interrupt Timeout = n * Tx Cycle */
-#define ITC_TX_ITMO(n) (((n) & 0xf) << 8)
-/* Rx Cycle Length */
-#define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */
-#define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */
-/* Rx Threshold: Aggregate n interrupts as 1 interrupt */
-#define ITC_RX_THR(n) (((n) & 0x7) << 4)
-/* Rx Interrupt Timeout = n * Rx Cycle */
-#define ITC_RX_ITMO(n) (((n) & 0xf) << 0)
-
-#define ITC_DEFAULT \
- (ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0))
-
-/*
- * APTC contrl bits
- */
-
-/* Tx Cycle Length */
-#define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */
-#define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */
-/* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */
-#define APTC_TX_PTMO(n) (((n) & 0xf) << 8)
-/* Rx Cycle Length */
-#define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */
-#define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */
-/* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */
-#define APTC_RX_PTMO(n) (((n) & 0xf) << 0)
-
-#define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1))
-
-/*
- * DBLAC contrl bits
- */
-#define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */
-#define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */
-#define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */
-#define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */
-#define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */
-#define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */
-#define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */
-#define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */
-#define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */
-
-#define DBLAC_DEFAULT \
- (DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2))
-
-/*
- * descriptor structure
- */
-struct ftmac110_desc {
- uint64_t ctrl;
- uint32_t pbuf;
- void *vbuf;
-};
-
-#define FTMAC110_RXD_END ((uint64_t)1 << 63)
-#define FTMAC110_RXD_BUFSZ(x) (((uint64_t)(x) & 0x7ff) << 32)
-
-#define FTMAC110_RXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */
-#define FTMAC110_RXD_FRS ((uint64_t)1 << 29) /* first pkt desc */
-#define FTMAC110_RXD_LRS ((uint64_t)1 << 28) /* last pkt desc */
-#define FTMAC110_RXD_ODDNB ((uint64_t)1 << 22) /* odd nibble */
-#define FTMAC110_RXD_RUNT ((uint64_t)1 << 21) /* runt pkt */
-#define FTMAC110_RXD_FTL ((uint64_t)1 << 20) /* frame too long */
-#define FTMAC110_RXD_CRC ((uint64_t)1 << 19) /* pkt crc error */
-#define FTMAC110_RXD_ERR ((uint64_t)1 << 18) /* bus error */
-#define FTMAC110_RXD_ERRMASK ((uint64_t)0x1f << 18)
-#define FTMAC110_RXD_BCST ((uint64_t)1 << 17) /* Bcst pkt */
-#define FTMAC110_RXD_MCST ((uint64_t)1 << 16) /* Mcst pkt */
-#define FTMAC110_RXD_LEN(x) ((uint64_t)((x) & 0x7ff))
-
-#define FTMAC110_RXD_CLRMASK \
- (FTMAC110_RXD_END | FTMAC110_RXD_BUFSZ(0x7ff))
-
-#define FTMAC110_TXD_END ((uint64_t)1 << 63) /* end of ring */
-#define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */
-#define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */
-#define FTMAC110_TXD_FTS ((uint64_t)1 << 60) /* first pkt desc */
-#define FTMAC110_TXD_LTS ((uint64_t)1 << 59) /* last pkt desc */
-#define FTMAC110_TXD_LEN(x) ((uint64_t)((x) & 0x7ff) << 32)
-
-#define FTMAC110_TXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */
-#define FTMAC110_TXD_COL ((uint64_t)3) /* collision */
-
-#define FTMAC110_TXD_CLRMASK \
- (FTMAC110_TXD_END)
-
-#endif /* FTMAC110_H */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*------------------------------------------------------------------------
- * lan91c96.c
- * This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based
- * on the SMC91111 driver from U-Boot.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Rolf Offermanns <rof@sysgo.de>
- *
- * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- * Developed by Simple Network Magic Corporation (SNMC)
- * Copyright (C) 1996 by Erik Stahlman (ES)
- *
- * Information contained in this file was obtained from the LAN91C96
- * manual from SMC. To get a copy, if you really want one, you can find
- * information under www.smsc.com.
- *
- * "Features" of the SMC chip:
- * 6144 byte packet memory. ( for the 91C96 )
- * EEPROM for configuration
- * AUI/TP selection ( mine has 10Base2/10BaseT select )
- *
- * Arguments:
- * io = for the base address
- * irq = for the IRQ
- *
- * author:
- * Erik Stahlman ( erik@vt.edu )
- * Daris A Nevil ( dnevil@snmc.com )
- *
- *
- * Hardware multicast code from Peter Cammaert ( pc@denkart.be )
- *
- * Sources:
- * o SMSC LAN91C96 databook (www.smsc.com)
- * o smc91111.c (u-boot driver)
- * o smc9194.c (linux kernel driver)
- * o lan91c96.c (Intel Diagnostic Manager driver)
- *
- * History:
- * 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version)
- * for lan91c96
- *---------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <malloc.h>
-#include <linux/delay.h>
-#include "lan91c96.h"
-#include <net.h>
-#include <linux/compiler.h>
-
-/*------------------------------------------------------------------------
- *
- * Configuration options, for the experienced user to change.
- *
- -------------------------------------------------------------------------*/
-
-/* Use power-down feature of the chip */
-#define POWER_DOWN 0
-
-/*
- * Wait time for memory to be free. This probably shouldn't be
- * tuned that much, as waiting for this means nothing else happens
- * in the system
-*/
-#define MEMORY_WAIT_TIME 16
-
-#define SMC_DEBUG 0
-
-#if (SMC_DEBUG > 2 )
-#define PRINTK3(args...) printf(args)
-#else
-#define PRINTK3(args...)
-#endif
-
-#if SMC_DEBUG > 1
-#define PRINTK2(args...) printf(args)
-#else
-#define PRINTK2(args...)
-#endif
-
-#ifdef SMC_DEBUG
-#define PRINTK(args...) printf(args)
-#else
-#define PRINTK(args...)
-#endif
-
-
-/*------------------------------------------------------------------------
- *
- * The internal workings of the driver. If you are changing anything
- * here with the SMC stuff, you should have the datasheet and know
- * what you are doing.
- *
- *------------------------------------------------------------------------
- */
-#define DRIVER_NAME "LAN91C96"
-#define SMC_ALLOC_MAX_TRY 5
-#define SMC_TX_TIMEOUT 30
-
-#define ETH_ZLEN 60
-
-#ifdef CONFIG_LAN91C96_USE_32_BIT
-#define USE_32_BIT 1
-#else
-#undef USE_32_BIT
-#endif
-
-/* See if a MAC address is defined in the current environment. If so use it. If not
- . print a warning and set the environment and other globals with the default.
- . If an EEPROM is present it really should be consulted.
-*/
-static int smc_get_ethaddr(struct bd_info *bd, struct eth_device *dev);
-static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac);
-
-/* ------------------------------------------------------------
- * Internal routines
- * ------------------------------------------------------------
- */
-
-static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
-
-/*
- * This function must be called before smc_open() if you want to override
- * the default mac address.
- */
-
-static void smc_set_mac_addr(const unsigned char *addr)
-{
- int i;
-
- for (i = 0; i < sizeof (smc_mac_addr); i++) {
- smc_mac_addr[i] = addr[i];
- }
-}
-
-/***********************************************
- * Show available memory *
- ***********************************************/
-void dump_memory_info(struct eth_device *dev)
-{
- __maybe_unused word mem_info;
- word old_bank;
-
- old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT) & 0xF;
-
- SMC_SELECT_BANK(dev, 0);
- mem_info = SMC_inw(dev, LAN91C96_MIR);
- PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048);
-
- SMC_SELECT_BANK(dev, old_bank);
-}
-
-/*
- * A rather simple routine to print out a packet for debugging purposes.
- */
-#if SMC_DEBUG > 2
-static void print_packet (byte *, int);
-#endif
-
-static int poll4int (struct eth_device *dev, byte mask, int timeout)
-{
- int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
- int is_timeout = 0;
- word old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT);
-
- PRINTK2 ("Polling...\n");
- SMC_SELECT_BANK(dev, 2);
- while ((SMC_inw(dev, LAN91C96_INT_STATS) & mask) == 0) {
- if (get_timer (0) >= tmo) {
- is_timeout = 1;
- break;
- }
- }
-
- /* restore old bank selection */
- SMC_SELECT_BANK(dev, old_bank);
-
- if (is_timeout)
- return 1;
- else
- return 0;
-}
-
-/*
- * Function: smc_reset
- * Purpose:
- * This sets the SMC91111 chip to its normal state, hopefully from whatever
- * mess that any other DOS driver has put it in.
- *
- * Maybe I should reset more registers to defaults in here? SOFTRST should
- * do that for me.
- *
- * Method:
- * 1. send a SOFT RESET
- * 2. wait for it to finish
- * 3. enable autorelease mode
- * 4. reset the memory management unit
- * 5. clear all interrupts
- *
-*/
-static void smc_reset(struct eth_device *dev)
-{
- PRINTK2("%s:smc_reset\n", dev->name);
-
- /* This resets the registers mostly to defaults, but doesn't
- affect EEPROM. That seems unnecessary */
- SMC_SELECT_BANK(dev, 0);
- SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
-
- udelay(10);
-
- /* Disable transmit and receive functionality */
- SMC_outw(dev, 0, LAN91C96_RCR);
- SMC_outw(dev, 0, LAN91C96_TCR);
-
- /* set the control register */
- SMC_SELECT_BANK(dev, 1);
- SMC_outw(dev, SMC_inw(dev, LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8,
- LAN91C96_CONTROL);
-
- /* Disable all interrupts */
- SMC_outb(dev, 0, LAN91C96_INT_MASK);
-}
-
-/*
- * Function: smc_enable
- * Purpose: let the chip talk to the outside work
- * Method:
- * 1. Initialize the Memory Configuration Register
- * 2. Enable the transmitter
- * 3. Enable the receiver
-*/
-static void smc_enable(struct eth_device *dev)
-{
- PRINTK2("%s:smc_enable\n", dev->name);
- SMC_SELECT_BANK(dev, 0);
-
- /* Initialize the Memory Configuration Register. See page
- 49 of the LAN91C96 data sheet for details. */
- SMC_outw(dev, LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR);
-
- /* Initialize the Transmit Control Register */
- SMC_outw(dev, LAN91C96_TCR_TXENA, LAN91C96_TCR);
- /* Initialize the Receive Control Register
- * FIXME:
- * The promiscuous bit set because I could not receive ARP reply
- * packets from the server when I send a ARP request. It only works
- * when I set the promiscuous bit
- */
- SMC_outw(dev, LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR);
-}
-
-/*
- * Function: smc_shutdown
- * Purpose: closes down the SMC91xxx chip.
- * Method:
- * 1. zero the interrupt mask
- * 2. clear the enable receive flag
- * 3. clear the enable xmit flags
- *
- * TODO:
- * (1) maybe utilize power down mode.
- * Why not yet? Because while the chip will go into power down mode,
- * the manual says that it will wake up in response to any I/O requests
- * in the register space. Empirical results do not show this working.
- */
-static void smc_shutdown(struct eth_device *dev)
-{
- PRINTK2("%s:smc_shutdown\n", dev->name);
-
- /* no more interrupts for me */
- SMC_SELECT_BANK(dev, 2);
- SMC_outb(dev, 0, LAN91C96_INT_MASK);
-
- /* and tell the card to stay away from that nasty outside world */
- SMC_SELECT_BANK(dev, 0);
- SMC_outb(dev, 0, LAN91C96_RCR);
- SMC_outb(dev, 0, LAN91C96_TCR);
-}
-
-
-/*
- * Function: smc_hardware_send_packet(struct net_device * )
- * Purpose:
- * This sends the actual packet to the SMC9xxx chip.
- *
- * Algorithm:
- * First, see if a saved_skb is available.
- * ( this should NOT be called if there is no 'saved_skb'
- * Now, find the packet number that the chip allocated
- * Point the data pointers at it in memory
- * Set the length word in the chip's memory
- * Dump the packet to chip memory
- * Check if a last byte is needed ( odd length packet )
- * if so, set the control flag right
- * Tell the card to send it
- * Enable the transmit interrupt, so I know if it failed
- * Free the kernel data if I actually sent it.
- */
-static int smc_send_packet(struct eth_device *dev, void *packet,
- int packet_length)
-{
- byte packet_no;
- byte *buf;
- int length;
- int numPages;
- int try = 0;
- int time_out;
- byte status;
-
-
- PRINTK3("%s:smc_hardware_send_packet\n", dev->name);
-
- length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
-
- /* allocate memory
- ** The MMU wants the number of pages to be the number of 256 bytes
- ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
- **
- ** The 91C111 ignores the size bits, but the code is left intact
- ** for backwards and future compatibility.
- **
- ** Pkt size for allocating is data length +6 (for additional status
- ** words, length and ctl!)
- **
- ** If odd size then last byte is included in this header.
- */
- numPages = ((length & 0xfffe) + 6);
- numPages >>= 8; /* Divide by 256 */
-
- if (numPages > 7) {
- printf("%s: Far too big packet error. \n", dev->name);
- return 0;
- }
-
- /* now, try to allocate the memory */
-
- SMC_SELECT_BANK(dev, 2);
- SMC_outw(dev, LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU);
-
- again:
- try++;
- time_out = MEMORY_WAIT_TIME;
- do {
- status = SMC_inb(dev, LAN91C96_INT_STATS);
- if (status & LAN91C96_IST_ALLOC_INT) {
-
- SMC_outb(dev, LAN91C96_IST_ALLOC_INT,
- LAN91C96_INT_STATS);
- break;
- }
- } while (--time_out);
-
- if (!time_out) {
- PRINTK2 ("%s: memory allocation, try %d failed ...\n",
- dev->name, try);
- if (try < SMC_ALLOC_MAX_TRY)
- goto again;
- else
- return 0;
- }
-
- PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
- dev->name, try);
-
- /* I can send the packet now.. */
- buf = (byte *) packet;
-
- /* If I get here, I _know_ there is a packet slot waiting for me */
- packet_no = SMC_inb(dev, LAN91C96_ARR);
- if (packet_no & LAN91C96_ARR_FAILED) {
- /* or isn't there? BAD CHIP! */
- printf("%s: Memory allocation failed. \n", dev->name);
- return 0;
- }
-
- /* we have a packet address, so tell the card to use it */
- SMC_outb(dev, packet_no, LAN91C96_PNR);
-
- /* point to the beginning of the packet */
- SMC_outw(dev, LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
-
- PRINTK3("%s: Trying to xmit packet of length %x\n",
- dev->name, length);
-
-#if SMC_DEBUG > 2
- printf ("Transmitting Packet\n");
- print_packet (buf, length);
-#endif
-
- /* send the packet length ( +6 for status, length and ctl byte )
- and the status word ( set to zeros ) */
-#ifdef USE_32_BIT
- SMC_outl(dev, (length + 6) << 16, LAN91C96_DATA_HIGH);
-#else
- SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
- /* send the packet length ( +6 for status words, length, and ctl */
- SMC_outw(dev, (length + 6), LAN91C96_DATA_HIGH);
-#endif /* USE_32_BIT */
-
- /* send the actual data
- * I _think_ it's faster to send the longs first, and then
- * mop up by sending the last word. It depends heavily
- * on alignment, at least on the 486. Maybe it would be
- * a good idea to check which is optimal? But that could take
- * almost as much time as is saved?
- */
-#ifdef USE_32_BIT
- SMC_outsl(dev, LAN91C96_DATA_HIGH, buf, length >> 2);
- if (length & 0x2)
- SMC_outw(dev, *((word *) (buf + (length & 0xFFFFFFFC))),
- LAN91C96_DATA_HIGH);
-#else
- SMC_outsw(dev, LAN91C96_DATA_HIGH, buf, (length) >> 1);
-#endif /* USE_32_BIT */
-
- /* Send the last byte, if there is one. */
- if ((length & 1) == 0) {
- SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
- } else {
- SMC_outw(dev, buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH);
- }
-
- /* and let the chipset deal with it */
- SMC_outw(dev, LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU);
-
- /* poll for TX INT */
- if (poll4int (dev, LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) {
- /* sending failed */
- PRINTK2("%s: TX timeout, sending failed...\n", dev->name);
-
- /* release packet */
- SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
-
- /* wait for MMU getting ready (low) */
- while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay(10);
-
- PRINTK2("MMU ready\n");
-
-
- return 0;
- } else {
- /* ack. int */
- SMC_outw(dev, LAN91C96_IST_TX_INT, LAN91C96_INT_STATS);
-
- PRINTK2("%s: Sent packet of length %d \n", dev->name, length);
-
- /* release packet */
- SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
-
- /* wait for MMU getting ready (low) */
- while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay(10);
-
- PRINTK2 ("MMU ready\n");
- }
-
- return length;
-}
-
-
-/*
- * Open and Initialize the board
- *
- * Set up everything, reset the card, etc ..
- *
- */
-static int smc_open(struct bd_info *bd, struct eth_device *dev)
-{
- int i, err; /* used to set hw ethernet address */
-
- PRINTK2("%s:smc_open\n", dev->name);
-
- /* reset the hardware */
-
- smc_reset(dev);
- smc_enable(dev);
-
- SMC_SELECT_BANK(dev, 1);
- /* set smc_mac_addr, and sync it with u-boot globals */
- err = smc_get_ethaddr(bd, dev);
- if (err < 0)
- return -1;
-#ifdef USE_32_BIT
- for (i = 0; i < 6; i += 2) {
- word address;
-
- address = smc_mac_addr[i + 1] << 8;
- address |= smc_mac_addr[i];
- SMC_outw(dev, address, LAN91C96_IA0 + i);
- }
-#else
- for (i = 0; i < 6; i++)
- SMC_outb(dev, smc_mac_addr[i], LAN91C96_IA0 + i);
-#endif
- return 0;
-}
-
-/*-------------------------------------------------------------
- *
- * smc_rcv - receive a packet from the card
- *
- * There is ( at least ) a packet waiting to be read from
- * chip-memory.
- *
- * o Read the status
- * o If an error, record it
- * o otherwise, read in the packet
- *-------------------------------------------------------------
- */
-static int smc_rcv(struct eth_device *dev)
-{
- int packet_number;
- word status;
- word packet_length;
- int is_error = 0;
-
-#ifdef USE_32_BIT
- dword stat_len;
-#endif
-
-
- SMC_SELECT_BANK(dev, 2);
- packet_number = SMC_inw(dev, LAN91C96_FIFO);
-
- if (packet_number & LAN91C96_FIFO_RXEMPTY) {
- return 0;
- }
-
- PRINTK3("%s:smc_rcv\n", dev->name);
- /* start reading from the start of the packet */
- SMC_outw(dev, LAN91C96_PTR_READ | LAN91C96_PTR_RCV |
- LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
-
- /* First two words are status and packet_length */
-#ifdef USE_32_BIT
- stat_len = SMC_inl(dev, LAN91C96_DATA_HIGH);
- status = stat_len & 0xffff;
- packet_length = stat_len >> 16;
-#else
- status = SMC_inw(dev, LAN91C96_DATA_HIGH);
- packet_length = SMC_inw(dev, LAN91C96_DATA_HIGH);
-#endif
-
- packet_length &= 0x07ff; /* mask off top bits */
-
- PRINTK2 ("RCV: STATUS %4x LENGTH %4x\n", status, packet_length);
-
- if (!(status & FRAME_FILTER)) {
- /* Adjust for having already read the first two words */
- packet_length -= 4; /*4; */
-
-
- /* set odd length for bug in LAN91C111, */
- /* which never sets RS_ODDFRAME */
- /* TODO ? */
-
-
-#ifdef USE_32_BIT
- PRINTK3 (" Reading %d dwords (and %d bytes) \n",
- packet_length >> 2, packet_length & 3);
- /* QUESTION: Like in the TX routine, do I want
- to send the DWORDs or the bytes first, or some
- mixture. A mixture might improve already slow PIO
- performance */
- SMC_insl(dev, LAN91C96_DATA_HIGH, net_rx_packets[0],
- packet_length >> 2);
- /* read the left over bytes */
- if (packet_length & 3) {
- int i;
-
- byte *tail = (byte *)(net_rx_packets[0] +
- (packet_length & ~3));
- dword leftover = SMC_inl(dev, LAN91C96_DATA_HIGH);
-
- for (i = 0; i < (packet_length & 3); i++)
- *tail++ = (byte) (leftover >> (8 * i)) & 0xff;
- }
-#else
- PRINTK3(" Reading %d words and %d byte(s)\n",
- (packet_length >> 1), packet_length & 1);
- SMC_insw(dev, LAN91C96_DATA_HIGH, net_rx_packets[0],
- packet_length >> 1);
-
-#endif /* USE_32_BIT */
-
-#if SMC_DEBUG > 2
- printf ("Receiving Packet\n");
- print_packet((byte *)net_rx_packets[0], packet_length);
-#endif
- } else {
- /* error ... */
- /* TODO ? */
- is_error = 1;
- }
-
- while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay(1); /* Wait until not busy */
-
- /* error or good, tell the card to get rid of this packet */
- SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
-
- while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay(1); /* Wait until not busy */
-
- if (!is_error) {
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[0], packet_length);
- return packet_length;
- } else {
- return 0;
- }
-
-}
-
-/*----------------------------------------------------
- * smc_close
- *
- * this makes the board clean up everything that it can
- * and not talk to the outside world. Caused by
- * an 'ifconfig ethX down'
- *
- -----------------------------------------------------*/
-static int smc_close(struct eth_device *dev)
-{
- PRINTK2("%s:smc_close\n", dev->name);
-
- /* clear everything */
- smc_shutdown(dev);
-
- return 0;
-}
-
-#if SMC_DEBUG > 2
-static void print_packet(byte *buf, int length)
-{
-#if 0
- int i;
- int remainder;
- int lines;
-
- printf ("Packet of length %d \n", length);
-
- lines = length / 16;
- remainder = length % 16;
-
- for (i = 0; i < lines; i++) {
- int cur;
-
- for (cur = 0; cur < 8; cur++) {
- byte a, b;
-
- a = *(buf++);
- b = *(buf++);
- printf ("%02x%02x ", a, b);
- }
- printf ("\n");
- }
- for (i = 0; i < remainder / 2; i++) {
- byte a, b;
-
- a = *(buf++);
- b = *(buf++);
- printf ("%02x%02x ", a, b);
- }
- printf ("\n");
-#endif /* 0 */
-}
-#endif /* SMC_DEBUG > 2 */
-
-static int lan91c96_init(struct eth_device *dev, struct bd_info *bd)
-{
- return smc_open(bd, dev);
-}
-
-static void lan91c96_halt(struct eth_device *dev)
-{
- smc_close(dev);
-}
-
-static int lan91c96_recv(struct eth_device *dev)
-{
- return smc_rcv(dev);
-}
-
-static int lan91c96_send(struct eth_device *dev, void *packet,
- int length)
-{
- return smc_send_packet(dev, packet, length);
-}
-
-/* smc_get_ethaddr
- *
- * This checks both the environment and the ROM for an ethernet address. If
- * found, the environment takes precedence.
- */
-
-static int smc_get_ethaddr(struct bd_info *bd, struct eth_device *dev)
-{
- uchar v_mac[6];
-
- if (!eth_env_get_enetaddr("ethaddr", v_mac)) {
- /* get ROM mac value if any */
- if (!get_rom_mac(dev, v_mac)) {
- printf("\n*** ERROR: ethaddr is NOT set !!\n");
- return -1;
- }
- eth_env_set_enetaddr("ethaddr", v_mac);
- }
-
- smc_set_mac_addr(v_mac); /* use old function to update smc default */
- PRINTK("Using MAC Address %pM\n", v_mac);
- return 0;
-}
-
-/*
- * get_rom_mac()
- * Note, this has omly been tested for the OMAP730 P2.
- */
-
-static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac)
-{
- int i;
- SMC_SELECT_BANK(dev, 1);
- for (i=0; i<6; i++)
- {
- v_rom_mac[i] = SMC_inb(dev, LAN91C96_IA0 + i);
- }
- return (1);
-}
-
-/* Structure to detect the device IDs */
-struct id_type {
- u8 id;
- char *name;
-};
-static struct id_type supported_chips[] = {
- {0, ""}, /* Dummy entry to prevent id check failure */
- {9, "LAN91C110"},
- {8, "LAN91C100FD"},
- {7, "LAN91C100"},
- {5, "LAN91C95"},
- {4, "LAN91C94/96"},
- {3, "LAN91C90/92"},
-};
-/* lan91c96_detect_chip
- * See:
- * http://www.embeddedsys.com/subpages/resources/images/documents/LAN91C96_datasheet.pdf
- * page 71 - that is the closest we get to detect this device
- */
-static int lan91c96_detect_chip(struct eth_device *dev)
-{
- u8 chip_id;
- int r;
- SMC_SELECT_BANK(dev, 3);
- chip_id = (SMC_inw(dev, 0xA) & LAN91C96_REV_CHIPID) >> 4;
- SMC_SELECT_BANK(dev, 0);
- for (r = 0; r < ARRAY_SIZE(supported_chips); r++)
- if (chip_id == supported_chips[r].id)
- return r;
- return 0;
-}
-
-int lan91c96_initialize(u8 dev_num, int base_addr)
-{
- struct eth_device *dev;
- int r = 0;
-
- dev = malloc(sizeof(*dev));
- if (!dev) {
- return 0;
- }
- memset(dev, 0, sizeof(*dev));
-
- dev->iobase = base_addr;
-
- /* Try to detect chip. Will fail if not present. */
- r = lan91c96_detect_chip(dev);
- if (!r) {
- free(dev);
- return 0;
- }
- get_rom_mac(dev, dev->enetaddr);
-
- dev->init = lan91c96_init;
- dev->halt = lan91c96_halt;
- dev->send = lan91c96_send;
- dev->recv = lan91c96_recv;
- sprintf(dev->name, "%s-%hu", supported_chips[r].name, dev_num);
-
- eth_register(dev);
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*------------------------------------------------------------------------
- * lan91c96.h
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Rolf Offermanns <rof@sysgo.de>
- * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- * Developed by Simple Network Magic Corporation (SNMC)
- * Copyright (C) 1996 by Erik Stahlman (ES)
- *
- * This file contains register information and access macros for
- * the LAN91C96 single chip ethernet controller. It is a modified
- * version of the smc9111.h file.
- *
- * Information contained in this file was obtained from the LAN91C96
- * manual from SMC. To get a copy, if you really want one, you can find
- * information under www.smsc.com.
- *
- * Authors
- * Erik Stahlman ( erik@vt.edu )
- * Daris A Nevil ( dnevil@snmc.com )
- *
- * History
- * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version)
- * for lan91c96
- *-------------------------------------------------------------------------
- */
-#ifndef _LAN91C96_H_
-#define _LAN91C96_H_
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <config.h>
-
-/* I want some simple types */
-
-typedef unsigned char byte;
-typedef unsigned short word;
-typedef unsigned long int dword;
-
-/*
- * DEBUGGING LEVELS
- *
- * 0 for normal operation
- * 1 for slightly more details
- * >2 for various levels of increasingly useless information
- * 2 for interrupt tracking, status flags
- * 3 for packet info
- * 4 for complete packet dumps
- */
-/*#define SMC_DEBUG 0 */
-
-/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
-
-#define SMC_IO_EXTENT 16
-
-#ifdef CONFIG_CPU_PXA25X
-
-#define SMC_IO_SHIFT 0
-
-#define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT))
-
-#define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r)))
-#define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r)))
-#define SMC_inb(edev, p) ({ \
- unsigned int __p = p; \
- unsigned int __v = SMC_inw(edev, __p & ~1); \
- if (__p & 1) __v >>= 8; \
- else __v &= 0xff; \
- __v; })
-
-#define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d)
-#define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d)
-#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
- word __w = SMC_inw(edev, (r)&~1); \
- __w &= ((r)&1) ? 0x00FF : 0xFF00; \
- __w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(edev, __w, (r)&~1); \
- })
-
-#define SMC_outsl(edev, r, b, l) ({ int __i; \
- dword *__b2; \
- __b2 = (dword *) b; \
- for (__i = 0; __i < l; __i++) { \
- SMC_outl(edev, *(__b2 + __i),\
- r); \
- } \
- })
-
-#define SMC_outsw(edev, r, b, l) ({ int __i; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- SMC_outw(edev, *(__b2 + __i),\
- r); \
- } \
- })
-
-#define SMC_insl(edev, r, b, l) ({ int __i ; \
- dword *__b2; \
- __b2 = (dword *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl(edev,\
- r); \
- SMC_inl(edev, 0); \
- }; \
- })
-
-#define SMC_insw(edev, r, b, l) ({ int __i ; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(edev,\
- r); \
- SMC_inw(edev, 0); \
- }; \
- })
-
-#define SMC_insb(edev, r, b, l) ({ int __i ; \
- byte *__b2; \
- __b2 = (byte *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inb(edev,\
- r); \
- SMC_inb(edev, 0); \
- }; \
- })
-
-#else /* if not CONFIG_CPU_PXA25X */
-
-/*
- * We have only 16 Bit PCMCIA access on Socket 0
- */
-
-#define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r))))
-#define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\
- SMC_inw(edev, r)&0xFF)
-
-#define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d)
-#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
- word __w = SMC_inw(edev, (r)&~1); \
- __w &= ((r)&1) ? 0x00FF : 0xFF00; \
- __w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(edev, __w, (r)&~1); \
- })
-#define SMC_outsw(edev, r, b, l) ({ int __i; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- SMC_outw(edev, *(__b2 + __i),\
- r); \
- } \
- })
-
-#define SMC_insw(edev, r, b, l) ({ int __i ; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(edev,\
- r); \
- SMC_inw(edev, 0); \
- }; \
- })
-
-#endif
-
-/*
- ****************************************************************************
- * Bank Select Field
- ****************************************************************************
- */
-#define LAN91C96_BANK_SELECT 14 /* Bank Select Register */
-#define LAN91C96_BANKSELECT (0x3UC << 0)
-#define BANK0 0x00
-#define BANK1 0x01
-#define BANK2 0x02
-#define BANK3 0x03
-#define BANK4 0x04
-
-/*
- ****************************************************************************
- * EEPROM Addresses.
- ****************************************************************************
- */
-#define EEPROM_MAC_OFFSET_1 0x6020
-#define EEPROM_MAC_OFFSET_2 0x6021
-#define EEPROM_MAC_OFFSET_3 0x6022
-
-/*
- ****************************************************************************
- * Bank 0 Register Map in I/O Space
- ****************************************************************************
- */
-#define LAN91C96_TCR 0 /* Transmit Control Register */
-#define LAN91C96_EPH_STATUS 2 /* EPH Status Register */
-#define LAN91C96_RCR 4 /* Receive Control Register */
-#define LAN91C96_COUNTER 6 /* Counter Register */
-#define LAN91C96_MIR 8 /* Memory Information Register */
-#define LAN91C96_MCR 10 /* Memory Configuration Register */
-
-/*
- ****************************************************************************
- * Transmit Control Register - Bank 0 - Offset 0
- ****************************************************************************
- */
-#define LAN91C96_TCR_TXENA (0x1U << 0)
-#define LAN91C96_TCR_LOOP (0x1U << 1)
-#define LAN91C96_TCR_FORCOL (0x1U << 2)
-#define LAN91C96_TCR_TXP_EN (0x1U << 3)
-#define LAN91C96_TCR_PAD_EN (0x1U << 7)
-#define LAN91C96_TCR_NOCRC (0x1U << 8)
-#define LAN91C96_TCR_MON_CSN (0x1U << 10)
-#define LAN91C96_TCR_FDUPLX (0x1U << 11)
-#define LAN91C96_TCR_STP_SQET (0x1U << 12)
-#define LAN91C96_TCR_EPH_LOOP (0x1U << 13)
-#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14)
-#define LAN91C96_TCR_FDSE (0x1U << 15)
-
-/*
- ****************************************************************************
- * EPH Status Register - Bank 0 - Offset 2
- ****************************************************************************
- */
-#define LAN91C96_EPHSR_TX_SUC (0x1U << 0)
-#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1)
-#define LAN91C96_EPHSR_MUL_COL (0x1U << 2)
-#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3)
-#define LAN91C96_EPHSR_16COL (0x1U << 4)
-#define LAN91C96_EPHSR_SQET (0x1U << 5)
-#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6)
-#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7)
-#define LAN91C96_EPHSR_WAKEUP (0x1U << 8)
-#define LAN91C96_EPHSR_LATCOL (0x1U << 9)
-#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10)
-#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11)
-#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12)
-
-#define LAN91C96_EPHSR_LINK_OK (0x1U << 14)
-#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15)
-
-#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \
- LAN91C96_EPHSR_MUL_COL | \
- LAN91C96_EPHSR_16COL | \
- LAN91C96_EPHSR_SQET | \
- LAN91C96_EPHSR_TX_DEFR | \
- LAN91C96_EPHSR_LATCOL | \
- LAN91C96_EPHSR_LOST_CARR | \
- LAN91C96_EPHSR_EXC_DEF | \
- LAN91C96_EPHSR_LINK_OK | \
- LAN91C96_EPHSR_TX_UNRN)
-
-/*
- ****************************************************************************
- * Receive Control Register - Bank 0 - Offset 4
- ****************************************************************************
- */
-#define LAN91C96_RCR_RX_ABORT (0x1U << 0)
-#define LAN91C96_RCR_PRMS (0x1U << 1)
-#define LAN91C96_RCR_ALMUL (0x1U << 2)
-#define LAN91C96_RCR_RXEN (0x1U << 8)
-#define LAN91C96_RCR_STRIP_CRC (0x1U << 9)
-#define LAN91C96_RCR_FILT_CAR (0x1U << 14)
-#define LAN91C96_RCR_SOFT_RST (0x1U << 15)
-
-/*
- ****************************************************************************
- * Counter Register - Bank 0 - Offset 6
- ****************************************************************************
- */
-#define LAN91C96_ECR_SNGL_COL (0xFU << 0)
-#define LAN91C96_ECR_MULT_COL (0xFU << 5)
-#define LAN91C96_ECR_DEF_TX (0xFU << 8)
-#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12)
-
-/*
- ****************************************************************************
- * Memory Information Register - Bank 0 - OFfset 8
- ****************************************************************************
- */
-#define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */
-
-/*
- ****************************************************************************
- * Memory Configuration Register - Bank 0 - Offset 10
- ****************************************************************************
- */
-#define LAN91C96_MCR_MEM_RES (0xFFU << 0)
-#define LAN91C96_MCR_MEM_MULT (0x3U << 9)
-#define LAN91C96_MCR_HIGH_ID (0x3U << 12)
-
-#define LAN91C96_MCR_TRANSMIT_PAGES 0x6
-
-/*
- ****************************************************************************
- * Bank 1 Register Map in I/O Space
- ****************************************************************************
- */
-#define LAN91C96_CONFIG 0 /* Configuration Register */
-#define LAN91C96_BASE 2 /* Base Address Register */
-#define LAN91C96_IA0 4 /* Individual Address Register - 0 */
-#define LAN91C96_IA1 5 /* Individual Address Register - 1 */
-#define LAN91C96_IA2 6 /* Individual Address Register - 2 */
-#define LAN91C96_IA3 7 /* Individual Address Register - 3 */
-#define LAN91C96_IA4 8 /* Individual Address Register - 4 */
-#define LAN91C96_IA5 9 /* Individual Address Register - 5 */
-#define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */
-#define LAN91C96_CONTROL 12 /* Control Register */
-
-/*
- ****************************************************************************
- * Configuration Register - Bank 1 - Offset 0
- ****************************************************************************
- */
-#define LAN91C96_CR_INT_SEL0 (0x1U << 1)
-#define LAN91C96_CR_INT_SEL1 (0x1U << 2)
-#define LAN91C96_CR_RES (0x3U << 3)
-#define LAN91C96_CR_DIS_LINK (0x1U << 6)
-#define LAN91C96_CR_16BIT (0x1U << 7)
-#define LAN91C96_CR_AUI_SELECT (0x1U << 8)
-#define LAN91C96_CR_SET_SQLCH (0x1U << 9)
-#define LAN91C96_CR_FULL_STEP (0x1U << 10)
-#define LAN91C96_CR_NO_WAIT (0x1U << 12)
-
-/*
- ****************************************************************************
- * Base Address Register - Bank 1 - Offset 2
- ****************************************************************************
- */
-#define LAN91C96_BAR_RA_BITS (0x27U << 0)
-#define LAN91C96_BAR_ROM_SIZE (0x1U << 6)
-#define LAN91C96_BAR_A_BITS (0xFFU << 8)
-
-/*
- ****************************************************************************
- * Control Register - Bank 1 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_CTR_STORE (0x1U << 0)
-#define LAN91C96_CTR_RELOAD (0x1U << 1)
-#define LAN91C96_CTR_EEPROM (0x1U << 2)
-#define LAN91C96_CTR_TE_ENABLE (0x1U << 5)
-#define LAN91C96_CTR_CR_ENABLE (0x1U << 6)
-#define LAN91C96_CTR_LE_ENABLE (0x1U << 7)
-#define LAN91C96_CTR_BIT_8 (0x1U << 8)
-#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
-#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12)
-#define LAN91C96_CTR_PWRDN (0x1U << 13)
-#define LAN91C96_CTR_RCV_BAD (0x1U << 14)
-
-/*
- ****************************************************************************
- * Bank 2 Register Map in I/O Space
- ****************************************************************************
- */
-#define LAN91C96_MMU 0 /* MMU Command Register */
-#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */
-#define LAN91C96_PNR 2 /* Packet Number Register */
-#define LAN91C96_ARR 3 /* Allocation Result Register */
-#define LAN91C96_FIFO 4 /* FIFO Ports Register */
-#define LAN91C96_POINTER 6 /* Pointer Register */
-#define LAN91C96_DATA_HIGH 8 /* Data High Register */
-#define LAN91C96_DATA_LOW 10 /* Data Low Register */
-#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */
-#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */
-#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */
-
-/*
- ****************************************************************************
- * MMU Command Register - Bank 2 - Offset 0
- ****************************************************************************
- */
-#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0)
-#define LAN91C96_MMUCR_N1 (0x1U << 1)
-#define LAN91C96_MMUCR_N2 (0x1U << 2)
-#define LAN91C96_MMUCR_COMMAND (0xFU << 4)
-#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */
-#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */
-#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */
-#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */
-#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */
-#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */
-#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */
-#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */
-
-/*
- ****************************************************************************
- * Auto Tx Start Register - Bank 2 - Offset 1
- ****************************************************************************
- */
-#define LAN91C96_AUTOTX (0xFFU << 0)
-
-/*
- ****************************************************************************
- * Packet Number Register - Bank 2 - Offset 2
- ****************************************************************************
- */
-#define LAN91C96_PNR_TX (0x1FU << 0)
-
-/*
- ****************************************************************************
- * Allocation Result Register - Bank 2 - Offset 3
- ****************************************************************************
- */
-#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0)
-#define LAN91C96_ARR_FAILED (0x1U << 7)
-
-/*
- ****************************************************************************
- * FIFO Ports Register - Bank 2 - Offset 4
- ****************************************************************************
- */
-#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0)
-#define LAN91C96_FIFO_TEMPTY (0x1U << 7)
-#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8)
-#define LAN91C96_FIFO_RXEMPTY (0x1U << 15)
-
-/*
- ****************************************************************************
- * Pointer Register - Bank 2 - Offset 6
- ****************************************************************************
- */
-#define LAN91C96_PTR_LOW (0xFFU << 0)
-#define LAN91C96_PTR_HIGH (0x7U << 8)
-#define LAN91C96_PTR_AUTO_TX (0x1U << 11)
-#define LAN91C96_PTR_ETEN (0x1U << 12)
-#define LAN91C96_PTR_READ (0x1U << 13)
-#define LAN91C96_PTR_AUTO_INCR (0x1U << 14)
-#define LAN91C96_PTR_RCV (0x1U << 15)
-
-#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \
- LAN91C96_PTR_AUTO_INCR | \
- LAN91C96_PTR_READ)
-
-/*
- ****************************************************************************
- * Data Register - Bank 2 - Offset 8
- ****************************************************************************
- */
-#define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */
-#define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */
-
-/*
- ****************************************************************************
- * Interrupt Status Register - Bank 2 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_IST_RCV_INT (0x1U << 0)
-#define LAN91C96_IST_TX_INT (0x1U << 1)
-#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
-#define LAN91C96_IST_ALLOC_INT (0x1U << 3)
-#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4)
-#define LAN91C96_IST_EPH_INT (0x1U << 5)
-#define LAN91C96_IST_ERCV_INT (0x1U << 6)
-#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7)
-
-/*
- ****************************************************************************
- * Interrupt Acknowledge Register - Bank 2 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_ACK_TX_INT (0x1U << 1)
-#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
-#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4)
-#define LAN91C96_ACK_ERCV_INT (0x1U << 6)
-
-/*
- ****************************************************************************
- * Interrupt Mask Register - Bank 2 - Offset 13
- ****************************************************************************
- */
-#define LAN91C96_MSK_RCV_INT (0x1U << 0)
-#define LAN91C96_MSK_TX_INT (0x1U << 1)
-#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
-#define LAN91C96_MSK_ALLOC_INT (0x1U << 3)
-#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4)
-#define LAN91C96_MSK_EPH_INT (0x1U << 5)
-#define LAN91C96_MSK_ERCV_INT (0x1U << 6)
-#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7)
-
-/*
- ****************************************************************************
- * Bank 3 Register Map in I/O Space
- **************************************************************************
- */
-#define LAN91C96_MGMT_MDO (0x1U << 0)
-#define LAN91C96_MGMT_MDI (0x1U << 1)
-#define LAN91C96_MGMT_MCLK (0x1U << 2)
-#define LAN91C96_MGMT_MDOE (0x1U << 3)
-#define LAN91C96_MGMT_LOW_ID (0x3U << 4)
-#define LAN91C96_MGMT_IOS0 (0x1U << 8)
-#define LAN91C96_MGMT_IOS1 (0x1U << 9)
-#define LAN91C96_MGMT_IOS2 (0x1U << 10)
-#define LAN91C96_MGMT_nXNDEC (0x1U << 11)
-#define LAN91C96_MGMT_HIGH_ID (0x3U << 12)
-
-/*
- ****************************************************************************
- * Revision Register - Bank 3 - Offset 10
- ****************************************************************************
- */
-#define LAN91C96_REV_REVID (0xFU << 0)
-#define LAN91C96_REV_CHIPID (0xFU << 4)
-
-/*
- ****************************************************************************
- * Early RCV Register - Bank 3 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0)
-#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7)
-
-/*
- ****************************************************************************
- * PCMCIA Configuration Registers
- ****************************************************************************
- */
-#define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */
-#define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */
-
-/*
- ****************************************************************************
- * PCMCIA Ethernet Configuration Option Register (ECOR)
- ****************************************************************************
- */
-#define LAN91C96_ECOR_ENABLE (0x1U << 0)
-#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2)
-#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6)
-#define LAN91C96_ECOR_SRESET (0x1U << 7)
-
-/*
- ****************************************************************************
- * PCMCIA Ethernet Configuration and Status Register (ECSR)
- ****************************************************************************
- */
-#define LAN91C96_ECSR_INTR (0x1U << 1)
-#define LAN91C96_ECSR_PWRDWN (0x1U << 2)
-#define LAN91C96_ECSR_IOIS8 (0x1U << 5)
-
-/*
- ****************************************************************************
- * Receive Frame Status Word - See page 38 of the LAN91C96 specification.
- ****************************************************************************
- */
-#define LAN91C96_TOO_SHORT (0x1U << 10)
-#define LAN91C96_TOO_LONG (0x1U << 11)
-#define LAN91C96_ODD_FRM (0x1U << 12)
-#define LAN91C96_BAD_CRC (0x1U << 13)
-#define LAN91C96_BROD_CAST (0x1U << 14)
-#define LAN91C96_ALGN_ERR (0x1U << 15)
-
-#define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR)
-
-/*
- ****************************************************************************
- * Default MAC Address
- ****************************************************************************
- */
-#define MAC_DEF_HI 0x0800
-#define MAC_DEF_MED 0x3333
-#define MAC_DEF_LO 0x0100
-
-/*
- ****************************************************************************
- * Default I/O Signature - 0x33
- ****************************************************************************
- */
-#define LAN91C96_LOW_SIGNATURE (0x33U << 0)
-#define LAN91C96_HIGH_SIGNATURE (0x33U << 8)
-#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
-
-#define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */
-#define ETHERNET_MAX_LENGTH 1514
-
-
-/*-------------------------------------------------------------------------
- * I define some macros to make it easier to do somewhat common
- * or slightly complicated, repeated tasks.
- *-------------------------------------------------------------------------
- */
-
-/* select a register bank, 0 to 3 */
-
-#define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); }
-
-/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(edev, x) {\
- unsigned char mask;\
- SMC_SELECT_BANK(edev, 2);\
- mask = SMC_inb(edev, LAN91C96_INT_MASK);\
- mask |= (x);\
- SMC_outb(edev, mask, LAN91C96_INT_MASK); \
-}
-
-/* this disables an interrupt from the interrupt mask register */
-
-#define SMC_DISABLE_INT(edev, x) {\
- unsigned char mask;\
- SMC_SELECT_BANK(edev, 2);\
- mask = SMC_inb(edev, LAN91C96_INT_MASK);\
- mask &= ~(x);\
- SMC_outb(edev, mask, LAN91C96_INT_MASK); \
-}
-
-/*----------------------------------------------------------------------
- * Define the interrupts that I want to receive from the card
- *
- * I want:
- * LAN91C96_IST_EPH_INT, for nasty errors
- * LAN91C96_IST_RCV_INT, for happy received packets
- * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
- *-------------------------------------------------------------------------
- */
-#define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
-
-#endif /* _LAN91C96_H_ */
+++ /dev/null
-/*
- natsemi.c: A U-Boot driver for the NatSemi DP8381x series.
- Author: Mark A. Rakes (mark_rakes@vivato.net)
-
- Adapted from an Etherboot driver written by:
-
- Copyright (C) 2001 Entity Cyber, Inc.
-
- This development of this Etherboot driver was funded by
-
- Sicom Systems: http://www.sicompos.com/
-
- Author: Marty Connor (mdc@thinguin.org)
- Adapted from a Linux driver which was written by Donald Becker
-
- This software may be used and distributed according to the terms
- of the GNU Public License (GPL), incorporated herein by reference.
-
- Original Copyright Notice:
-
- Written/copyright 1999-2001 by Donald Becker.
-
- This software may be used and distributed according to the terms of
- the GNU General Public License (GPL), incorporated herein by reference.
- Drivers based on or derived from this code fall under the GPL and must
- retain the authorship, copyright and license notice. This file is not
- a complete program and may only be used when the entire operating
- system is licensed under the GPL. License for under other terms may be
- available. Contact the original author for details.
-
- The original author may be reached as becker@scyld.com, or at
- Scyld Computing Corporation
- 410 Severn Ave., Suite 210
- Annapolis MD 21403
-
- Support information and updates available at
- http://www.scyld.com/network/netsemi.html
-
- References:
- http://www.scyld.com/expert/100mbps.html
- http://www.scyld.com/expert/NWay.html
- Datasheet is available from:
- http://www.national.com/pf/DP/DP83815.html
-*/
-
-/* Revision History
- * October 2002 mar 1.0
- * Initial U-Boot Release. Tested with Netgear FA311 board
- * and dp83815 chipset on custom board
-*/
-
-/* Includes */
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <linux/delay.h>
-
-/* defines */
-#define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
-
-#define DSIZE 0x00000FFF
-#define CRC_SIZE 4
-#define TOUT_LOOP 500000
-#define TX_BUF_SIZE 1536
-#define RX_BUF_SIZE 1536
-#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
-
-/* Offsets to the device registers.
- Unlike software-only systems, device drivers interact with complex hardware.
- It's not useful to define symbolic names for every register bit in the
- device. */
-enum register_offsets {
- ChipCmd = 0x00,
- ChipConfig = 0x04,
- EECtrl = 0x08,
- IntrMask = 0x14,
- IntrEnable = 0x18,
- TxRingPtr = 0x20,
- TxConfig = 0x24,
- RxRingPtr = 0x30,
- RxConfig = 0x34,
- ClkRun = 0x3C,
- RxFilterAddr = 0x48,
- RxFilterData = 0x4C,
- SiliconRev = 0x58,
- PCIPM = 0x44,
- BasicControl = 0x80,
- BasicStatus = 0x84,
- /* These are from the spec, around page 78... on a separate table. */
- PGSEL = 0xCC,
- PMDCSR = 0xE4,
- TSTDAT = 0xFC,
- DSPCFG = 0xF4,
- SDCFG = 0x8C
-};
-
-/* Bit in ChipCmd. */
-enum ChipCmdBits {
- ChipReset = 0x100,
- RxReset = 0x20,
- TxReset = 0x10,
- RxOff = 0x08,
- RxOn = 0x04,
- TxOff = 0x02,
- TxOn = 0x01
-};
-
-enum ChipConfigBits {
- LinkSts = 0x80000000,
- HundSpeed = 0x40000000,
- FullDuplex = 0x20000000,
- TenPolarity = 0x10000000,
- AnegDone = 0x08000000,
- AnegEnBothBoth = 0x0000E000,
- AnegDis100Full = 0x0000C000,
- AnegEn100Both = 0x0000A000,
- AnegDis100Half = 0x00008000,
- AnegEnBothHalf = 0x00006000,
- AnegDis10Full = 0x00004000,
- AnegEn10Both = 0x00002000,
- DuplexMask = 0x00008000,
- SpeedMask = 0x00004000,
- AnegMask = 0x00002000,
- AnegDis10Half = 0x00000000,
- ExtPhy = 0x00001000,
- PhyRst = 0x00000400,
- PhyDis = 0x00000200,
- BootRomDisable = 0x00000004,
- BEMode = 0x00000001,
-};
-
-enum TxConfig_bits {
- TxDrthMask = 0x3f,
- TxFlthMask = 0x3f00,
- TxMxdmaMask = 0x700000,
- TxMxdma_512 = 0x0,
- TxMxdma_4 = 0x100000,
- TxMxdma_8 = 0x200000,
- TxMxdma_16 = 0x300000,
- TxMxdma_32 = 0x400000,
- TxMxdma_64 = 0x500000,
- TxMxdma_128 = 0x600000,
- TxMxdma_256 = 0x700000,
- TxCollRetry = 0x800000,
- TxAutoPad = 0x10000000,
- TxMacLoop = 0x20000000,
- TxHeartIgn = 0x40000000,
- TxCarrierIgn = 0x80000000
-};
-
-enum RxConfig_bits {
- RxDrthMask = 0x3e,
- RxMxdmaMask = 0x700000,
- RxMxdma_512 = 0x0,
- RxMxdma_4 = 0x100000,
- RxMxdma_8 = 0x200000,
- RxMxdma_16 = 0x300000,
- RxMxdma_32 = 0x400000,
- RxMxdma_64 = 0x500000,
- RxMxdma_128 = 0x600000,
- RxMxdma_256 = 0x700000,
- RxAcceptLong = 0x8000000,
- RxAcceptTx = 0x10000000,
- RxAcceptRunt = 0x40000000,
- RxAcceptErr = 0x80000000
-};
-
-/* Bits in the RxMode register. */
-enum rx_mode_bits {
- AcceptErr = 0x20,
- AcceptRunt = 0x10,
- AcceptBroadcast = 0xC0000000,
- AcceptMulticast = 0x00200000,
- AcceptAllMulticast = 0x20000000,
- AcceptAllPhys = 0x10000000,
- AcceptMyPhys = 0x08000000
-};
-
-typedef struct _BufferDesc {
- u32 link;
- vu_long cmdsts;
- u32 bufptr;
- u32 software_use;
-} BufferDesc;
-
-/* Bits in network_desc.status */
-enum desc_status_bits {
- DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
- DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
- DescSizeMask = 0xfff,
-
- DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
- DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
- DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
- DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
-
- DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
- DescRxDest = 0x01800000, DescRxLong = 0x00400000,
- DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
- DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
- DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
-};
-
-/* Globals */
-#ifdef NATSEMI_DEBUG
-static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */
-#endif
-static u32 SavedClkRun;
-static unsigned int cur_rx;
-static unsigned int advertising;
-static unsigned int rx_config;
-static unsigned int tx_config;
-
-/* Note: transmit and receive buffers and descriptors must be
- longword aligned */
-static BufferDesc txd __attribute__ ((aligned(4)));
-static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4)));
-
-static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4)));
-static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
- __attribute__ ((aligned(4)));
-
-/* Function Prototypes */
-#if 0
-static void write_eeprom(struct eth_device *dev, long addr, int location,
- short value);
-#endif
-static int read_eeprom(struct eth_device *dev, long addr, int location);
-static int mdio_read(struct eth_device *dev, int phy_id, int location);
-static int natsemi_init(struct eth_device *dev, struct bd_info * bis);
-static void natsemi_reset(struct eth_device *dev);
-static void natsemi_init_rxfilter(struct eth_device *dev);
-static void natsemi_init_txd(struct eth_device *dev);
-static void natsemi_init_rxd(struct eth_device *dev);
-static void natsemi_set_rx_mode(struct eth_device *dev);
-static void natsemi_check_duplex(struct eth_device *dev);
-static int natsemi_send(struct eth_device *dev, void *packet, int length);
-static int natsemi_poll(struct eth_device *dev);
-static void natsemi_disable(struct eth_device *dev);
-
-static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815},
- {}
-};
-
-#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
-
-static inline int
-INW(struct eth_device *dev, u_long addr)
-{
- return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
-}
-
-static int
-INL(struct eth_device *dev, u_long addr)
-{
- return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
-}
-
-static inline void
-OUTW(struct eth_device *dev, int command, u_long addr)
-{
- *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
-}
-
-static inline void
-OUTL(struct eth_device *dev, int command, u_long addr)
-{
- *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
-}
-
-/*
- * Function: natsemi_initialize
- *
- * Description: Retrieves the MAC address of the card, and sets up some
- * globals required by other routines, and initializes the NIC, making it
- * ready to send and receive packets.
- *
- * Side effects:
- * leaves the natsemi initialized, and ready to receive packets.
- *
- * Returns: struct eth_device *: pointer to NIC data structure
- */
-
-int
-natsemi_initialize(struct bd_info * bis)
-{
- pci_dev_t devno;
- int card_number = 0;
- struct eth_device *dev;
- u32 iobase, status, chip_config;
- int i, idx = 0;
- int prev_eedata;
- u32 tmp;
-
- while (1) {
- /* Find PCI device(s) */
- if ((devno = pci_find_devices(supported, idx++)) < 0) {
- break;
- }
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
- iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */
-
- pci_write_config_dword(devno, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Check if I/O accesses and Bus Mastering are enabled. */
- pci_read_config_dword(devno, PCI_COMMAND, &status);
- if (!(status & PCI_COMMAND_MEMORY)) {
- printf("Error: Can not enable MEM access.\n");
- continue;
- } else if (!(status & PCI_COMMAND_MASTER)) {
- printf("Error: Can not enable Bus Mastering.\n");
- continue;
- }
-
- dev = (struct eth_device *) malloc(sizeof *dev);
- if (!dev) {
- printf("natsemi: Can not allocate memory\n");
- break;
- }
- memset(dev, 0, sizeof(*dev));
-
- sprintf(dev->name, "dp83815#%d", card_number);
- dev->iobase = bus_to_phys(iobase);
-#ifdef NATSEMI_DEBUG
- printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase);
-#endif
- dev->priv = (void *) devno;
- dev->init = natsemi_init;
- dev->halt = natsemi_disable;
- dev->send = natsemi_send;
- dev->recv = natsemi_poll;
-
- eth_register(dev);
-
- card_number++;
-
- /* Set the latency timer for value. */
- pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
-
- udelay(10 * 1000);
-
- /* natsemi has a non-standard PM control register
- * in PCI config space. Some boards apparently need
- * to be brought to D0 in this manner. */
- pci_read_config_dword(devno, PCIPM, &tmp);
- if (tmp & (0x03 | 0x100)) {
- /* D0 state, disable PME assertion */
- u32 newtmp = tmp & ~(0x03 | 0x100);
- pci_write_config_dword(devno, PCIPM, newtmp);
- }
-
- printf("natsemi: EEPROM contents:\n");
- for (i = 0; i <= EEPROM_SIZE; i++) {
- short eedata = read_eeprom(dev, EECtrl, i);
- printf(" %04hx", eedata);
- }
- printf("\n");
-
- /* get MAC address */
- prev_eedata = read_eeprom(dev, EECtrl, 6);
- for (i = 0; i < 3; i++) {
- int eedata = read_eeprom(dev, EECtrl, i + 7);
- dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15);
- dev->enetaddr[i*2+1] = eedata >> 7;
- prev_eedata = eedata;
- }
-
- /* Reset the chip to erase any previous misconfiguration. */
- OUTL(dev, ChipReset, ChipCmd);
-
- advertising = mdio_read(dev, 1, 4);
- chip_config = INL(dev, ChipConfig);
-#ifdef NATSEMI_DEBUG
- printf("%s: Transceiver status %#08X advertising %#08X\n",
- dev->name, (int) INL(dev, BasicStatus), advertising);
- printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n",
- dev->name, chip_config & AnegMask ? "enabled, advertise" :
- "disabled, force", chip_config & SpeedMask ? "0" : "",
- chip_config & DuplexMask ? "full" : "half");
-#endif
- chip_config |= AnegEnBothBoth;
-#ifdef NATSEMI_DEBUG
- printf("%s: changed to autoneg. %s 10%s %s duplex.\n",
- dev->name, chip_config & AnegMask ? "enabled, advertise" :
- "disabled, force", chip_config & SpeedMask ? "0" : "",
- chip_config & DuplexMask ? "full" : "half");
-#endif
- /*write new autoneg bits, reset phy*/
- OUTL(dev, (chip_config | PhyRst), ChipConfig);
- /*un-reset phy*/
- OUTL(dev, chip_config, ChipConfig);
-
- /* Disable PME:
- * The PME bit is initialized from the EEPROM contents.
- * PCI cards probably have PME disabled, but motherboard
- * implementations may have PME set to enable WakeOnLan.
- * With PME set the chip will scan incoming packets but
- * nothing will be written to memory. */
- SavedClkRun = INL(dev, ClkRun);
- OUTL(dev, SavedClkRun & ~0x100, ClkRun);
- }
- return card_number;
-}
-
-/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
- The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
-
-/* Delay between EEPROM clock transitions.
- No extra delay is needed with 33MHz PCI, but future 66MHz
- access may need a delay. */
-#define eeprom_delay(ee_addr) INL(dev, ee_addr)
-
-enum EEPROM_Ctrl_Bits {
- EE_ShiftClk = 0x04,
- EE_DataIn = 0x01,
- EE_ChipSelect = 0x08,
- EE_DataOut = 0x02
-};
-
-#define EE_Write0 (EE_ChipSelect)
-#define EE_Write1 (EE_ChipSelect | EE_DataIn)
-/* The EEPROM commands include the alway-set leading bit. */
-enum EEPROM_Cmds {
- EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6),
- EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6),
-};
-
-#if 0
-static void
-write_eeprom(struct eth_device *dev, long addr, int location, short value)
-{
- int i;
- int ee_addr = (typeof(ee_addr))addr;
- short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/
- short write_cmd = location | EE_WriteCmd;
-
-#ifdef NATSEMI_DEBUG
- printf("write_eeprom: %08x, %04hx, %04hx\n",
- dev->iobase + ee_addr, write_cmd, value);
-#endif
- /* Shift the write enable command bits out. */
- for (i = 9; i >= 0; i--) {
- short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
- OUTL(dev, cmdval, ee_addr);
- eeprom_delay(ee_addr);
- OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- }
-
- OUTL(dev, 0, ee_addr); /*bring chip select low*/
- OUTL(dev, EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
-
- /* Shift the write command bits out. */
- for (i = 9; i >= 0; i--) {
- short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
- OUTL(dev, cmdval, ee_addr);
- eeprom_delay(ee_addr);
- OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- }
-
- for (i = 0; i < 16; i++) {
- short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0;
- OUTL(dev, cmdval, ee_addr);
- eeprom_delay(ee_addr);
- OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- }
-
- OUTL(dev, 0, ee_addr); /*bring chip select low*/
- OUTL(dev, EE_ShiftClk, ee_addr);
- for (i = 0; i < 200000; i++) {
- OUTL(dev, EE_Write0, ee_addr); /*poll for done*/
- if (INL(dev, ee_addr) & EE_DataOut) {
- break; /*finished*/
- }
- }
- eeprom_delay(ee_addr);
-
- /* Terminate the EEPROM access. */
- OUTL(dev, EE_Write0, ee_addr);
- OUTL(dev, 0, ee_addr);
- return;
-}
-#endif
-
-static int
-read_eeprom(struct eth_device *dev, long addr, int location)
-{
- int i;
- int retval = 0;
- int ee_addr = (typeof(ee_addr))addr;
- int read_cmd = location | EE_ReadCmd;
-
- OUTL(dev, EE_Write0, ee_addr);
-
- /* Shift the read command bits out. */
- for (i = 10; i >= 0; i--) {
- short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
- OUTL(dev, dataval, ee_addr);
- eeprom_delay(ee_addr);
- OUTL(dev, dataval | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- }
- OUTL(dev, EE_ChipSelect, ee_addr);
- eeprom_delay(ee_addr);
-
- for (i = 0; i < 16; i++) {
- OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0;
- OUTL(dev, EE_ChipSelect, ee_addr);
- eeprom_delay(ee_addr);
- }
-
- /* Terminate the EEPROM access. */
- OUTL(dev, EE_Write0, ee_addr);
- OUTL(dev, 0, ee_addr);
-#ifdef NATSEMI_DEBUG
- if (natsemi_debug)
- printf("read_eeprom: %08x, %08x, retval %08x\n",
- dev->iobase + ee_addr, read_cmd, retval);
-#endif
- return retval;
-}
-
-/* MII transceiver control section.
- The 83815 series has an internal transceiver, and we present the
- management registers as if they were MII connected. */
-
-static int
-mdio_read(struct eth_device *dev, int phy_id, int location)
-{
- if (phy_id == 1 && location < 32)
- return INL(dev, BasicControl+(location<<2))&0xffff;
- else
- return 0xffff;
-}
-
-/* Function: natsemi_init
- *
- * Description: resets the ethernet controller chip and configures
- * registers and data structures required for sending and receiving packets.
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * returns: int.
- */
-
-static int
-natsemi_init(struct eth_device *dev, struct bd_info * bis)
-{
-
- natsemi_reset(dev);
-
- /* Disable PME:
- * The PME bit is initialized from the EEPROM contents.
- * PCI cards probably have PME disabled, but motherboard
- * implementations may have PME set to enable WakeOnLan.
- * With PME set the chip will scan incoming packets but
- * nothing will be written to memory. */
- OUTL(dev, SavedClkRun & ~0x100, ClkRun);
-
- natsemi_init_rxfilter(dev);
- natsemi_init_txd(dev);
- natsemi_init_rxd(dev);
-
- /* Configure the PCI bus bursts and FIFO thresholds. */
- tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
- rx_config = RxMxdma_256 | 0x20;
-
-#ifdef NATSEMI_DEBUG
- printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
- printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
-#endif
- OUTL(dev, tx_config, TxConfig);
- OUTL(dev, rx_config, RxConfig);
-
- natsemi_check_duplex(dev);
- natsemi_set_rx_mode(dev);
-
- OUTL(dev, (RxOn | TxOn), ChipCmd);
- return 1;
-}
-
-/*
- * Function: natsemi_reset
- *
- * Description: soft resets the controller chip
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: void.
- */
-static void
-natsemi_reset(struct eth_device *dev)
-{
- OUTL(dev, ChipReset, ChipCmd);
-
- /* On page 78 of the spec, they recommend some settings for "optimum
- performance" to be done in sequence. These settings optimize some
- of the 100Mbit autodetection circuitry. Also, we only want to do
- this for rev C of the chip. */
- if (INL(dev, SiliconRev) == 0x302) {
- OUTW(dev, 0x0001, PGSEL);
- OUTW(dev, 0x189C, PMDCSR);
- OUTW(dev, 0x0000, TSTDAT);
- OUTW(dev, 0x5040, DSPCFG);
- OUTW(dev, 0x008C, SDCFG);
- }
- /* Disable interrupts using the mask. */
- OUTL(dev, 0, IntrMask);
- OUTL(dev, 0, IntrEnable);
-}
-
-/* Function: natsemi_init_rxfilter
- *
- * Description: sets receive filter address to our MAC address
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * returns: void.
- */
-
-static void
-natsemi_init_rxfilter(struct eth_device *dev)
-{
- int i;
-
- for (i = 0; i < ETH_ALEN; i += 2) {
- OUTL(dev, i, RxFilterAddr);
- OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
- RxFilterData);
- }
-}
-
-/*
- * Function: natsemi_init_txd
- *
- * Description: initializes the Tx descriptor
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * returns: void.
- */
-
-static void
-natsemi_init_txd(struct eth_device *dev)
-{
- txd.link = (u32) 0;
- txd.cmdsts = (u32) 0;
- txd.bufptr = (u32) & txb[0];
-
- /* load Transmit Descriptor Register */
- OUTL(dev, (u32) & txd, TxRingPtr);
-#ifdef NATSEMI_DEBUG
- printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n",
- INL(dev, TxRingPtr));
-#endif
-}
-
-/* Function: natsemi_init_rxd
- *
- * Description: initializes the Rx descriptor ring
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: void.
- */
-
-static void
-natsemi_init_rxd(struct eth_device *dev)
-{
- int i;
-
- cur_rx = 0;
-
- /* init RX descriptor */
- for (i = 0; i < NUM_RX_DESC; i++) {
- rxd[i].link =
- cpu_to_le32((i + 1 <
- NUM_RX_DESC) ? (u32) & rxd[i +
- 1] : (u32) &
- rxd[0]);
- rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
- rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
-#ifdef NATSEMI_DEBUG
- printf
- ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n",
- i, &rxd[i], le32_to_cpu(rxd[i].link),
- rxd[i].cmdsts, rxd[i].bufptr);
-#endif
- }
-
- /* load Receive Descriptor Register */
- OUTL(dev, (u32) & rxd[0], RxRingPtr);
-
-#ifdef NATSEMI_DEBUG
- printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n",
- INL(dev, RxRingPtr));
-#endif
-}
-
-/* Function: natsemi_set_rx_mode
- *
- * Description:
- * sets the receive mode to accept all broadcast packets and packets
- * with our MAC address, and reject all multicast packets.
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: void.
- */
-
-static void
-natsemi_set_rx_mode(struct eth_device *dev)
-{
- u32 rx_mode = AcceptBroadcast | AcceptMyPhys;
-
- OUTL(dev, rx_mode, RxFilterAddr);
-}
-
-static void
-natsemi_check_duplex(struct eth_device *dev)
-{
- int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0;
-
-#ifdef NATSEMI_DEBUG
- printf("%s: Setting %s-duplex based on negotiated link"
- " capability.\n", dev->name, duplex ? "full" : "half");
-#endif
- if (duplex) {
- rx_config |= RxAcceptTx;
- tx_config |= (TxCarrierIgn | TxHeartIgn);
- } else {
- rx_config &= ~RxAcceptTx;
- tx_config &= ~(TxCarrierIgn | TxHeartIgn);
- }
- OUTL(dev, tx_config, TxConfig);
- OUTL(dev, rx_config, RxConfig);
-}
-
-/* Function: natsemi_send
- *
- * Description: transmits a packet and waits for completion or timeout.
- *
- * Returns: void. */
-static int natsemi_send(struct eth_device *dev, void *packet, int length)
-{
- u32 i, status = 0;
- u32 tx_status = 0;
- u32 *tx_ptr = &tx_status;
- vu_long *res = (vu_long *)tx_ptr;
-
- /* Stop the transmitter */
- OUTL(dev, TxOff, ChipCmd);
-
-#ifdef NATSEMI_DEBUG
- if (natsemi_debug)
- printf("natsemi_send: sending %d bytes\n", (int) length);
-#endif
-
- /* set the transmit buffer descriptor and enable Transmit State Machine */
- txd.link = cpu_to_le32(0);
- txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet));
- txd.cmdsts = cpu_to_le32(DescOwn | length);
-
- /* load Transmit Descriptor Register */
- OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
-#ifdef NATSEMI_DEBUG
- if (natsemi_debug)
- printf("natsemi_send: TX descriptor register loaded with: %#08X\n",
- INL(dev, TxRingPtr));
-#endif
- /* restart the transmitter */
- OUTL(dev, TxOn, ChipCmd);
-
- for (i = 0;
- (*res = le32_to_cpu(txd.cmdsts)) & DescOwn;
- i++) {
- if (i >= TOUT_LOOP) {
- printf
- ("%s: tx error buffer not ready: txd.cmdsts == %#X\n",
- dev->name, tx_status);
- goto Done;
- }
- }
-
- if (!(tx_status & DescPktOK)) {
- printf("natsemi_send: Transmit error, Tx status %X.\n",
- tx_status);
- goto Done;
- }
-
- status = 1;
- Done:
- return status;
-}
-
-/* Function: natsemi_poll
- *
- * Description: checks for a received packet and returns it if found.
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: 1 if packet was received.
- * 0 if no packet was received.
- *
- * Side effects:
- * Returns (copies) the packet to the array dev->packet.
- * Returns the length of the packet.
- */
-
-static int
-natsemi_poll(struct eth_device *dev)
-{
- int retstat = 0;
- int length = 0;
- u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
-
- if (!(rx_status & (u32) DescOwn))
- return retstat;
-#ifdef NATSEMI_DEBUG
- if (natsemi_debug)
- printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n",
- cur_rx, rx_status);
-#endif
- length = (rx_status & DSIZE) - CRC_SIZE;
-
- if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
- printf
- ("natsemi_poll: Corrupted packet received, buffer status = %X\n",
- rx_status);
- retstat = 0;
- } else { /* give packet to higher level routine */
- net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE),
- length);
- retstat = 1;
- }
-
- /* return the descriptor and buffer to receive ring */
- rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
- rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
-
- if (++cur_rx == NUM_RX_DESC)
- cur_rx = 0;
-
- /* re-enable the potentially idle receive state machine */
- OUTL(dev, RxOn, ChipCmd);
-
- return retstat;
-}
-
-/* Function: natsemi_disable
- *
- * Description: Turns off interrupts and stops Tx and Rx engines
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: void.
- */
-
-static void
-natsemi_disable(struct eth_device *dev)
-{
- /* Disable interrupts using the mask. */
- OUTL(dev, 0, IntrMask);
- OUTL(dev, 0, IntrEnable);
-
- /* Stop the chip's Tx and Rx processes. */
- OUTL(dev, RxOff | TxOff, ChipCmd);
-
- /* Restore PME enable bit */
- OUTL(dev, SavedClkRun, ClkRun);
-}
+++ /dev/null
-/*
- ns8382x.c: A U-Boot driver for the NatSemi DP8382[01].
- ported by: Mark A. Rakes (mark_rakes@vivato.net)
-
- Adapted from:
- 1. an Etherboot driver for DP8381[56] written by:
- Copyright (C) 2001 Entity Cyber, Inc.
-
- This development of this Etherboot driver was funded by
- Sicom Systems: http://www.sicompos.com/
-
- Author: Marty Connor (mdc@thinguin.org)
- Adapted from a Linux driver which was written by Donald Becker
-
- This software may be used and distributed according to the terms
- of the GNU Public License (GPL), incorporated herein by reference.
-
- 2. A Linux driver by Donald Becker, ns820.c:
- Written/copyright 1999-2002 by Donald Becker.
-
- This software may be used and distributed according to the terms of
- the GNU General Public License (GPL), incorporated herein by reference.
- Drivers based on or derived from this code fall under the GPL and must
- retain the authorship, copyright and license notice. This file is not
- a complete program and may only be used when the entire operating
- system is licensed under the GPL. License for under other terms may be
- available. Contact the original author for details.
-
- The original author may be reached as becker@scyld.com, or at
- Scyld Computing Corporation
- 410 Severn Ave., Suite 210
- Annapolis MD 21403
-
- Support information and updates available at
- http://www.scyld.com/network/netsemi.html
-
- Datasheets available from:
- http://www.national.com/pf/DP/DP83820.html
- http://www.national.com/pf/DP/DP83821.html
-*/
-
-/* Revision History
- * October 2002 mar 1.0
- * Initial U-Boot Release.
- * Tested with Netgear GA622T (83820)
- * and SMC9452TX (83821)
- * NOTE: custom boards with these chips may (likely) require
- * a programmed EEPROM device (if present) in order to work
- * correctly.
-*/
-
-/* Includes */
-#include <common.h>
-#include <log.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <linux/delay.h>
-
-/* defines */
-#define DSIZE 0x00000FFF
-#define CRC_SIZE 4
-#define TOUT_LOOP 500000
-#define TX_BUF_SIZE 1536
-#define RX_BUF_SIZE 1536
-#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
-
-enum register_offsets {
- ChipCmd = 0x00,
- ChipConfig = 0x04,
- EECtrl = 0x08,
- IntrMask = 0x14,
- IntrEnable = 0x18,
- TxRingPtr = 0x20,
- TxRingPtrHi = 0x24,
- TxConfig = 0x28,
- RxRingPtr = 0x30,
- RxRingPtrHi = 0x34,
- RxConfig = 0x38,
- PriQueue = 0x3C,
- RxFilterAddr = 0x48,
- RxFilterData = 0x4C,
- ClkRun = 0xCC,
- PCIPM = 0x44,
-};
-
-enum ChipCmdBits {
- ChipReset = 0x100,
- RxReset = 0x20,
- TxReset = 0x10,
- RxOff = 0x08,
- RxOn = 0x04,
- TxOff = 0x02,
- TxOn = 0x01
-};
-
-enum ChipConfigBits {
- LinkSts = 0x80000000,
- GigSpeed = 0x40000000,
- HundSpeed = 0x20000000,
- FullDuplex = 0x10000000,
- TBIEn = 0x01000000,
- Mode1000 = 0x00400000,
- T64En = 0x00004000,
- D64En = 0x00001000,
- M64En = 0x00000800,
- PhyRst = 0x00000400,
- PhyDis = 0x00000200,
- ExtStEn = 0x00000100,
- BEMode = 0x00000001,
-};
-#define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex)
-
-enum TxConfig_bits {
- TxDrthMask = 0x000000ff,
- TxFlthMask = 0x0000ff00,
- TxMxdmaMask = 0x00700000,
- TxMxdma_8 = 0x00100000,
- TxMxdma_16 = 0x00200000,
- TxMxdma_32 = 0x00300000,
- TxMxdma_64 = 0x00400000,
- TxMxdma_128 = 0x00500000,
- TxMxdma_256 = 0x00600000,
- TxMxdma_512 = 0x00700000,
- TxMxdma_1024 = 0x00000000,
- TxCollRetry = 0x00800000,
- TxAutoPad = 0x10000000,
- TxMacLoop = 0x20000000,
- TxHeartIgn = 0x40000000,
- TxCarrierIgn = 0x80000000
-};
-
-enum RxConfig_bits {
- RxDrthMask = 0x0000003e,
- RxMxdmaMask = 0x00700000,
- RxMxdma_8 = 0x00100000,
- RxMxdma_16 = 0x00200000,
- RxMxdma_32 = 0x00300000,
- RxMxdma_64 = 0x00400000,
- RxMxdma_128 = 0x00500000,
- RxMxdma_256 = 0x00600000,
- RxMxdma_512 = 0x00700000,
- RxMxdma_1024 = 0x00000000,
- RxAcceptLenErr = 0x04000000,
- RxAcceptLong = 0x08000000,
- RxAcceptTx = 0x10000000,
- RxStripCRC = 0x20000000,
- RxAcceptRunt = 0x40000000,
- RxAcceptErr = 0x80000000,
-};
-
-/* Bits in the RxMode register. */
-enum rx_mode_bits {
- RxFilterEnable = 0x80000000,
- AcceptAllBroadcast = 0x40000000,
- AcceptAllMulticast = 0x20000000,
- AcceptAllUnicast = 0x10000000,
- AcceptPerfectMatch = 0x08000000,
-};
-
-typedef struct _BufferDesc {
- u32 link;
- u32 bufptr;
- vu_long cmdsts;
- u32 extsts; /*not used here */
-} BufferDesc;
-
-/* Bits in network_desc.status */
-enum desc_status_bits {
- DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
- DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
- DescSizeMask = 0xfff,
-
- DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
- DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
- DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
- DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
-
- DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
- DescRxDest = 0x01800000, DescRxLong = 0x00400000,
- DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
- DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
- DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
-};
-
-/* Bits in MEAR */
-enum mii_reg_bits {
- MDIO_ShiftClk = 0x0040,
- MDIO_EnbOutput = 0x0020,
- MDIO_Data = 0x0010,
-};
-
-/* PHY Register offsets. */
-enum phy_reg_offsets {
- BMCR = 0x00,
- BMSR = 0x01,
- PHYIDR1 = 0x02,
- PHYIDR2 = 0x03,
- ANAR = 0x04,
- KTCR = 0x09,
-};
-
-/* basic mode control register bits */
-enum bmcr_bits {
- Bmcr_Reset = 0x8000,
- Bmcr_Loop = 0x4000,
- Bmcr_Speed0 = 0x2000,
- Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */
- Bmcr_RstAutoNeg = 0x0200,
- Bmcr_Duplex = 0x0100,
- Bmcr_Speed1 = 0x0040,
- Bmcr_Force10H = 0x0000,
- Bmcr_Force10F = 0x0100,
- Bmcr_Force100H = 0x2000,
- Bmcr_Force100F = 0x2100,
- Bmcr_Force1000H = 0x0040,
- Bmcr_Force1000F = 0x0140,
-};
-
-/* auto negotiation advertisement register */
-enum anar_bits {
- anar_adv_100F = 0x0100,
- anar_adv_100H = 0x0080,
- anar_adv_10F = 0x0040,
- anar_adv_10H = 0x0020,
- anar_ieee_8023 = 0x0001,
-};
-
-/* 1K-base T control register */
-enum ktcr_bits {
- ktcr_adv_1000H = 0x0100,
- ktcr_adv_1000F = 0x0200,
-};
-
-/* Globals */
-static u32 SavedClkRun;
-static unsigned int cur_rx;
-static unsigned int rx_config;
-static unsigned int tx_config;
-
-/* Note: transmit and receive buffers and descriptors must be
- long long word aligned */
-static BufferDesc txd __attribute__ ((aligned(8)));
-static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8)));
-static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8)));
-static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
- __attribute__ ((aligned(8)));
-
-/* Function Prototypes */
-static int mdio_read(struct eth_device *dev, int phy_id, int addr);
-static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value);
-static void mdio_sync(struct eth_device *dev, u32 offset);
-static int ns8382x_init(struct eth_device *dev, struct bd_info * bis);
-static void ns8382x_reset(struct eth_device *dev);
-static void ns8382x_init_rxfilter(struct eth_device *dev);
-static void ns8382x_init_txd(struct eth_device *dev);
-static void ns8382x_init_rxd(struct eth_device *dev);
-static void ns8382x_set_rx_mode(struct eth_device *dev);
-static void ns8382x_check_duplex(struct eth_device *dev);
-static int ns8382x_send(struct eth_device *dev, void *packet, int length);
-static int ns8382x_poll(struct eth_device *dev);
-static void ns8382x_disable(struct eth_device *dev);
-
-static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820},
- {}
-};
-
-#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
-
-static inline int
-INW(struct eth_device *dev, u_long addr)
-{
- return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
-}
-
-static int
-INL(struct eth_device *dev, u_long addr)
-{
- return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
-}
-
-static inline void
-OUTW(struct eth_device *dev, int command, u_long addr)
-{
- *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
-}
-
-static inline void
-OUTL(struct eth_device *dev, int command, u_long addr)
-{
- *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
-}
-
-/* Function: ns8382x_initialize
- * Description: Retrieves the MAC address of the card, and sets up some
- * globals required by other routines, and initializes the NIC, making it
- * ready to send and receive packets.
- * Side effects: initializes ns8382xs, ready to receive packets.
- * Returns: int: number of cards found
- */
-
-int
-ns8382x_initialize(struct bd_info * bis)
-{
- pci_dev_t devno;
- int card_number = 0;
- struct eth_device *dev;
- u32 iobase, status;
- int i, idx = 0;
- u32 phyAddress;
- u32 tmp;
- u32 chip_config;
-
- while (1) { /* Find PCI device(s) */
- if ((devno = pci_find_devices(supported, idx++)) < 0)
- break;
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
- iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
-
- debug("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase);
-
- pci_write_config_dword(devno, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Check if I/O accesses and Bus Mastering are enabled. */
- pci_read_config_dword(devno, PCI_COMMAND, &status);
- if (!(status & PCI_COMMAND_MEMORY)) {
- printf("Error: Can not enable MEM access.\n");
- continue;
- } else if (!(status & PCI_COMMAND_MASTER)) {
- printf("Error: Can not enable Bus Mastering.\n");
- continue;
- }
-
- dev = (struct eth_device *) malloc(sizeof *dev);
- if (!dev) {
- printf("ns8382x: Can not allocate memory\n");
- break;
- }
- memset(dev, 0, sizeof(*dev));
-
- sprintf(dev->name, "dp8382x#%d", card_number);
- dev->iobase = bus_to_phys(iobase);
- dev->priv = (void *) devno;
- dev->init = ns8382x_init;
- dev->halt = ns8382x_disable;
- dev->send = ns8382x_send;
- dev->recv = ns8382x_poll;
-
- /* ns8382x has a non-standard PM control register
- * in PCI config space. Some boards apparently need
- * to be brought to D0 in this manner. */
- pci_read_config_dword(devno, PCIPM, &tmp);
- if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */
- u32 newtmp = tmp & ~(0x03 | 0x100);
- pci_write_config_dword(devno, PCIPM, newtmp);
- }
-
- /* get MAC address */
- for (i = 0; i < 3; i++) {
- u32 data;
- char *mac = (char *)&dev->enetaddr[i * 2];
-
- OUTL(dev, i * 2, RxFilterAddr);
- data = INL(dev, RxFilterData);
- *mac++ = data;
- *mac++ = data >> 8;
- }
- /* get PHY address, can't be zero */
- for (phyAddress = 1; phyAddress < 32; phyAddress++) {
- u32 rev, phy1;
-
- phy1 = mdio_read(dev, phyAddress, PHYIDR1);
- if (phy1 == 0x2000) { /*check for 83861/91 */
- rev = mdio_read(dev, phyAddress, PHYIDR2);
- if ((rev & ~(0x000f)) == 0x00005c50 ||
- (rev & ~(0x000f)) == 0x00005c60) {
- debug("phy rev is %x\n", rev);
- debug("phy address is %x\n",
- phyAddress);
- break;
- }
- }
- }
-
- /* set phy to autonegotiate && advertise everything */
- mdio_write(dev, phyAddress, KTCR,
- (ktcr_adv_1000H | ktcr_adv_1000F));
- mdio_write(dev, phyAddress, ANAR,
- (anar_adv_100F | anar_adv_100H | anar_adv_10H |
- anar_adv_10F | anar_ieee_8023));
- mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */
- mdio_write(dev, phyAddress, BMCR,
- (Bmcr_AutoNegEn | Bmcr_RstAutoNeg));
- /* Reset the chip to erase any previous misconfiguration. */
- OUTL(dev, (ChipReset), ChipCmd);
-
- chip_config = INL(dev, ChipConfig);
- /* reset the phy */
- OUTL(dev, (chip_config | PhyRst), ChipConfig);
- /* power up and initialize transceiver */
- OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig);
-
- mdio_sync(dev, EECtrl);
-
- {
- u32 chpcfg =
- INL(dev, ChipConfig) ^ SpeedStatus_Polarity;
-
- debug("%s: Transceiver 10%s %s duplex.\n", dev->name,
- (chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed)
- ? "0" : "",
- chpcfg & FullDuplex ? "full" : "half");
- debug("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
- dev->enetaddr[0], dev->enetaddr[1],
- dev->enetaddr[2], dev->enetaddr[3],
- dev->enetaddr[4], dev->enetaddr[5]);
- }
-
- /* Disable PME:
- * The PME bit is initialized from the EEPROM contents.
- * PCI cards probably have PME disabled, but motherboard
- * implementations may have PME set to enable WakeOnLan.
- * With PME set the chip will scan incoming packets but
- * nothing will be written to memory. */
- SavedClkRun = INL(dev, ClkRun);
- OUTL(dev, SavedClkRun & ~0x100, ClkRun);
-
- eth_register(dev);
-
- card_number++;
-
- pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60);
-
- udelay(10 * 1000);
- }
- return card_number;
-}
-
-/* MII transceiver control section.
- Read and write MII registers using software-generated serial MDIO
- protocol. See the MII specifications or DP83840A data sheet for details.
-
- The maximum data clock rate is 2.5 MHz. To meet minimum timing we
- must flush writes to the PCI bus with a PCI read. */
-#define mdio_delay(mdio_addr) INL(dev, mdio_addr)
-
-#define MDIO_EnbIn (0)
-#define MDIO_WRITE0 (MDIO_EnbOutput)
-#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
-
-/* Generate the preamble required for initial synchronization and
- a few older transceivers. */
-static void
-mdio_sync(struct eth_device *dev, u32 offset)
-{
- int bits = 32;
-
- /* Establish sync by sending at least 32 logic ones. */
- while (--bits >= 0) {
- OUTL(dev, MDIO_WRITE1, offset);
- mdio_delay(offset);
- OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset);
- mdio_delay(offset);
- }
-}
-
-static int
-mdio_read(struct eth_device *dev, int phy_id, int addr)
-{
- int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr;
- int i, retval = 0;
-
- /* Shift the read command bits out. */
- for (i = 15; i >= 0; i--) {
- int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
-
- OUTL(dev, dataval, EECtrl);
- mdio_delay(EECtrl);
- OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
- mdio_delay(EECtrl);
- }
- /* Read the two transition, 16 data, and wire-idle bits. */
- for (i = 19; i > 0; i--) {
- OUTL(dev, MDIO_EnbIn, EECtrl);
- mdio_delay(EECtrl);
- retval =
- (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0);
- OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
- mdio_delay(EECtrl);
- }
- return (retval >> 1) & 0xffff;
-}
-
-static void
-mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
-{
- int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value;
- int i;
-
- /* Shift the command bits out. */
- for (i = 31; i >= 0; i--) {
- int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
-
- OUTL(dev, dataval, EECtrl);
- mdio_delay(EECtrl);
- OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
- mdio_delay(EECtrl);
- }
- /* Clear out extra bits. */
- for (i = 2; i > 0; i--) {
- OUTL(dev, MDIO_EnbIn, EECtrl);
- mdio_delay(EECtrl);
- OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
- mdio_delay(EECtrl);
- }
- return;
-}
-
-/* Function: ns8382x_init
- * Description: resets the ethernet controller chip and configures
- * registers and data structures required for sending and receiving packets.
- * Arguments: struct eth_device *dev: NIC data structure
- * returns: int.
- */
-
-static int
-ns8382x_init(struct eth_device *dev, struct bd_info * bis)
-{
- u32 config;
-
- ns8382x_reset(dev);
-
- /* Disable PME:
- * The PME bit is initialized from the EEPROM contents.
- * PCI cards probably have PME disabled, but motherboard
- * implementations may have PME set to enable WakeOnLan.
- * With PME set the chip will scan incoming packets but
- * nothing will be written to memory. */
- OUTL(dev, SavedClkRun & ~0x100, ClkRun);
-
- ns8382x_init_rxfilter(dev);
- ns8382x_init_txd(dev);
- ns8382x_init_rxd(dev);
-
- /*set up ChipConfig */
- config = INL(dev, ChipConfig);
- /*turn off 64 bit ops && Ten-bit interface
- * && big-endian mode && extended status */
- config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn);
- OUTL(dev, config, ChipConfig);
-
- /* Configure the PCI bus bursts and FIFO thresholds. */
- tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad
- | TxCollRetry | TxMxdma_1024 | (0x1002);
- rx_config = RxMxdma_1024 | 0x20;
-
- debug("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
- debug("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
-
- OUTL(dev, tx_config, TxConfig);
- OUTL(dev, rx_config, RxConfig);
-
- /*turn off priority queueing */
- OUTL(dev, 0x0, PriQueue);
-
- ns8382x_check_duplex(dev);
- ns8382x_set_rx_mode(dev);
-
- OUTL(dev, (RxOn | TxOn), ChipCmd);
- return 1;
-}
-
-/* Function: ns8382x_reset
- * Description: soft resets the controller chip
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: void.
- */
-static void
-ns8382x_reset(struct eth_device *dev)
-{
- OUTL(dev, ChipReset, ChipCmd);
- while (INL(dev, ChipCmd))
- /*wait until done */ ;
- OUTL(dev, 0, IntrMask);
- OUTL(dev, 0, IntrEnable);
-}
-
-/* Function: ns8382x_init_rxfilter
- * Description: sets receive filter address to our MAC address
- * Arguments: struct eth_device *dev: NIC data structure
- * returns: void.
- */
-
-static void
-ns8382x_init_rxfilter(struct eth_device *dev)
-{
- int i;
-
- for (i = 0; i < ETH_ALEN; i += 2) {
- OUTL(dev, i, RxFilterAddr);
- OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
- RxFilterData);
- }
-}
-
-/* Function: ns8382x_init_txd
- * Description: initializes the Tx descriptor
- * Arguments: struct eth_device *dev: NIC data structure
- * returns: void.
- */
-
-static void
-ns8382x_init_txd(struct eth_device *dev)
-{
- txd.link = (u32) 0;
- txd.bufptr = cpu_to_le32((u32) & txb[0]);
- txd.cmdsts = (u32) 0;
- txd.extsts = (u32) 0;
-
- OUTL(dev, 0x0, TxRingPtrHi);
- OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
-
- debug("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n",
- INL(dev, TxRingPtr), &txd);
-}
-
-/* Function: ns8382x_init_rxd
- * Description: initializes the Rx descriptor ring
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: void.
- */
-
-static void
-ns8382x_init_rxd(struct eth_device *dev)
-{
- int i;
-
- OUTL(dev, 0x0, RxRingPtrHi);
-
- cur_rx = 0;
- for (i = 0; i < NUM_RX_DESC; i++) {
- rxd[i].link =
- cpu_to_le32((i + 1 <
- NUM_RX_DESC) ? (u32) & rxd[i +
- 1] : (u32) &
- rxd[0]);
- rxd[i].extsts = cpu_to_le32((u32) 0x0);
- rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
- rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
-
- debug
- ("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
- i, &rxd[i], le32_to_cpu(rxd[i].link),
- le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
- }
- OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr);
-
- debug("ns8382x_init_rxd: RX descriptor register loaded with: %X\n",
- INL(dev, RxRingPtr));
-}
-
-/* Function: ns8382x_set_rx_mode
- * Description:
- * sets the receive mode to accept all broadcast packets and packets
- * with our MAC address, and reject all multicast packets.
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: void.
- */
-
-static void
-ns8382x_set_rx_mode(struct eth_device *dev)
-{
- u32 rx_mode = 0x0;
- /*spec says RxFilterEnable has to be 0 for rest of
- * this stuff to be properly configured. Linux driver
- * seems to support this*/
-/* OUTL(dev, rx_mode, RxFilterAddr);*/
- rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch);
- OUTL(dev, rx_mode, RxFilterAddr);
- printf("ns8382x_set_rx_mode: set to %X\n", rx_mode);
- /*now we turn RxFilterEnable back on */
- /*rx_mode |= RxFilterEnable;
- OUTL(dev, rx_mode, RxFilterAddr);*/
-}
-
-static void
-ns8382x_check_duplex(struct eth_device *dev)
-{
- int gig = 0;
- int hun = 0;
- int duplex = 0;
- int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity);
-
- duplex = (config & FullDuplex) ? 1 : 0;
- gig = (config & GigSpeed) ? 1 : 0;
- hun = (config & HundSpeed) ? 1 : 0;
-
- debug("%s: Setting 10%s %s-duplex based on negotiated link"
- " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
- duplex ? "full" : "half");
-
- if (duplex) {
- rx_config |= RxAcceptTx;
- tx_config |= (TxCarrierIgn | TxHeartIgn);
- } else {
- rx_config &= ~RxAcceptTx;
- tx_config &= ~(TxCarrierIgn | TxHeartIgn);
- }
-
- debug("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
- debug("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
-
- OUTL(dev, tx_config, TxConfig);
- OUTL(dev, rx_config, RxConfig);
-
- /*if speed is 10 or 100, remove MODE1000,
- * if it's 1000, then set it */
- config = INL(dev, ChipConfig);
- if (gig)
- config |= Mode1000;
- else
- config &= ~Mode1000;
-
- debug("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns");
-
- OUTL(dev, config, ChipConfig);
-}
-
-/* Function: ns8382x_send
- * Description: transmits a packet and waits for completion or timeout.
- * Returns: void. */
-static int ns8382x_send(struct eth_device *dev, void *packet, int length)
-{
- u32 i, status = 0;
- vu_long tx_stat = 0;
-
- /* Stop the transmitter */
- OUTL(dev, TxOff, ChipCmd);
-
- debug("ns8382x_send: sending %d bytes\n", (int)length);
-
- /* set the transmit buffer descriptor and enable Transmit State Machine */
- txd.link = cpu_to_le32(0x0);
- txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet));
- txd.extsts = cpu_to_le32(0x0);
- txd.cmdsts = cpu_to_le32(DescOwn | length);
-
- /* load Transmit Descriptor Register */
- OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
-
- debug("ns8382x_send: TX descriptor register loaded with: %#08X\n",
- INL(dev, TxRingPtr));
- debug("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n",
- le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
- le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
-
- /* restart the transmitter */
- OUTL(dev, TxOn, ChipCmd);
-
- for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
- if (i >= TOUT_LOOP) {
- printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n",
- dev->name, tx_stat);
- goto Done;
- }
- }
-
- if (!(tx_stat & DescPktOK)) {
- printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat);
- goto Done;
- }
-
- debug("ns8382x_send: tx_stat: %#08lX\n", tx_stat);
-
- status = 1;
-Done:
- return status;
-}
-
-/* Function: ns8382x_poll
- * Description: checks for a received packet and returns it if found.
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: 1 if packet was received.
- * 0 if no packet was received.
- * Side effects:
- * Returns (copies) the packet to the array dev->packet.
- * Returns the length of the packet.
- */
-
-static int
-ns8382x_poll(struct eth_device *dev)
-{
- int retstat = 0;
- int length = 0;
- vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
-
- if (!(rx_status & (u32) DescOwn))
- return retstat;
-
- debug("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n",
- cur_rx, rx_status);
-
- length = (rx_status & DSIZE) - CRC_SIZE;
-
- if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
- /* corrupted packet received */
- printf("ns8382x_poll: Corrupted packet, status:%lx\n",
- rx_status);
- retstat = 0;
- } else {
- /* give packet to higher level routine */
- net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE),
- length);
- retstat = 1;
- }
-
- /* return the descriptor and buffer to receive ring */
- rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
- rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
-
- if (++cur_rx == NUM_RX_DESC)
- cur_rx = 0;
-
- /* re-enable the potentially idle receive state machine */
- OUTL(dev, RxOn, ChipCmd);
-
- return retstat;
-}
-
-/* Function: ns8382x_disable
- * Description: Turns off interrupts and stops Tx and Rx engines
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: void.
- */
-
-static void
-ns8382x_disable(struct eth_device *dev)
-{
- /* Disable interrupts using the mask. */
- OUTL(dev, 0, IntrMask);
- OUTL(dev, 0, IntrEnable);
-
- /* Stop the chip's Tx and Rx processes. */
- OUTL(dev, (RxOff | TxOff), ChipCmd);
-
- /* Restore PME enable bit */
- OUTL(dev, SavedClkRun, ClkRun);
-}
Enable support for NXP C45 TJA11XX PHYs.
Currently supports only the TJA1103 PHY.
+config PHY_NXP_TJA11XX
+ bool "NXP TJA11XX Ethernet PHYs support"
+ help
+ Currently supports the NXP TJA1100 and TJA1101 PHY.
+
config PHY_REALTEK
bool "Realtek Ethernet PHYs support"
obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
+obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
#include <linux/delay.h>
#include <asm/gpio.h>
-struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev)
+struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
+ int phyaddr)
{
struct phy_device *phydev;
struct ofnode_phandle_args phandle_args;
ret = ofnode_read_eth_phy_id(node, &vendor, &device);
if (ret) {
- dev_err(dev, "Failed to read eth PHY id, err: %d\n", ret);
+ debug("Failed to read eth PHY id, err: %d\n", ret);
return NULL;
}
- ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio,
- GPIOD_ACTIVE_LOW);
- if (!ret) {
- assert = ofnode_read_u32_default(node, "reset-assert-us", 0);
- deassert = ofnode_read_u32_default(node,
- "reset-deassert-us", 0);
- ret = dm_gpio_set_value(&gpio, 1);
- if (ret) {
- dev_err(dev, "Failed assert gpio, err: %d\n", ret);
- return NULL;
- }
+ if (!IS_ENABLED(CONFIG_DM_ETH_PHY)) {
+ ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio,
+ GPIOD_ACTIVE_LOW);
+ if (!ret) {
+ assert = ofnode_read_u32_default(node,
+ "reset-assert-us", 0);
+ deassert = ofnode_read_u32_default(node,
+ "reset-deassert-us",
+ 0);
+ ret = dm_gpio_set_value(&gpio, 1);
+ if (ret) {
+ dev_err(dev,
+ "Failed assert gpio, err: %d\n", ret);
+ return NULL;
+ }
- udelay(assert);
+ udelay(assert);
- ret = dm_gpio_set_value(&gpio, 0);
- if (ret) {
- dev_err(dev, "Failed deassert gpio, err: %d\n", ret);
- return NULL;
- }
+ ret = dm_gpio_set_value(&gpio, 0);
+ if (ret) {
+ dev_err(dev,
+ "Failed deassert gpio, err: %d\n",
+ ret);
+ return NULL;
+ }
- udelay(deassert);
+ udelay(deassert);
+ }
}
id = vendor << 16 | device;
- phydev = phy_device_create(bus, 0, id, false);
+ phydev = phy_device_create(bus, phyaddr, id, false);
if (phydev)
phydev->node = node;
return 0;
}
-static struct phy_driver nxp_tja11xx = {
+static struct phy_driver nxp_c45_tja11xx = {
.name = "NXP C45 TJA1103",
.uid = PHY_ID_TJA_1103,
.mask = 0xfffff0,
.shutdown = &genphy_shutdown,
};
-int phy_nxp_tja11xx_init(void)
+int phy_nxp_c45_tja11xx_init(void)
{
- phy_register(&nxp_tja11xx);
+ phy_register(&nxp_c45_tja11xx);
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/* NXP TJA1100 BroadRReach PHY driver
+ *
+ * Copyright (C) 2022 Michael Trimarchi <michael@amarulasolutions.com>
+ * Copyright (C) 2022 Ariel D'Alessandro <ariel.dalessandro@collabora.com>
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <phy.h>
+
+#define PHY_ID_MASK 0xfffffff0
+#define PHY_ID_TJA1100 0x0180dc40
+#define PHY_ID_TJA1101 0x0180dd00
+
+#define MII_ECTRL 17
+#define MII_ECTRL_LINK_CONTROL BIT(15)
+#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
+#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
+#define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
+#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
+#define MII_ECTRL_CABLE_TEST BIT(5)
+#define MII_ECTRL_CONFIG_EN BIT(2)
+#define MII_ECTRL_WAKE_REQUEST BIT(0)
+
+#define MII_CFG1 18
+#define MII_CFG1_MASTER_SLAVE BIT(15)
+#define MII_CFG1_AUTO_OP BIT(14)
+#define MII_CFG1_SLEEP_CONFIRM BIT(6)
+#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
+#define MII_CFG1_LED_MODE_LINKUP 0
+#define MII_CFG1_LED_ENABLE BIT(3)
+
+#define MII_CFG2 19
+#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
+#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
+
+#define MII_INTSRC 21
+#define MII_INTSRC_LINK_FAIL BIT(10)
+#define MII_INTSRC_LINK_UP BIT(9)
+#define MII_INTSRC_MASK (MII_INTSRC_LINK_FAIL | \
+ MII_INTSRC_LINK_UP)
+#define MII_INTSRC_UV_ERR BIT(3)
+#define MII_INTSRC_TEMP_ERR BIT(1)
+
+#define MII_INTEN 22
+#define MII_INTEN_LINK_FAIL BIT(10)
+#define MII_INTEN_LINK_UP BIT(9)
+#define MII_INTEN_UV_ERR BIT(3)
+#define MII_INTEN_TEMP_ERR BIT(1)
+
+#define MII_COMMSTAT 23
+#define MII_COMMSTAT_LINK_UP BIT(15)
+#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
+#define MII_COMMSTAT_SQI_MAX 7
+
+#define MII_GENSTAT 24
+#define MII_GENSTAT_PLL_LOCKED BIT(14)
+
+#define MII_EXTSTAT 25
+#define MII_EXTSTAT_SHORT_DETECT BIT(8)
+#define MII_EXTSTAT_OPEN_DETECT BIT(7)
+#define MII_EXTSTAT_POLARITY_DETECT BIT(6)
+
+#define MII_COMMCFG 27
+#define MII_COMMCFG_AUTO_OP BIT(15)
+
+static inline int tja11xx_set_bits(struct phy_device *phydev, u32 regnum,
+ u16 val)
+{
+ return phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_clear_bits(struct phy_device *phydev, u32 regnum,
+ u16 val)
+{
+ return phy_clear_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_read(struct phy_device *phydev, int regnum)
+{
+ return phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+}
+
+static inline int tja11xx_modify(struct phy_device *phydev, int regnum,
+ u16 mask, u16 set)
+{
+ return phy_modify(phydev, MDIO_DEVAD_NONE, regnum, mask, set);
+}
+
+static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
+{
+ int val;
+
+ return read_poll_timeout(tja11xx_read, val, (val & mask) == set, 150,
+ 30000, phydev, reg);
+}
+
+static int tja11xx_modify_check(struct phy_device *phydev, u8 reg,
+ u16 mask, u16 set)
+{
+ int ret;
+
+ ret = tja11xx_modify(phydev, reg, mask, set);
+ if (ret)
+ return ret;
+
+ return tja11xx_check(phydev, reg, mask, set);
+}
+
+static int tja11xx_enable_reg_write(struct phy_device *phydev)
+{
+ return tja11xx_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
+}
+
+static int tja11xx_enable_link_control(struct phy_device *phydev)
+{
+ return tja11xx_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
+}
+
+static int tja11xx_wakeup(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = tja11xx_read(phydev, MII_ECTRL);
+ if (ret < 0)
+ return ret;
+
+ switch (ret & MII_ECTRL_POWER_MODE_MASK) {
+ case MII_ECTRL_POWER_MODE_NO_CHANGE:
+ break;
+ case MII_ECTRL_POWER_MODE_NORMAL:
+ ret = tja11xx_set_bits(phydev, MII_ECTRL,
+ MII_ECTRL_WAKE_REQUEST);
+ if (ret)
+ return ret;
+
+ ret = tja11xx_clear_bits(phydev, MII_ECTRL,
+ MII_ECTRL_WAKE_REQUEST);
+ if (ret)
+ return ret;
+ break;
+ case MII_ECTRL_POWER_MODE_STANDBY:
+ ret = tja11xx_modify_check(phydev, MII_ECTRL,
+ MII_ECTRL_POWER_MODE_MASK,
+ MII_ECTRL_POWER_MODE_STANDBY);
+ if (ret)
+ return ret;
+
+ ret = tja11xx_modify(phydev, MII_ECTRL,
+ MII_ECTRL_POWER_MODE_MASK,
+ MII_ECTRL_POWER_MODE_NORMAL);
+ if (ret)
+ return ret;
+
+ ret = tja11xx_modify_check(phydev, MII_GENSTAT,
+ MII_GENSTAT_PLL_LOCKED,
+ MII_GENSTAT_PLL_LOCKED);
+ if (ret)
+ return ret;
+
+ return tja11xx_enable_link_control(phydev);
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int tja11xx_config_init(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = tja11xx_enable_reg_write(phydev);
+ if (ret)
+ return ret;
+
+ phydev->autoneg = AUTONEG_DISABLE;
+ phydev->speed = SPEED_100;
+ phydev->duplex = DUPLEX_FULL;
+
+ switch (phydev->phy_id & PHY_ID_MASK) {
+ case PHY_ID_TJA1100:
+ ret = tja11xx_modify(phydev, MII_CFG1,
+ MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
+ MII_CFG1_LED_ENABLE,
+ MII_CFG1_AUTO_OP |
+ MII_CFG1_LED_MODE_LINKUP |
+ MII_CFG1_LED_ENABLE);
+ if (ret)
+ return ret;
+ break;
+ case PHY_ID_TJA1101:
+ ret = tja11xx_set_bits(phydev, MII_COMMCFG,
+ MII_COMMCFG_AUTO_OP);
+ if (ret)
+ return ret;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = tja11xx_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
+ if (ret)
+ return ret;
+
+ ret = tja11xx_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
+ MII_CFG2_SLEEP_REQUEST_TO_16MS);
+ if (ret)
+ return ret;
+
+ ret = tja11xx_wakeup(phydev);
+ if (ret < 0)
+ return ret;
+
+ /* ACK interrupts by reading the status register */
+ ret = tja11xx_read(phydev, MII_INTSRC);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tja11xx_startup(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ ret = tja11xx_read(phydev, MII_CFG1);
+ if (ret < 0)
+ return ret;
+
+ if (phydev->link) {
+ ret = tja11xx_read(phydev, MII_COMMSTAT);
+ if (ret < 0)
+ return ret;
+
+ if (!(ret & MII_COMMSTAT_LINK_UP))
+ phydev->link = 0;
+ }
+
+ return 0;
+}
+
+static struct phy_driver TJA1100_driver = {
+ .name = "NXP TJA1100",
+ .uid = PHY_ID_TJA1100,
+ .mask = PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .config = &tja11xx_config_init,
+ .startup = &tja11xx_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver TJA1101_driver = {
+ .name = "NXP TJA1101",
+ .uid = PHY_ID_TJA1101,
+ .mask = PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .config = &tja11xx_config_init,
+ .startup = &tja11xx_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_nxp_tja11xx_init(void)
+{
+ phy_register(&TJA1100_driver);
+ phy_register(&TJA1101_driver);
+
+ return 0;
+}
phy_natsemi_init();
#endif
#ifdef CONFIG_NXP_C45_TJA11XX_PHY
+ phy_nxp_c45_tja11xx_init();
+#endif
+#ifdef CONFIG_PHY_NXP_TJA11XX
phy_nxp_tja11xx_init();
#endif
#ifdef CONFIG_PHY_REALTEK
#ifdef CONFIG_PHY_ETHERNET_ID
if (!phydev)
- phydev = phy_connect_phy_id(bus, dev);
+ phydev = phy_connect_phy_id(bus, dev, addr);
#endif
#ifdef CONFIG_PHY_XILINX_GMII2RGMII
return 0;
}
+
+/**
+ * phy_modify - Convenience function for modifying a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @mask: bit mask of bits to clear
+ * @set: new value of bits set in mask to write to @regnum
+ */
+int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
+ u16 set)
+{
+ int ret;
+
+ ret = phy_read(phydev, devad, regnum);
+ if (ret < 0)
+ return ret;
+
+ return phy_write(phydev, devad, regnum, (ret & ~mask) | set);
+}
#include <miiphy.h>
#include <net.h>
#include <reset.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <wait_bit.h>
#define MDIO_CMD_MII_BUSY BIT(0)
#define AHB_GATE_OFFSET_EPHY 0
-/* IO mux settings */
-#define SUN8I_IOMUX_H3 2
-#define SUN8I_IOMUX_R40 5
-#define SUN8I_IOMUX_H6 5
-#define SUN8I_IOMUX_H616 2
-#define SUN8I_IOMUX 4
-
/* H3/A64 EMAC Register's offset */
#define EMAC_CTL0 0x00
#define EMAC_CTL0_FULL_DUPLEX BIT(0)
return 0;
}
-static int parse_phy_pins(struct udevice *dev)
-{
- int offset;
- const char *pin_name;
- int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
- u32 iomux;
-
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
- "pinctrl-0");
- if (offset < 0) {
- printf("WARNING: emac: cannot find pinctrl-0 node\n");
- return offset;
- }
-
- drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
- "drive-strength", ~0);
- if (drive != ~0) {
- if (drive <= 10)
- drive = SUN4I_PINCTRL_10_MA;
- else if (drive <= 20)
- drive = SUN4I_PINCTRL_20_MA;
- else if (drive <= 30)
- drive = SUN4I_PINCTRL_30_MA;
- else
- drive = SUN4I_PINCTRL_40_MA;
- }
-
- if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
- pull = SUN4I_PINCTRL_PULL_UP;
- else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
- pull = SUN4I_PINCTRL_PULL_DOWN;
-
- /*
- * The GPIO pinmux value is an integration choice, so depends on the
- * SoC, not the EMAC variant.
- */
- if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
- iomux = SUN8I_IOMUX_H3;
- else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
- iomux = SUN8I_IOMUX_R40;
- else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
- iomux = SUN8I_IOMUX_H6;
- else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
- iomux = SUN8I_IOMUX_H616;
- else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
- iomux = SUN8I_IOMUX;
- else if (IS_ENABLED(CONFIG_MACH_SUN50I))
- iomux = SUN8I_IOMUX;
- else
- BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
-
- for (i = 0; ; i++) {
- int pin;
-
- pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
- "pins", i, NULL);
- if (!pin_name)
- break;
-
- pin = sunxi_name_to_gpio(pin_name);
- if (pin < 0)
- continue;
-
- sunxi_gpio_set_cfgpin(pin, iomux);
-
- if (drive != ~0)
- sunxi_gpio_set_drv(pin, drive);
- if (pull != ~0)
- sunxi_gpio_set_pull(pin, pull);
- }
-
- if (!i) {
- printf("WARNING: emac: cannot find pins property\n");
- return -2;
- }
-
- return 0;
-}
-
static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct emac_eth_dev *priv = dev_get_priv(dev);
priv->interface = pdata->phy_interface;
- if (!priv->use_internal_phy)
- parse_phy_pins(dev);
-
sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
"allwinner,tx-delay-ps", 0);
if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
#include <net.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
/* EMAC register */
struct emac_regs {
struct sunxi_sramc_regs *sram =
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
struct emac_regs *regs = priv->regs;
- int pin, ret;
+ int ret;
/* Map SRAM to EMAC */
setbits_le32(&sram->ctrl1, 0x5 << 2);
- /* Configure pin mux settings for MII Ethernet */
- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
-
/* Set up clock gating */
ret = clk_enable(&priv->clk);
if (ret) {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007, 2010 Freescale Semiconductor, Inc.
- *
- * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
- *
- * Description:
- * ULI 526x Ethernet port driver.
- * Based on the Linux driver: drivers/net/tulip/uli526x.c
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-
-/* some kernel function compatible define */
-
-#undef DEBUG
-
-/* Board/System/Debug information/definition */
-#define ULI_VENDOR_ID 0x10B9
-#define ULI5261_DEVICE_ID 0x5261
-#define ULI5263_DEVICE_ID 0x5263
-/* ULi M5261 ID*/
-#define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
-/* ULi M5263 ID*/
-#define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
-
-#define ULI526X_IO_SIZE 0x100
-#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
-#define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
-#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
-#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
-#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
-#define TX_BUF_ALLOC 0x300
-#define RX_ALLOC_SIZE PKTSIZE
-#define ULI526X_RESET 1
-#define CR0_DEFAULT 0
-#define CR6_DEFAULT 0x22200000
-#define CR7_DEFAULT 0x180c1
-#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
-#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
-#define MAX_PACKET_SIZE 1514
-#define ULI5261_MAX_MULTICAST 14
-#define RX_COPY_SIZE 100
-#define MAX_CHECK_PACKET 0x8000
-
-#define ULI526X_10MHF 0
-#define ULI526X_100MHF 1
-#define ULI526X_10MFD 4
-#define ULI526X_100MFD 5
-#define ULI526X_AUTO 8
-
-#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
-#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
-#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
-#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
-#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
-#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
-
-/* CR9 definition: SROM/MII */
-#define CR9_SROM_READ 0x4800
-#define CR9_SRCS 0x1
-#define CR9_SRCLK 0x2
-#define CR9_CRDOUT 0x8
-#define SROM_DATA_0 0x0
-#define SROM_DATA_1 0x4
-#define PHY_DATA_1 0x20000
-#define PHY_DATA_0 0x00000
-#define MDCLKH 0x10000
-
-#define PHY_POWER_DOWN 0x800
-
-#define SROM_V41_CODE 0x14
-
-#define SROM_CLK_WRITE(data, ioaddr) do { \
- outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
- udelay(5); \
- outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
- udelay(5); \
- outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
- udelay(5); \
- } while (0)
-
-/* Structure/enum declaration */
-
-struct tx_desc {
- u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
- char *tx_buf_ptr; /* Data for us */
- struct tx_desc *next_tx_desc;
-};
-
-struct rx_desc {
- u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
- char *rx_buf_ptr; /* Data for us */
- struct rx_desc *next_rx_desc;
-};
-
-struct uli526x_board_info {
- u32 chip_id; /* Chip vendor/Device ID */
- pci_dev_t pdev;
-
- long ioaddr; /* I/O base address */
- u32 cr0_data;
- u32 cr5_data;
- u32 cr6_data;
- u32 cr7_data;
- u32 cr15_data;
-
- /* pointer for memory physical address */
- dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
- dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
- dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
- dma_addr_t first_tx_desc_dma;
- dma_addr_t first_rx_desc_dma;
-
- /* descriptor pointer */
- unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
- unsigned char *buf_pool_start; /* Tx buffer pool align dword */
- unsigned char *desc_pool_ptr; /* descriptor pool memory */
- struct tx_desc *first_tx_desc;
- struct tx_desc *tx_insert_ptr;
- struct tx_desc *tx_remove_ptr;
- struct rx_desc *first_rx_desc;
- struct rx_desc *rx_ready_ptr; /* packet come pointer */
- unsigned long tx_packet_cnt; /* transmitted packet count */
-
- u16 PHY_reg4; /* Saved Phyxcer register 4 value */
-
- u8 media_mode; /* user specify media mode */
- u8 op_mode; /* real work dedia mode */
- u8 phy_addr;
-
- /* NIC SROM data */
- unsigned char srom[128];
-};
-
-enum uli526x_offsets {
- DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
- DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
- DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
- DCR15 = 0x78
-};
-
-enum uli526x_CR6_bits {
- CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
- CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
- CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
-};
-
-/* Global variable declaration -- */
-
-static unsigned char uli526x_media_mode = ULI526X_AUTO;
-
-static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
- __attribute__ ((aligned(32)));
-static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
-
-/* For module input parameter */
-static int mode = 8;
-
-/* function declaration -- */
-static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length);
-static u16 read_srom_word(long, int);
-static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
-static void allocate_rx_buffer(struct uli526x_board_info *);
-static void update_cr6(u32, unsigned long);
-static u16 uli_phy_read(unsigned long, u8, u8, u32);
-static u16 phy_readby_cr10(unsigned long, u8, u8);
-static void uli_phy_write(unsigned long, u8, u8, u16, u32);
-static void phy_writeby_cr10(unsigned long, u8, u8, u16);
-static void phy_write_1bit(unsigned long, u32, u32);
-static u16 phy_read_1bit(unsigned long, u32);
-static int uli526x_rx_packet(struct eth_device *);
-static void uli526x_free_tx_pkt(struct eth_device *,
- struct uli526x_board_info *);
-static void uli526x_reuse_buf(struct rx_desc *);
-static void uli526x_init(struct eth_device *);
-static void uli526x_set_phyxcer(struct uli526x_board_info *);
-
-
-static int uli526x_init_one(struct eth_device *, struct bd_info *);
-static void uli526x_disable(struct eth_device *);
-static void set_mac_addr(struct eth_device *);
-
-static struct pci_device_id uli526x_pci_tbl[] = {
- { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
- { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
- {}
-};
-
-/* ULI526X network board routine */
-
-/*
- * Search ULI526X board, register it
- */
-
-int uli526x_initialize(struct bd_info *bis)
-{
- pci_dev_t devno;
- int card_number = 0;
- struct eth_device *dev;
- struct uli526x_board_info *db; /* board information structure */
-
- u32 iobase;
- int idx = 0;
-
- while (1) {
- /* Find PCI device */
- devno = pci_find_devices(uli526x_pci_tbl, idx++);
- if (devno < 0)
- break;
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
- iobase &= ~0xf;
-
- dev = (struct eth_device *)malloc(sizeof *dev);
- if (!dev) {
- printf("uli526x: Can not allocate memory\n");
- break;
- }
- memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "uli526x#%d", card_number);
- db = (struct uli526x_board_info *)
- malloc(sizeof(struct uli526x_board_info));
-
- dev->priv = db;
- db->pdev = devno;
- dev->iobase = iobase;
-
- dev->init = uli526x_init_one;
- dev->halt = uli526x_disable;
- dev->send = uli526x_start_xmit;
- dev->recv = uli526x_rx_packet;
-
- /* init db */
- db->ioaddr = dev->iobase;
- /* get chip id */
-
- pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
-#ifdef DEBUG
- printf("uli526x: uli526x @0x%x\n", iobase);
- printf("uli526x: chip_id%x\n", db->chip_id);
-#endif
- eth_register(dev);
- card_number++;
- pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
- udelay(10 * 1000);
- }
- return card_number;
-}
-
-static int uli526x_init_one(struct eth_device *dev, struct bd_info *bis)
-{
-
- struct uli526x_board_info *db = dev->priv;
- int i;
-
- switch (mode) {
- case ULI526X_10MHF:
- case ULI526X_100MHF:
- case ULI526X_10MFD:
- case ULI526X_100MFD:
- uli526x_media_mode = mode;
- break;
- default:
- uli526x_media_mode = ULI526X_AUTO;
- break;
- }
-
- /* Allocate Tx/Rx descriptor memory */
- db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
- db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
- if (db->desc_pool_ptr == NULL)
- return -1;
-
- db->buf_pool_ptr = (uchar *)&buf_pool[0];
- db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
- if (db->buf_pool_ptr == NULL)
- return -1;
-
- db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
- db->first_tx_desc_dma = db->desc_pool_dma_ptr;
-
- db->buf_pool_start = db->buf_pool_ptr;
- db->buf_pool_dma_start = db->buf_pool_dma_ptr;
-
-#ifdef DEBUG
- printf("%s(): db->ioaddr= 0x%x\n",
- __FUNCTION__, db->ioaddr);
- printf("%s(): media_mode= 0x%x\n",
- __FUNCTION__, uli526x_media_mode);
- printf("%s(): db->desc_pool_ptr= 0x%x\n",
- __FUNCTION__, db->desc_pool_ptr);
- printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
- __FUNCTION__, db->desc_pool_dma_ptr);
- printf("%s(): db->buf_pool_ptr= 0x%x\n",
- __FUNCTION__, db->buf_pool_ptr);
- printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
- __FUNCTION__, db->buf_pool_dma_ptr);
-#endif
-
- /* read 64 word srom data */
- for (i = 0; i < 64; i++)
- ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
- i));
-
- /* Set Node address */
- if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
- ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
- /* SROM absent, so write MAC address to ID Table */
- set_mac_addr(dev);
- else { /*Exist SROM*/
- for (i = 0; i < 6; i++)
- dev->enetaddr[i] = db->srom[20 + i];
- }
-#ifdef DEBUG
- for (i = 0; i < 6; i++)
- printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
-#endif
- db->PHY_reg4 = 0x1e0;
-
- /* system variable init */
- db->cr6_data = CR6_DEFAULT ;
- db->cr6_data |= ULI526X_TXTH_256;
- db->cr0_data = CR0_DEFAULT;
- uli526x_init(dev);
- return 0;
-}
-
-static void uli526x_disable(struct eth_device *dev)
-{
-#ifdef DEBUG
- printf("uli526x_disable\n");
-#endif
- struct uli526x_board_info *db = dev->priv;
-
- if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
- /* Reset & stop ULI526X board */
- outl(ULI526X_RESET, db->ioaddr + DCR0);
- udelay(5);
- uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
-
- /* reset the board */
- db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
- update_cr6(db->cr6_data, dev->iobase);
- outl(0, dev->iobase + DCR7); /* Disable Interrupt */
- outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
- }
-}
-
-/* Initialize ULI526X board
- * Reset ULI526X board
- * Initialize TX/Rx descriptor chain structure
- * Send the set-up frame
- * Enable Tx/Rx machine
- */
-
-static void uli526x_init(struct eth_device *dev)
-{
-
- struct uli526x_board_info *db = dev->priv;
- u8 phy_tmp;
- u16 phy_value;
- u16 phy_reg_reset;
-
- /* Reset M526x MAC controller */
- outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
- udelay(100);
- outl(db->cr0_data, db->ioaddr + DCR0);
- udelay(5);
-
- /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
- db->phy_addr = 1;
- db->tx_packet_cnt = 0;
- for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
- /* peer add */
- phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
- if (phy_value != 0xffff && phy_value != 0) {
- db->phy_addr = phy_tmp;
- break;
- }
- }
-
-#ifdef DEBUG
- printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
- printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
-#endif
- if (phy_tmp == 32)
- printf("Can not find the phy address!!!");
-
- /* Parser SROM and media mode */
- db->media_mode = uli526x_media_mode;
-
- if (!(inl(db->ioaddr + DCR12) & 0x8)) {
- /* Phyxcer capability setting */
- phy_reg_reset = uli_phy_read(db->ioaddr,
- db->phy_addr, 0, db->chip_id);
- phy_reg_reset = (phy_reg_reset | 0x8000);
- uli_phy_write(db->ioaddr, db->phy_addr, 0,
- phy_reg_reset, db->chip_id);
- udelay(500);
-
- /* Process Phyxcer Media Mode */
- uli526x_set_phyxcer(db);
- }
- /* Media Mode Process */
- if (!(db->media_mode & ULI526X_AUTO))
- db->op_mode = db->media_mode; /* Force Mode */
-
- /* Initialize Transmit/Receive decriptor and CR3/4 */
- uli526x_descriptor_init(db, db->ioaddr);
-
- /* Init CR6 to program M526X operation */
- update_cr6(db->cr6_data, db->ioaddr);
-
- /* Init CR7, interrupt active bit */
- db->cr7_data = CR7_DEFAULT;
- outl(db->cr7_data, db->ioaddr + DCR7);
-
- /* Init CR15, Tx jabber and Rx watchdog timer */
- outl(db->cr15_data, db->ioaddr + DCR15);
-
- /* Enable ULI526X Tx/Rx function */
- db->cr6_data |= CR6_RXSC | CR6_TXSC;
- update_cr6(db->cr6_data, db->ioaddr);
- while (!(inl(db->ioaddr + DCR12) & 0x8))
- udelay(10);
-}
-
-/*
- * Hardware start transmission.
- * Send a packet to media from the upper layer.
- */
-
-static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length)
-{
- struct uli526x_board_info *db = dev->priv;
- struct tx_desc *txptr;
- unsigned int len = length;
- /* Too large packet check */
- if (len > MAX_PACKET_SIZE) {
- printf(": big packet = %d\n", len);
- return 0;
- }
-
- /* No Tx resource check, it never happen nromally */
- if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
- printf("No Tx resource %ld\n", db->tx_packet_cnt);
- return 0;
- }
-
- /* Disable NIC interrupt */
- outl(0, dev->iobase + DCR7);
-
- /* transmit this packet */
- txptr = db->tx_insert_ptr;
- memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
- txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
-
- /* Point to next transmit free descriptor */
- db->tx_insert_ptr = txptr->next_tx_desc;
-
- /* Transmit Packet Process */
- if ((db->tx_packet_cnt < TX_DESC_CNT)) {
- txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
- db->tx_packet_cnt++; /* Ready to send */
- outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
- }
-
- /* Got ULI526X status */
- db->cr5_data = inl(db->ioaddr + DCR5);
- outl(db->cr5_data, db->ioaddr + DCR5);
-
-#ifdef TX_DEBUG
- printf("%s(): length = 0x%x\n", __FUNCTION__, length);
- printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
-#endif
-
- outl(db->cr7_data, dev->iobase + DCR7);
- uli526x_free_tx_pkt(dev, db);
-
- return length;
-}
-
-/*
- * Free TX resource after TX complete
- */
-
-static void uli526x_free_tx_pkt(struct eth_device *dev,
- struct uli526x_board_info *db)
-{
- struct tx_desc *txptr;
- u32 tdes0;
-
- txptr = db->tx_remove_ptr;
- while (db->tx_packet_cnt) {
- tdes0 = le32_to_cpu(txptr->tdes0);
- /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
- if (tdes0 & 0x80000000)
- break;
-
- /* A packet sent completed */
- db->tx_packet_cnt--;
-
- if (tdes0 != 0x7fffffff) {
-#ifdef TX_DEBUG
- printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
-#endif
- if (tdes0 & TDES0_ERR_MASK) {
- if (tdes0 & 0x0002) { /* UnderRun */
- if (!(db->cr6_data & CR6_SFT)) {
- db->cr6_data = db->cr6_data |
- CR6_SFT;
- update_cr6(db->cr6_data,
- db->ioaddr);
- }
- }
- }
- }
-
- txptr = txptr->next_tx_desc;
- }/* End of while */
-
- /* Update TX remove pointer to next */
- db->tx_remove_ptr = txptr;
-}
-
-
-/*
- * Receive the come packet and pass to upper layer
- */
-
-static int uli526x_rx_packet(struct eth_device *dev)
-{
- struct uli526x_board_info *db = dev->priv;
- struct rx_desc *rxptr;
- int rxlen = 0;
- u32 rdes0;
-
- rxptr = db->rx_ready_ptr;
-
- rdes0 = le32_to_cpu(rxptr->rdes0);
-#ifdef RX_DEBUG
- printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0);
-#endif
- if (!(rdes0 & 0x80000000)) { /* packet owner check */
- if ((rdes0 & 0x300) != 0x300) {
- /* A packet without First/Last flag */
- /* reuse this buf */
- printf("A packet without First/Last flag");
- uli526x_reuse_buf(rxptr);
- } else {
- /* A packet with First/Last flag */
- rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
-#ifdef RX_DEBUG
- printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
-#endif
- /* error summary bit check */
- if (rdes0 & 0x8000) {
- /* This is a error packet */
- printf("Error: rdes0: %x\n", rdes0);
- }
-
- if (!(rdes0 & 0x8000) ||
- ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
-
-#ifdef RX_DEBUG
- printf("%s(): rx_skb_ptr =%x\n",
- __FUNCTION__, rxptr->rx_buf_ptr);
- printf("%s(): rxlen =%x\n",
- __FUNCTION__, rxlen);
-
- printf("%s(): buf addr =%x\n",
- __FUNCTION__, rxptr->rx_buf_ptr);
- printf("%s(): rxlen =%x\n",
- __FUNCTION__, rxlen);
- int i;
- for (i = 0; i < 0x20; i++)
- printf("%s(): data[%x] =%x\n",
- __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
-#endif
-
- net_process_received_packet(
- (uchar *)rxptr->rx_buf_ptr, rxlen);
- uli526x_reuse_buf(rxptr);
-
- } else {
- /* Reuse SKB buffer when the packet is error */
- printf("Reuse buffer, rdes0");
- uli526x_reuse_buf(rxptr);
- }
- }
-
- rxptr = rxptr->next_rx_desc;
- }
-
- db->rx_ready_ptr = rxptr;
- return rxlen;
-}
-
-/*
- * Reuse the RX buffer
- */
-
-static void uli526x_reuse_buf(struct rx_desc *rxptr)
-{
-
- if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
- rxptr->rdes0 = cpu_to_le32(0x80000000);
- else
- printf("Buffer reuse method error");
-}
-/*
- * Initialize transmit/Receive descriptor
- * Using Chain structure, and allocate Tx/Rx buffer
- */
-
-static void uli526x_descriptor_init(struct uli526x_board_info *db,
- unsigned long ioaddr)
-{
- struct tx_desc *tmp_tx;
- struct rx_desc *tmp_rx;
- unsigned char *tmp_buf;
- dma_addr_t tmp_tx_dma, tmp_rx_dma;
- dma_addr_t tmp_buf_dma;
- int i;
- /* tx descriptor start pointer */
- db->tx_insert_ptr = db->first_tx_desc;
- db->tx_remove_ptr = db->first_tx_desc;
-
- outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
-
- /* rx descriptor start pointer */
- db->first_rx_desc = (void *)db->first_tx_desc +
- sizeof(struct tx_desc) * TX_DESC_CNT;
- db->first_rx_desc_dma = db->first_tx_desc_dma +
- sizeof(struct tx_desc) * TX_DESC_CNT;
- db->rx_ready_ptr = db->first_rx_desc;
- outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
-#ifdef DEBUG
- printf("%s(): db->first_tx_desc= 0x%x\n",
- __FUNCTION__, db->first_tx_desc);
- printf("%s(): db->first_rx_desc_dma= 0x%x\n",
- __FUNCTION__, db->first_rx_desc_dma);
-#endif
- /* Init Transmit chain */
- tmp_buf = db->buf_pool_start;
- tmp_buf_dma = db->buf_pool_dma_start;
- tmp_tx_dma = db->first_tx_desc_dma;
- for (tmp_tx = db->first_tx_desc, i = 0;
- i < TX_DESC_CNT; i++, tmp_tx++) {
- tmp_tx->tx_buf_ptr = (char *)tmp_buf;
- tmp_tx->tdes0 = cpu_to_le32(0);
- tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
- tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
- tmp_tx_dma += sizeof(struct tx_desc);
- tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
- tmp_tx->next_tx_desc = tmp_tx + 1;
- tmp_buf = tmp_buf + TX_BUF_ALLOC;
- tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
- }
- (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
- tmp_tx->next_tx_desc = db->first_tx_desc;
-
- /* Init Receive descriptor chain */
- tmp_rx_dma = db->first_rx_desc_dma;
- for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
- i++, tmp_rx++) {
- tmp_rx->rdes0 = cpu_to_le32(0);
- tmp_rx->rdes1 = cpu_to_le32(0x01000600);
- tmp_rx_dma += sizeof(struct rx_desc);
- tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
- tmp_rx->next_rx_desc = tmp_rx + 1;
- }
- (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
- tmp_rx->next_rx_desc = db->first_rx_desc;
-
- /* pre-allocate Rx buffer */
- allocate_rx_buffer(db);
-}
-
-/*
- * Update CR6 value
- * Firstly stop ULI526X, then written value and start
- */
-
-static void update_cr6(u32 cr6_data, unsigned long ioaddr)
-{
-
- outl(cr6_data, ioaddr + DCR6);
- udelay(5);
-}
-
-/*
- * Allocate rx buffer,
- */
-
-static void allocate_rx_buffer(struct uli526x_board_info *db)
-{
- int index;
- struct rx_desc *rxptr;
- rxptr = db->first_rx_desc;
- u32 addr;
-
- for (index = 0; index < RX_DESC_CNT; index++) {
- addr = (u32)net_rx_packets[index];
- addr += (16 - (addr & 15));
- rxptr->rx_buf_ptr = (char *) addr;
- rxptr->rdes2 = cpu_to_le32(addr);
- rxptr->rdes0 = cpu_to_le32(0x80000000);
-#ifdef DEBUG
- printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
- printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
- printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
- printf("%s(): rxptr buf address = 0x%x\n", \
- __FUNCTION__, rxptr->rx_buf_ptr);
- printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
-#endif
- rxptr = rxptr->next_rx_desc;
- }
-}
-
-/*
- * Read one word data from the serial ROM
- */
-
-static u16 read_srom_word(long ioaddr, int offset)
-{
- int i;
- u16 srom_data = 0;
- long cr9_ioaddr = ioaddr + DCR9;
-
- outl(CR9_SROM_READ, cr9_ioaddr);
- outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
-
- /* Send the Read Command 110b */
- SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
- SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
- SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
-
- /* Send the offset */
- for (i = 5; i >= 0; i--) {
- srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
- SROM_CLK_WRITE(srom_data, cr9_ioaddr);
- }
-
- outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
-
- for (i = 16; i > 0; i--) {
- outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
- udelay(5);
- srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
- ? 1 : 0);
- outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
- udelay(5);
- }
-
- outl(CR9_SROM_READ, cr9_ioaddr);
- return srom_data;
-}
-
-/*
- * Set 10/100 phyxcer capability
- * AUTO mode : phyxcer register4 is NIC capability
- * Force mode: phyxcer register4 is the force media
- */
-
-static void uli526x_set_phyxcer(struct uli526x_board_info *db)
-{
- u16 phy_reg;
-
- /* Phyxcer capability setting */
- phy_reg = uli_phy_read(db->ioaddr,
- db->phy_addr, 4, db->chip_id) & ~0x01e0;
-
- if (db->media_mode & ULI526X_AUTO) {
- /* AUTO Mode */
- phy_reg |= db->PHY_reg4;
- } else {
- /* Force Mode */
- switch (db->media_mode) {
- case ULI526X_10MHF: phy_reg |= 0x20; break;
- case ULI526X_10MFD: phy_reg |= 0x40; break;
- case ULI526X_100MHF: phy_reg |= 0x80; break;
- case ULI526X_100MFD: phy_reg |= 0x100; break;
- }
-
- }
-
- /* Write new capability to Phyxcer Reg4 */
- if (!(phy_reg & 0x01e0)) {
- phy_reg |= db->PHY_reg4;
- db->media_mode |= ULI526X_AUTO;
- }
- uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
-
- /* Restart Auto-Negotiation */
- uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
- udelay(50);
-}
-
-/*
- * Write a word to Phy register
- */
-
-static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
- u16 phy_data, u32 chip_id)
-{
- u16 i;
- unsigned long ioaddr;
-
- if (chip_id == PCI_ULI5263_ID) {
- phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
- return;
- }
- /* M5261/M5263 Chip */
- ioaddr = iobase + DCR9;
-
- /* Send 33 synchronization clock to Phy controller */
- for (i = 0; i < 35; i++)
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send start command(01) to Phy */
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send write command(01) to Phy */
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send Phy address */
- for (i = 0x10; i > 0; i = i >> 1)
- phy_write_1bit(ioaddr, phy_addr & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-
- /* Send register address */
- for (i = 0x10; i > 0; i = i >> 1)
- phy_write_1bit(ioaddr, offset & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-
- /* written trasnition */
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
-
- /* Write a word data to PHY controller */
- for (i = 0x8000; i > 0; i >>= 1)
- phy_write_1bit(ioaddr, phy_data & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-}
-
-/*
- * Read a word data from phy register
- */
-
-static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
- u32 chip_id)
-{
- int i;
- u16 phy_data;
- unsigned long ioaddr;
-
- if (chip_id == PCI_ULI5263_ID)
- return phy_readby_cr10(iobase, phy_addr, offset);
- /* M5261/M5263 Chip */
- ioaddr = iobase + DCR9;
-
- /* Send 33 synchronization clock to Phy controller */
- for (i = 0; i < 35; i++)
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send start command(01) to Phy */
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send read command(10) to Phy */
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
-
- /* Send Phy address */
- for (i = 0x10; i > 0; i = i >> 1)
- phy_write_1bit(ioaddr, phy_addr & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-
- /* Send register address */
- for (i = 0x10; i > 0; i = i >> 1)
- phy_write_1bit(ioaddr, offset & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-
- /* Skip transition state */
- phy_read_1bit(ioaddr, chip_id);
-
- /* read 16bit data */
- for (phy_data = 0, i = 0; i < 16; i++) {
- phy_data <<= 1;
- phy_data |= phy_read_1bit(ioaddr, chip_id);
- }
-
- return phy_data;
-}
-
-static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
-{
- unsigned long ioaddr, cr10_value;
-
- ioaddr = iobase + DCR10;
- cr10_value = phy_addr;
- cr10_value = (cr10_value<<5) + offset;
- cr10_value = (cr10_value<<16) + 0x08000000;
- outl(cr10_value, ioaddr);
- udelay(1);
- while (1) {
- cr10_value = inl(ioaddr);
- if (cr10_value & 0x10000000)
- break;
- }
- return (cr10_value&0x0ffff);
-}
-
-static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
- u8 offset, u16 phy_data)
-{
- unsigned long ioaddr, cr10_value;
-
- ioaddr = iobase + DCR10;
- cr10_value = phy_addr;
- cr10_value = (cr10_value<<5) + offset;
- cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
- outl(cr10_value, ioaddr);
- udelay(1);
-}
-/*
- * Write one bit data to Phy Controller
- */
-
-static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
-{
- outl(phy_data , ioaddr); /* MII Clock Low */
- udelay(1);
- outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
- udelay(1);
- outl(phy_data , ioaddr); /* MII Clock Low */
- udelay(1);
-}
-
-/*
- * Read one bit phy data from PHY controller
- */
-
-static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
-{
- u16 phy_data;
-
- outl(0x50000 , ioaddr);
- udelay(1);
- phy_data = (inl(ioaddr) >> 19) & 0x1;
- outl(0x40000 , ioaddr);
- udelay(1);
-
- return phy_data;
-}
-
-/*
- * Set MAC address to ID Table
- */
-
-static void set_mac_addr(struct eth_device *dev)
-{
- int i;
- u16 addr;
- struct uli526x_board_info *db = dev->priv;
- outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
- /* Reset dianostic pointer port */
- outl(0x1c0, db->ioaddr + DCR13);
- outl(0, db->ioaddr + DCR14); /* Clear reset port */
- outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
- outl(0, db->ioaddr + DCR14); /* Clear reset port */
- outl(0, db->ioaddr + DCR13); /* Clear CR13 */
- /* Select ID Table access port */
- outl(0x1b0, db->ioaddr + DCR13);
- /* Read MAC address from CR14 */
- for (i = 0; i < 3; i++) {
- addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
- outl(addr, db->ioaddr + DCR14);
- }
- /* write end */
- outl(0, db->ioaddr + DCR13); /* Clear CR13 */
- outl(0, db->ioaddr + DCR0); /* Clear CR0 */
- udelay(10);
- return;
-}
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
+#include <eth_phy.h>
+#include <zynqmp_firmware.h>
/* Bit/mask specification */
#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
/* Enable only MDIO bus */
writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl);
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+ priv->phyaddr = eth_phy_get_addr(dev);
+
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
if (!priv->phydev)
return 0;
}
+static int gem_zynqmp_set_dynamic_config(struct udevice *dev)
+{
+ u32 pm_info[2];
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) {
+ if (!zynqmp_pm_is_function_supported(PM_IOCTL,
+ IOCTL_SET_GEM_CONFIG)) {
+ ret = ofnode_read_u32_array(dev_ofnode(dev),
+ "power-domains",
+ pm_info,
+ ARRAY_SIZE(pm_info));
+ if (ret) {
+ dev_err(dev,
+ "Failed to read power-domains info\n");
+ return ret;
+ }
+
+ ret = zynqmp_pm_set_gem_config(pm_info[1],
+ GEM_CONFIG_FIXED, 0);
+ if (ret)
+ return ret;
+
+ ret = zynqmp_pm_set_gem_config(pm_info[1],
+ GEM_CONFIG_SGMII_MODE,
+ 1);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
static int zynq_gem_probe(struct udevice *dev)
{
void *bd_space;
}
}
- priv->bus = mdio_alloc();
- priv->bus->read = zynq_gem_miiphy_read;
- priv->bus->write = zynq_gem_miiphy_write;
- priv->bus->priv = priv;
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+ priv->bus = eth_phy_get_mdio_bus(dev);
- ret = mdio_register_seq(priv->bus, dev_seq(dev));
- if (ret)
- goto err2;
+ if (!priv->bus) {
+ priv->bus = mdio_alloc();
+ priv->bus->read = zynq_gem_miiphy_read;
+ priv->bus->write = zynq_gem_miiphy_write;
+ priv->bus->priv = priv;
+
+ ret = mdio_register_seq(priv->bus, dev_seq(dev));
+ if (ret)
+ goto err2;
+ }
+
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+ eth_phy_set_mdio_bus(dev, priv->bus);
ret = zynq_phy_init(dev);
if (ret)
goto err3;
if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) {
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
+ if (device_is_compatible(dev, "cdns,zynqmp-gem")) {
+ ret = gem_zynqmp_set_dynamic_config(dev);
+ if (ret) {
+ dev_err
+ (dev,
+ "Failed to set gem dynamic config\n");
+ return ret;
+ }
+ }
+ }
ret = generic_phy_power_on(&phy);
if (ret)
return ret;
}
+ printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n",
+ (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phydev->addr,
+ phy_string_for_interface(priv->interface));
+
return ret;
err3:
ofnode parent;
debug("phy-handle does exist %s\n", dev->name);
- priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
- "reg", -1);
+ if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
+ priv->phyaddr = ofnode_read_u32_default
+ (phandle_args.node, "reg", -1);
+
priv->phy_of_node = phandle_args.node;
priv->max_speed = ofnode_read_u32_default(phandle_args.node,
"max-speed",
priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
- printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n",
- (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr,
- phy_string_for_interface(priv->interface));
-
priv->clk_en_info = dev_get_driver_data(dev);
return 0;
-1, 512, 0, &ns_udev);
if (ret)
goto free_id;
+
+ ret = blk_probe_or_unbind(ns_udev);
+ if (ret)
+ goto free_id;
}
free(id);
so you can easily distinguish them by banks layout.
config PHY_IMX8MQ_USB
- bool "NXP i.MX8MQ USB PHY Driver"
+ bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver"
depends on PHY
- depends on IMX8MQ
+ depends on IMX8MQ || IMX8MP
help
- Support the USB3.0 PHY in NXP i.MX8MQ SoC
+ Support the USB3.0 PHY in NXP i.MX8MQ or i.MX8MP SoC
config PHY_XILINX_ZYNQMP
tristate "Xilinx ZynqMP PHY driver"
#include <dm.h>
#include <errno.h>
#include <generic-phy.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
+#include <linux/delay.h>
#include <linux/err.h>
#include <clk.h>
#define PHY_STS0_FSVPLUS BIT(3)
#define PHY_STS0_FSVMINUS BIT(2)
+enum imx8mpq_phy_type {
+ IMX8MQ_PHY,
+ IMX8MP_PHY,
+};
+
struct imx8mq_usb_phy {
#if CONFIG_IS_ENABLED(CLK)
struct clk phy_clk;
#endif
void __iomem *base;
+ enum imx8mpq_phy_type type;
};
static const struct udevice_id imx8mq_usb_phy_of_match[] = {
- {
- .compatible = "fsl,imx8mq-usb-phy",
- },
+ { .compatible = "fsl,imx8mq-usb-phy", .data = IMX8MQ_PHY },
+ { .compatible = "fsl,imx8mp-usb-phy", .data = IMX8MP_PHY },
{},
};
return 0;
}
+static int imx8mp_usb_phy_init(struct phy *usb_phy)
+{
+ struct udevice *dev = usb_phy->dev;
+ struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
+ u32 value;
+
+ /* USB3.0 PHY signal fsel for 24M ref */
+ value = readl(imx_phy->base + PHY_CTRL0);
+ value &= ~PHY_CTRL0_FSEL_MASK;
+ value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
+ writel(value, imx_phy->base + PHY_CTRL0);
+
+ /* Disable alt_clk_en and use internal MPLL clocks */
+ value = readl(imx_phy->base + PHY_CTRL6);
+ value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
+ writel(value, imx_phy->base + PHY_CTRL6);
+
+ value = readl(imx_phy->base + PHY_CTRL1);
+ value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
+ value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
+ writel(value, imx_phy->base + PHY_CTRL1);
+
+ value = readl(imx_phy->base + PHY_CTRL0);
+ value |= PHY_CTRL0_REF_SSP_EN;
+ writel(value, imx_phy->base + PHY_CTRL0);
+
+ value = readl(imx_phy->base + PHY_CTRL2);
+ value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
+ writel(value, imx_phy->base + PHY_CTRL2);
+
+ udelay(10);
+
+ value = readl(imx_phy->base + PHY_CTRL1);
+ value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
+ writel(value, imx_phy->base + PHY_CTRL1);
+
+ return 0;
+}
+
+static int imx8mpq_usb_phy_init(struct phy *usb_phy)
+{
+ struct udevice *dev = usb_phy->dev;
+ struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
+
+ if (imx_phy->type == IMX8MP_PHY)
+ return imx8mp_usb_phy_init(usb_phy);
+ else
+ return imx8mq_usb_phy_init(usb_phy);
+}
+
static int imx8mq_usb_phy_power_on(struct phy *usb_phy)
{
struct udevice *dev = usb_phy->dev;
}
struct phy_ops imx8mq_usb_phy_ops = {
- .init = imx8mq_usb_phy_init,
+ .init = imx8mpq_usb_phy_init,
.power_on = imx8mq_usb_phy_power_on,
.power_off = imx8mq_usb_phy_power_off,
.exit = imx8mq_usb_phy_exit,
{
struct imx8mq_usb_phy *priv = dev_get_priv(dev);
+ priv->type = dev_get_driver_data(dev);
priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
+source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
endmenu
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
-
+obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
config PINCTRL_IMX8M
bool "IMX8M pinctrl driver"
depends on ARCH_IMX8M && PINCTRL_FULL
- select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the imx8m pinctrl driver
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_SUNXI
+
+config PINCTRL_SUNXI
+ select PINCTRL_FULL
+ select PINCTRL_GENERIC
+ select PINCONF
+ select PINMUX
+ bool
+
+config PINCTRL_SUNIV_F1C100S
+ bool "Support for the Allwinner F1C100s PIO"
+ default MACH_SUNIV
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN4I_A10
+ bool "Support for the Allwinner A10 PIO"
+ default MACH_SUN4I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN5I_A13
+ bool "Support for the Allwinner A10s/A13 PIO"
+ default MACH_SUN5I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN6I_A31
+ bool "Support for the Allwinner A31 PIO"
+ default MACH_SUN6I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN6I_A31_R
+ bool "Support for the Allwinner A31 R-PIO"
+ default MACH_SUN6I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN7I_A20
+ bool "Support for the Allwinner A20/R40 PIO"
+ default MACH_SUN7I || MACH_SUN8I_R40
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A23
+ bool "Support for the Allwinner A23 PIO"
+ default MACH_SUN8I_A23
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A23_R
+ bool "Support for the Allwinner A23/A33 R-PIO"
+ default MACH_SUN8I_A23 || MACH_SUN8I_A33
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A33
+ bool "Support for the Allwinner A33 PIO"
+ default MACH_SUN8I_A33
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A83T
+ bool "Support for the Allwinner A83T PIO"
+ default MACH_SUN8I_A83T
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A83T_R
+ bool "Support for the Allwinner A83T R-PIO"
+ default MACH_SUN8I_A83T
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_H3
+ bool "Support for the Allwinner H3 PIO"
+ default MACH_SUN8I_H3
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_H3_R
+ bool "Support for the Allwinner H3/H5 R-PIO"
+ default MACH_SUN8I_H3 || MACH_SUN50I_H5
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_V3S
+ bool "Support for the Allwinner V3s PIO"
+ default MACH_SUN8I_V3S
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN9I_A80
+ bool "Support for the Allwinner A80 PIO"
+ default MACH_SUN9I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN9I_A80_R
+ bool "Support for the Allwinner A80 R-PIO"
+ default MACH_SUN9I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A64
+ bool "Support for the Allwinner A64 PIO"
+ default MACH_SUN50I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A64_R
+ bool "Support for the Allwinner A64 R-PIO"
+ default MACH_SUN50I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H5
+ bool "Support for the Allwinner H5 PIO"
+ default MACH_SUN50I_H5
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H6
+ bool "Support for the Allwinner H6 PIO"
+ default MACH_SUN50I_H6
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H6_R
+ bool "Support for the Allwinner H6 R-PIO"
+ default MACH_SUN50I_H6
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H616
+ bool "Support for the Allwinner H616 PIO"
+ default MACH_SUN50I_H616
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H616_R
+ bool "Support for the Allwinner H616 R-PIO"
+ default MACH_SUN50I_H616
+ select PINCTRL_SUNXI
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += pinctrl-sunxi.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <clk.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <errno.h>
+#include <malloc.h>
+
+#include <asm/gpio.h>
+
+extern U_BOOT_DRIVER(gpio_sunxi);
+
+/*
+ * This structure implements a simplified view of the possible pinmux settings:
+ * Each mux value is assumed to be the same for a given function, across the
+ * pins in each group (almost universally true, with same rare exceptions not
+ * relevant to U-Boot), but also across different ports (not true in many
+ * cases). We ignore the first problem, and work around the latter by just
+ * supporting one particular port for a each function. This works fine for all
+ * board configurations so far. If this would need to be revisited, we could
+ * add a "u8 port;" below and match that, with 0 encoding the "don't care" case.
+ */
+struct sunxi_pinctrl_function {
+ const char name[sizeof("gpio_out")];
+ u8 mux;
+};
+
+struct sunxi_pinctrl_desc {
+ const struct sunxi_pinctrl_function *functions;
+ u8 num_functions;
+ u8 first_bank;
+ u8 num_banks;
+};
+
+struct sunxi_pinctrl_plat {
+ struct sunxi_gpio __iomem *base;
+};
+
+static int sunxi_pinctrl_get_pins_count(struct udevice *dev)
+{
+ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+
+ return desc->num_banks * SUNXI_GPIOS_PER_BANK;
+}
+
+static const char *sunxi_pinctrl_get_pin_name(struct udevice *dev,
+ uint pin_selector)
+{
+ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+ static char pin_name[sizeof("PN31")];
+
+ snprintf(pin_name, sizeof(pin_name), "P%c%d",
+ pin_selector / SUNXI_GPIOS_PER_BANK + desc->first_bank + 'A',
+ pin_selector % SUNXI_GPIOS_PER_BANK);
+
+ return pin_name;
+}
+
+static int sunxi_pinctrl_get_functions_count(struct udevice *dev)
+{
+ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+
+ return desc->num_functions;
+}
+
+static const char *sunxi_pinctrl_get_function_name(struct udevice *dev,
+ uint func_selector)
+{
+ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+
+ return desc->functions[func_selector].name;
+}
+
+static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector,
+ uint func_selector)
+{
+ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+ struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
+ int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
+ int pin = pin_selector % SUNXI_GPIOS_PER_BANK;
+
+ debug("set mux: %-4s => %s (%d)\n",
+ sunxi_pinctrl_get_pin_name(dev, pin_selector),
+ sunxi_pinctrl_get_function_name(dev, func_selector),
+ desc->functions[func_selector].mux);
+
+ sunxi_gpio_set_cfgbank(plat->base + bank, pin,
+ desc->functions[func_selector].mux);
+
+ return 0;
+}
+
+static const struct pinconf_param sunxi_pinctrl_pinconf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 2 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 10 },
+};
+
+static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat,
+ uint bank, uint pin, uint bias)
+{
+ struct sunxi_gpio *regs = &plat->base[bank];
+
+ sunxi_gpio_set_pull_bank(regs, pin, bias);
+
+ return 0;
+}
+
+static int sunxi_pinctrl_pinconf_set_drive(struct sunxi_pinctrl_plat *plat,
+ uint bank, uint pin, uint drive)
+{
+ struct sunxi_gpio *regs = &plat->base[bank];
+
+ if (drive < 10 || drive > 40)
+ return -EINVAL;
+
+ /* Convert mA to the register value, rounding down. */
+ sunxi_gpio_set_drv_bank(regs, pin, drive / 10 - 1);
+
+ return 0;
+}
+
+static int sunxi_pinctrl_pinconf_set(struct udevice *dev, uint pin_selector,
+ uint param, uint val)
+{
+ struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
+ int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
+ int pin = pin_selector % SUNXI_GPIOS_PER_BANK;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ return sunxi_pinctrl_pinconf_set_pull(plat, bank, pin, val);
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ return sunxi_pinctrl_pinconf_set_drive(plat, bank, pin, val);
+ }
+
+ return -EINVAL;
+}
+
+static int sunxi_pinctrl_get_pin_muxing(struct udevice *dev, uint pin_selector,
+ char *buf, int size)
+{
+ struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
+ int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
+ int pin = pin_selector % SUNXI_GPIOS_PER_BANK;
+ int mux = sunxi_gpio_get_cfgbank(plat->base + bank, pin);
+
+ switch (mux) {
+ case SUNXI_GPIO_INPUT:
+ strlcpy(buf, "gpio input", size);
+ break;
+ case SUNXI_GPIO_OUTPUT:
+ strlcpy(buf, "gpio output", size);
+ break;
+ case SUNXI_GPIO_DISABLE:
+ strlcpy(buf, "disabled", size);
+ break;
+ default:
+ snprintf(buf, size, "function %d", mux);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct pinctrl_ops sunxi_pinctrl_ops = {
+ .get_pins_count = sunxi_pinctrl_get_pins_count,
+ .get_pin_name = sunxi_pinctrl_get_pin_name,
+ .get_functions_count = sunxi_pinctrl_get_functions_count,
+ .get_function_name = sunxi_pinctrl_get_function_name,
+ .pinmux_set = sunxi_pinctrl_pinmux_set,
+ .pinconf_num_params = ARRAY_SIZE(sunxi_pinctrl_pinconf_params),
+ .pinconf_params = sunxi_pinctrl_pinconf_params,
+ .pinconf_set = sunxi_pinctrl_pinconf_set,
+ .set_state = pinctrl_generic_set_state,
+ .get_pin_muxing = sunxi_pinctrl_get_pin_muxing,
+};
+
+static int sunxi_pinctrl_bind(struct udevice *dev)
+{
+ struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
+ struct sunxi_pinctrl_desc *desc;
+ struct sunxi_gpio_plat *gpio_plat;
+ struct udevice *gpio_dev;
+ int i, ret;
+
+ desc = (void *)dev_get_driver_data(dev);
+ if (!desc)
+ return -EINVAL;
+ dev_set_priv(dev, desc);
+
+ plat->base = dev_read_addr_ptr(dev);
+
+ ret = device_bind_driver_to_node(dev, "gpio_sunxi", dev->name,
+ dev_ofnode(dev), &gpio_dev);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < desc->num_banks; ++i) {
+ gpio_plat = malloc(sizeof(*gpio_plat));
+ if (!gpio_plat)
+ return -ENOMEM;
+
+ gpio_plat->regs = plat->base + i;
+ gpio_plat->bank_name[0] = 'P';
+ gpio_plat->bank_name[1] = 'A' + desc->first_bank + i;
+ gpio_plat->bank_name[2] = '\0';
+
+ ret = device_bind(gpio_dev, DM_DRIVER_REF(gpio_sunxi),
+ gpio_plat->bank_name, gpio_plat,
+ ofnode_null(), NULL);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sunxi_pinctrl_probe(struct udevice *dev)
+{
+ struct clk *apb_clk;
+
+ apb_clk = devm_clk_get(dev, "apb");
+ if (!IS_ERR(apb_clk))
+ clk_enable(apb_clk);
+
+ return 0;
+}
+
+static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 3 }, /* PE11-PE12 */
+ { "i2c1", 3 }, /* PD5-PD6 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 3 }, /* PC0-PC2 */
+ { "spi0", 2 }, /* PC0-PC3 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 5 }, /* PE0-PE1 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = {
+ .functions = suniv_f1c100s_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(suniv_f1c100s_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 6,
+};
+
+static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
+ { "emac", 2 }, /* PA0-PA17 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PB0-PB1 */
+ { "i2c1", 2 }, /* PB18-PB19 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+#if IS_ENABLED(CONFIG_MMC1_PINS_PH)
+ { "mmc1", 5 }, /* PH22-PH27 */
+#else
+ { "mmc1", 4 }, /* PG0-PG5 */
+#endif
+ { "mmc2", 3 }, /* PC6-PC15 */
+ { "mmc3", 2 }, /* PI4-PI9 */
+ { "spi0", 3 }, /* PC0-PC2, PC23 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 4 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PB22-PB23 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
+ .functions = sun4i_a10_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun4i_a10_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 9,
+};
+
+static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
+ { "emac", 2 }, /* PA0-PA17 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PB0-PB1 */
+ { "i2c1", 2 }, /* PB15-PB16 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG3-PG8 */
+ { "mmc2", 3 }, /* PC6-PC15 */
+ { "spi0", 3 }, /* PC0-PC3 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 4 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PB19-PB20 */
+#endif
+ { "uart1", 4 }, /* PG3-PG4 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
+ .functions = sun5i_a13_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun5i_a13_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 7,
+};
+
+static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
+ { "gmac", 2 }, /* PA0-PA27 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PH14-PH15 */
+ { "i2c1", 2 }, /* PH16-PH17 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC6-PC15, PC24 */
+ { "mmc3", 4 }, /* PC6-PC15, PC24 */
+ { "spi0", 3 }, /* PC0-PC2, PC27 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PH20-PH21 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
+ .functions = sun6i_a31_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun6i_a31_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 8,
+};
+
+static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c", 2 }, /* PL0-PL1 */
+ { "s_uart", 2 }, /* PL2-PL3 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc = {
+ .functions = sun6i_a31_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun6i_a31_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 2,
+};
+
+static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
+ { "emac", 2 }, /* PA0-PA17 */
+ { "gmac", 5 }, /* PA0-PA17 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PB0-PB1 */
+ { "i2c1", 2 }, /* PB18-PB19 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+#if IS_ENABLED(CONFIG_MMC1_PINS_PH)
+ { "mmc1", 5 }, /* PH22-PH27 */
+#else
+ { "mmc1", 4 }, /* PG0-PG5 */
+#endif
+ { "mmc2", 3 }, /* PC5-PC15, PC24 */
+ { "spi0", 3 }, /* PC0-PC2, PC23 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 4 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PB22-PB23 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
+ .functions = sun7i_a20_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun7i_a20_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 9,
+};
+
+static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PH2-PH3 */
+ { "i2c1", 2 }, /* PH4-PH5 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC5-PC16 */
+ { "spi0", 3 }, /* PC0-PC3 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 2 }, /* PB0-PB1 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
+ .functions = sun8i_a23_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun8i_a23_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 8,
+};
+
+static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_uart", 2 }, /* PL2-PL3 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc = {
+ .functions = sun8i_a23_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun8i_a23_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 1,
+};
+
+static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PH2-PH3 */
+ { "i2c1", 2 }, /* PH4-PH5 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC5-PC16 */
+ { "spi0", 3 }, /* PC0-PC3 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 3 }, /* PB0-PB1 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 2 }, /* PB0-PB1 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
+ .functions = sun8i_a33_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun8i_a33_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 8,
+};
+
+static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
+ { "gmac", 4 }, /* PD2-PD23 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PH0-PH1 */
+ { "i2c1", 2 }, /* PH2-PH3 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC5-PC16 */
+ { "spi0", 3 }, /* PC0-PC3 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PB9-PB10 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 2 }, /* PB0-PB1 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc = {
+ .functions = sun8i_a83t_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun8i_a83t_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 8,
+};
+
+static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c", 2 }, /* PL8-PL9 */
+ { "s_uart", 2 }, /* PL2-PL3 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc = {
+ .functions = sun8i_a83t_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun8i_a83t_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 1,
+};
+
+static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
+ { "emac", 2 }, /* PD0-PD17 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PA11-PA12 */
+ { "i2c1", 3 }, /* PA18-PA19 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC5-PC16 */
+ { "spi0", 3 }, /* PC0-PC3 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PA4-PA5 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 2 }, /* PA0-PA1 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
+ .functions = sun8i_h3_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun8i_h3_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 7,
+};
+
+static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c", 2 }, /* PL0-PL1 */
+ { "s_uart", 2 }, /* PL2-PL3 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc = {
+ .functions = sun8i_h3_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun8i_h3_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 1,
+};
+
+static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
+ { "emac", 4 }, /* PD0-PD17 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PB6-PB7 */
+ { "i2c1", 2 }, /* PB8-PB9 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 2 }, /* PC0-PC10 */
+ { "spi0", 3 }, /* PC0-PC3 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 3 }, /* PB8-PB9 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 2 }, /* PB0-PB1 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
+ .functions = sun8i_v3s_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun8i_v3s_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 7,
+};
+
+static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
+ { "gmac", 2 }, /* PA0-PA17 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PH0-PH1 */
+ { "i2c1", 2 }, /* PH2-PH3 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC6-PC16 */
+ { "spi0", 3 }, /* PC0-PC2, PC19 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 4 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PH12-PH13 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
+ .functions = sun9i_a80_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun9i_a80_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 8,
+};
+
+static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c0", 2 }, /* PN0-PN1 */
+ { "s_i2c1", 3 }, /* PM8-PM9 */
+ { "s_uart", 3 }, /* PL0-PL1 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = {
+ .functions = sun9i_a80_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun9i_a80_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 3,
+};
+
+static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
+ { "emac", 4 }, /* PD8-PD23 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PH0-PH1 */
+ { "i2c1", 2 }, /* PH2-PH3 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC1-PC16 */
+ { "pwm", 2 }, /* PD22 */
+ { "spi0", 4 }, /* PC0-PC3 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 4 }, /* PB8-PB9 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 2 }, /* PB0-PB1 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc = {
+ .functions = sun50i_a64_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_a64_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 8,
+};
+
+static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c", 2 }, /* PL8-PL9 */
+ { "s_uart", 2 }, /* PL2-PL3 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc = {
+ .functions = sun50i_a64_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_a64_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 1,
+};
+
+static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
+ { "emac", 2 }, /* PD0-PD17 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PA11-PA12 */
+ { "i2c1", 3 }, /* PA18-PA19 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC1-PC16 */
+ { "spi0", 3 }, /* PC0-PC3 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PA4-PA5 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 2 }, /* PA0-PA1 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
+ .functions = sun50i_h5_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_h5_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 7,
+};
+
+static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
+ { "emac", 5 }, /* PD0-PD20 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 }, /* PD25-PD26 */
+ { "i2c1", 4 }, /* PH5-PH6 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC1-PC14 */
+ { "spi0", 4 }, /* PC0-PC7 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PH0-PH1 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
+ .functions = sun50i_h6_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_h6_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 8,
+};
+
+static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_uart", 2 }, /* PL2-PL3 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc = {
+ .functions = sun50i_h6_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_h6_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 2,
+};
+
+static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
+ { "emac0", 2 }, /* PI0-PI16 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC0-PC16 */
+ { "spi0", 4 }, /* PC0-PC7, PC15-PC16 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PH0-PH1 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = {
+ .functions = sun50i_h616_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_h616_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 9,
+};
+
+static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_uart", 2 }, /* PL2-PL3 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc = {
+ .functions = sun50i_h616_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_h616_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 1,
+};
+
+static const struct udevice_id sunxi_pinctrl_ids[] = {
+#ifdef CONFIG_PINCTRL_SUNIV_F1C100S
+ {
+ .compatible = "allwinner,suniv-f1c100s-pinctrl",
+ .data = (ulong)&suniv_f1c100s_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN4I_A10
+ {
+ .compatible = "allwinner,sun4i-a10-pinctrl",
+ .data = (ulong)&sun4i_a10_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN5I_A13
+ {
+ .compatible = "allwinner,sun5i-a10s-pinctrl",
+ .data = (ulong)&sun5i_a13_pinctrl_desc,
+ },
+ {
+ .compatible = "allwinner,sun5i-a13-pinctrl",
+ .data = (ulong)&sun5i_a13_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN6I_A31
+ {
+ .compatible = "allwinner,sun6i-a31-pinctrl",
+ .data = (ulong)&sun6i_a31_pinctrl_desc,
+ },
+ {
+ .compatible = "allwinner,sun6i-a31s-pinctrl",
+ .data = (ulong)&sun6i_a31_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN6I_A31_R
+ {
+ .compatible = "allwinner,sun6i-a31-r-pinctrl",
+ .data = (ulong)&sun6i_a31_r_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN7I_A20
+ {
+ .compatible = "allwinner,sun7i-a20-pinctrl",
+ .data = (ulong)&sun7i_a20_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A23
+ {
+ .compatible = "allwinner,sun8i-a23-pinctrl",
+ .data = (ulong)&sun8i_a23_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A23_R
+ {
+ .compatible = "allwinner,sun8i-a23-r-pinctrl",
+ .data = (ulong)&sun8i_a23_r_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A33
+ {
+ .compatible = "allwinner,sun8i-a33-pinctrl",
+ .data = (ulong)&sun8i_a33_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A83T
+ {
+ .compatible = "allwinner,sun8i-a83t-pinctrl",
+ .data = (ulong)&sun8i_a83t_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A83T_R
+ {
+ .compatible = "allwinner,sun8i-a83t-r-pinctrl",
+ .data = (ulong)&sun8i_a83t_r_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_H3
+ {
+ .compatible = "allwinner,sun8i-h3-pinctrl",
+ .data = (ulong)&sun8i_h3_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_H3_R
+ {
+ .compatible = "allwinner,sun8i-h3-r-pinctrl",
+ .data = (ulong)&sun8i_h3_r_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN7I_A20
+ {
+ .compatible = "allwinner,sun8i-r40-pinctrl",
+ .data = (ulong)&sun7i_a20_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_V3S
+ {
+ .compatible = "allwinner,sun8i-v3-pinctrl",
+ .data = (ulong)&sun8i_v3s_pinctrl_desc,
+ },
+ {
+ .compatible = "allwinner,sun8i-v3s-pinctrl",
+ .data = (ulong)&sun8i_v3s_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN9I_A80
+ {
+ .compatible = "allwinner,sun9i-a80-pinctrl",
+ .data = (ulong)&sun9i_a80_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN9I_A80_R
+ {
+ .compatible = "allwinner,sun9i-a80-r-pinctrl",
+ .data = (ulong)&sun9i_a80_r_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A64
+ {
+ .compatible = "allwinner,sun50i-a64-pinctrl",
+ .data = (ulong)&sun50i_a64_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A64_R
+ {
+ .compatible = "allwinner,sun50i-a64-r-pinctrl",
+ .data = (ulong)&sun50i_a64_r_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H5
+ {
+ .compatible = "allwinner,sun50i-h5-pinctrl",
+ .data = (ulong)&sun50i_h5_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H6
+ {
+ .compatible = "allwinner,sun50i-h6-pinctrl",
+ .data = (ulong)&sun50i_h6_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H6_R
+ {
+ .compatible = "allwinner,sun50i-h6-r-pinctrl",
+ .data = (ulong)&sun50i_h6_r_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H616
+ {
+ .compatible = "allwinner,sun50i-h616-pinctrl",
+ .data = (ulong)&sun50i_h616_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H616_R
+ {
+ .compatible = "allwinner,sun50i-h616-r-pinctrl",
+ .data = (ulong)&sun50i_h616_r_pinctrl_desc,
+ },
+#endif
+ {}
+};
+
+U_BOOT_DRIVER(sunxi_pinctrl) = {
+ .name = "sunxi-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = sunxi_pinctrl_ids,
+ .bind = sunxi_pinctrl_bind,
+ .probe = sunxi_pinctrl_probe,
+ .plat_auto = sizeof(struct sunxi_pinctrl_plat),
+ .ops = &sunxi_pinctrl_ops,
+};
#include <linux/iopoll.h>
#define PSC_PTCMD 0x120
+#define PSC_PTCMD_H 0x124
#define PSC_PTSTAT 0x128
+#define PSC_PTSTAT_H 0x12C
#define PSC_PDSTAT 0x200
#define PSC_PDCTL 0x300
#define PSC_MDSTAT 0x800
static int ti_pd_wait(struct ti_pd *pd)
{
u32 ptstat;
+ u32 pdoffset = 0;
+ u32 ptstatreg = PSC_PTSTAT;
int ret;
- ret = readl_poll_timeout(pd->psc->base + PSC_PTSTAT, ptstat,
- !(ptstat & BIT(pd->id)), PD_TIMEOUT);
+ if (pd->id > 31) {
+ pdoffset = 32;
+ ptstatreg = PSC_PTSTAT_H;
+ }
+
+ ret = readl_poll_timeout(pd->psc->base + ptstatreg, ptstat,
+ !(ptstat & BIT(pd->id - pdoffset)), PD_TIMEOUT);
if (ret)
printf("%s: psc%d, pd%d failed to transition.\n", __func__,
static void ti_pd_transition(struct ti_pd *pd)
{
- psc_write(BIT(pd->id), pd->psc, PSC_PTCMD);
+ u32 pdoffset = 0;
+ u32 ptcmdreg = PSC_PTCMD;
+
+ if (pd->id > 31) {
+ pdoffset = 32;
+ ptcmdreg = PSC_PTCMD_H;
+ }
+
+ psc_write(BIT(pd->id - pdoffset), pd->psc, ptcmdreg);
}
u8 ti_pd_state(struct ti_pd *pd)
endif
+config PMIC_TPS65217
+ bool "Enable driver for Texas Instruments TPS65217 PMIC"
+ ---help---
+ The TPS65217 is a PMIC containing several LDOs, DC to DC convertors,
+ FETs and a battery charger. This driver provides register access
+ only, and you can enable the regulator/charger drivers separately if
+ required.
+
config POWER_MC34VR500
bool "Enable driver for Freescale MC34VR500 PMIC"
depends on !DM_PMIC
obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
-obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
static const struct udevice_id pca9450_ids[] = {
{ .compatible = "nxp,pca9450a", .data = 0x25, },
{ .compatible = "nxp,pca9450b", .data = 0x25, },
+ { .compatible = "nxp,pca9450c", .data = 0x25, },
{ }
};
#include <common.h>
#include <i2c.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <power/pmic.h>
#include <power/tps65217.h>
+#if !CONFIG_IS_ENABLED(DM_PMIC)
struct udevice *tps65217_dev __section(".data") = NULL;
/**
#endif
return 0;
}
+#else /* CONFIG_IS_ENABLED(DM_PMIC) */
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo", .driver = "tps65217_ldo" },
+ { },
+};
+
+static int tps65217_reg_count(struct udevice *dev)
+{
+ return TPS65217_PMIC_NUM_OF_REGS;
+}
+
+static int tps65217_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ if (dm_i2c_write(dev, reg, buff, len)) {
+ pr_err("write error to device: %p register: %#x!\n", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int tps65217_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret) {
+ pr_err("read error %d from device: %p register: %#x!\n", ret,
+ dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int tps65217_bind(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found!\n", __func__,
+ dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops tps65217_ops = {
+ .reg_count = tps65217_reg_count,
+ .read = tps65217_read,
+ .write = tps65217_write,
+};
+
+static const struct udevice_id tps65217_ids[] = {
+ { .compatible = "ti,tps65217" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_tps65217) = {
+ .name = "tps65217 pmic",
+ .id = UCLASS_PMIC,
+ .of_match = tps65217_ids,
+ .bind = tps65217_bind,
+ .ops = &tps65217_ops,
+};
+#endif
*/
#include <common.h>
+#include <clk.h>
#include <errno.h>
#include <dm.h>
+#include <linux/delay.h>
#include <log.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include "regulator_common.h"
+struct fixed_clock_regulator_plat {
+ struct clk *enable_clock;
+ unsigned int clk_enable_counter;
+};
+
static int fixed_regulator_of_to_plat(struct udevice *dev)
{
struct dm_regulator_uclass_plat *uc_pdata;
return regulator_common_set_enable(dev, dev_get_plat(dev), enable);
}
+static int fixed_clock_regulator_get_enable(struct udevice *dev)
+{
+ struct fixed_clock_regulator_plat *priv = dev_get_priv(dev);
+
+ return priv->clk_enable_counter > 0;
+}
+
+static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable)
+{
+ struct fixed_clock_regulator_plat *priv = dev_get_priv(dev);
+ struct regulator_common_plat *dev_pdata = dev_get_plat(dev);
+ int ret = 0;
+
+ if (enable) {
+ ret = clk_enable(priv->enable_clock);
+ priv->clk_enable_counter++;
+ } else {
+ ret = clk_disable(priv->enable_clock);
+ priv->clk_enable_counter--;
+ }
+ if (ret)
+ return ret;
+
+ if (enable && dev_pdata->startup_delay_us)
+ udelay(dev_pdata->startup_delay_us);
+
+ if (!enable && dev_pdata->off_on_delay_us)
+ udelay(dev_pdata->off_on_delay_us);
+
+ return ret;
+}
+
static const struct dm_regulator_ops fixed_regulator_ops = {
.get_value = fixed_regulator_get_value,
.get_current = fixed_regulator_get_current,
.set_enable = fixed_regulator_set_enable,
};
+static const struct dm_regulator_ops fixed_clock_regulator_ops = {
+ .get_enable = fixed_clock_regulator_get_enable,
+ .set_enable = fixed_clock_regulator_set_enable,
+};
+
static const struct udevice_id fixed_regulator_ids[] = {
{ .compatible = "regulator-fixed" },
{ },
};
+static const struct udevice_id fixed_clock_regulator_ids[] = {
+ { .compatible = "regulator-fixed-clock" },
+ { },
+};
+
U_BOOT_DRIVER(regulator_fixed) = {
.name = "regulator_fixed",
.id = UCLASS_REGULATOR,
.ops = &fixed_regulator_ops,
.of_match = fixed_regulator_ids,
.of_to_plat = fixed_regulator_of_to_plat,
- .plat_auto = sizeof(struct regulator_common_plat),
+ .plat_auto = sizeof(struct regulator_common_plat),
+};
+
+U_BOOT_DRIVER(regulator_fixed_clock) = {
+ .name = "regulator_fixed_clk",
+ .id = UCLASS_REGULATOR,
+ .ops = &fixed_clock_regulator_ops,
+ .of_match = fixed_clock_regulator_ids,
+ .of_to_plat = fixed_regulator_of_to_plat,
+ .plat_auto = sizeof(struct fixed_clock_regulator_plat),
};
help
Support for PWM hardware on AT91 based SoC.
+config PWM_CADENCE_TTC
+ bool "Enable support for the Cadence TTC PWM"
+ depends on DM_PWM && !CADENCE_TTC_TIMER
+ help
+ Cadence TTC can be configured as timer which is done via
+ CONFIG_CADENCE_TTC_TIMER or as PWM. This is covering only PWM now.
+
config PWM_CROS_EC
bool "Enable support for the Chrome OS EC PWM"
depends on DM_PWM
obj-$(CONFIG_PWM_ASPEED) += pwm-aspeed.o
obj-$(CONFIG_PWM_AT91) += pwm-at91.o
+obj-$(CONFIG_PWM_CADENCE_TTC) += pwm-cadence-ttc.o
obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
-obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
+obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_MESON) += pwm-meson.o
obj-$(CONFIG_PWM_MTK) += pwm-mtk.o
obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021 Xilinx, Inc. Michal Simek
+ */
+
+#define LOG_CATEGORY UCLASS_PWM
+
+#include <clk.h>
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <log.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <log.h>
+#include <div64.h>
+#include <linux/bitfield.h>
+#include <linux/math64.h>
+#include <linux/log2.h>
+#include <dm/device_compat.h>
+
+#define CLOCK_CONTROL 0
+#define COUNTER_CONTROL 0xc
+#define INTERVAL_COUNTER 0x24
+#define MATCH_1_COUNTER 0x30
+
+#define CLK_FALLING_EDGE BIT(6)
+#define CLK_SRC_EXTERNAL BIT(5)
+#define CLK_PRESCALE_MASK GENMASK(4, 1)
+#define CLK_PRESCALE_ENABLE BIT(0)
+
+#define COUNTER_WAVE_POL BIT(6)
+#define COUNTER_WAVE_DISABLE BIT(5)
+#define COUNTER_RESET BIT(4)
+#define COUNTER_MATCH_ENABLE BIT(3)
+#define COUNTER_DECREMENT_ENABLE BIT(2)
+#define COUNTER_INTERVAL_ENABLE BIT(1)
+#define COUNTER_COUNTING_DISABLE BIT(0)
+
+#define NSEC_PER_SEC 1000000000L
+
+#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32))
+#define TTC_CLOCK_CONTROL(reg, channel) \
+ TTC_REG((reg) + CLOCK_CONTROL, (channel))
+#define TTC_COUNTER_CONTROL(reg, channel) \
+ TTC_REG((reg) + COUNTER_CONTROL, (channel))
+#define TTC_INTERVAL_COUNTER(reg, channel) \
+ TTC_REG((reg) + INTERVAL_COUNTER, (channel))
+#define TTC_MATCH_1_COUNTER(reg, channel) \
+ TTC_REG((reg) + MATCH_1_COUNTER, (channel))
+
+struct cadence_ttc_pwm_plat {
+ u8 *regs;
+ u32 timer_width;
+};
+
+struct cadence_ttc_pwm_priv {
+ u8 *regs;
+ u32 timer_width;
+ u32 timer_mask;
+ unsigned long frequency;
+ bool invert[2];
+};
+
+static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel,
+ bool polarity)
+{
+ struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
+
+ if (channel > 2) {
+ dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
+ return -EINVAL;
+ }
+
+ priv->invert[channel] = polarity;
+
+ dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity);
+
+ return 0;
+}
+
+static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel,
+ uint period_ns, uint duty_ns)
+{
+ struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
+ u32 counter_ctrl, clock_ctrl;
+ int period_clocks, duty_clocks, prescaler;
+
+ dev_dbg(dev, "channel %d, duty %d/period %d ns\n", channel,
+ duty_ns, period_ns);
+
+ if (channel > 2) {
+ dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
+ return -EINVAL;
+ }
+
+ /* Make sure counter is stopped */
+ counter_ctrl = readl(TTC_COUNTER_CONTROL(priv->regs, channel));
+ setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
+ COUNTER_COUNTING_DISABLE | COUNTER_WAVE_DISABLE);
+
+ /* Calculate period, prescaler and set clock control register */
+ period_clocks = div64_u64(((int64_t)period_ns * priv->frequency),
+ NSEC_PER_SEC);
+
+ prescaler = ilog2(period_clocks) + 1 - priv->timer_width;
+ if (prescaler < 0)
+ prescaler = 0;
+
+ clock_ctrl = readl(TTC_CLOCK_CONTROL(priv->regs, channel));
+
+ if (!prescaler) {
+ clock_ctrl &= ~(CLK_PRESCALE_ENABLE | CLK_PRESCALE_MASK);
+ } else {
+ clock_ctrl &= ~CLK_PRESCALE_MASK;
+ clock_ctrl |= CLK_PRESCALE_ENABLE;
+ clock_ctrl |= FIELD_PREP(CLK_PRESCALE_MASK, prescaler - 1);
+ };
+
+ /* External source is not handled by this driver now */
+ clock_ctrl &= ~CLK_SRC_EXTERNAL;
+
+ writel(clock_ctrl, TTC_CLOCK_CONTROL(priv->regs, channel));
+
+ /* Calculate interval and set counter control value */
+ duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency),
+ NSEC_PER_SEC);
+
+ writel((period_clocks >> prescaler) & priv->timer_mask,
+ TTC_INTERVAL_COUNTER(priv->regs, channel));
+ writel((duty_clocks >> prescaler) & priv->timer_mask,
+ TTC_MATCH_1_COUNTER(priv->regs, channel));
+
+ /* Restore/reset counter */
+ counter_ctrl &= ~COUNTER_DECREMENT_ENABLE;
+ counter_ctrl |= COUNTER_INTERVAL_ENABLE |
+ COUNTER_RESET |
+ COUNTER_MATCH_ENABLE;
+
+ if (priv->invert[channel])
+ counter_ctrl |= COUNTER_WAVE_POL;
+ else
+ counter_ctrl &= ~COUNTER_WAVE_POL;
+
+ writel(counter_ctrl, TTC_COUNTER_CONTROL(priv->regs, channel));
+
+ dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks,
+ period_clocks, prescaler);
+
+ return 0;
+};
+
+static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel,
+ bool enable)
+{
+ struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
+
+ if (channel > 2) {
+ dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel);
+
+ if (enable) {
+ clrbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
+ COUNTER_COUNTING_DISABLE |
+ COUNTER_WAVE_DISABLE);
+ setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
+ COUNTER_RESET);
+ } else {
+ setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
+ COUNTER_COUNTING_DISABLE |
+ COUNTER_WAVE_DISABLE);
+ }
+
+ return 0;
+};
+
+static int cadence_ttc_pwm_probe(struct udevice *dev)
+{
+ struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
+ struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
+ struct clk clk;
+ int ret;
+
+ priv->regs = plat->regs;
+ priv->timer_width = plat->timer_width;
+ priv->timer_mask = GENMASK(priv->timer_width - 1, 0);
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clock\n");
+ return ret;
+ }
+
+ priv->frequency = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(priv->frequency)) {
+ dev_err(dev, "failed to get rate\n");
+ return priv->frequency;
+ }
+ dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency);
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cadence_ttc_pwm_of_to_plat(struct udevice *dev)
+{
+ struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
+ const char *cells;
+
+ cells = dev_read_prop(dev, "#pwm-cells", NULL);
+ if (!cells)
+ return -EINVAL;
+
+ plat->regs = dev_read_addr_ptr(dev);
+
+ plat->timer_width = dev_read_u32_default(dev, "timer-width", 16);
+
+ return 0;
+}
+
+static int cadence_ttc_pwm_bind(struct udevice *dev)
+{
+ const char *cells;
+
+ cells = dev_read_prop(dev, "#pwm-cells", NULL);
+ if (!cells)
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct pwm_ops cadence_ttc_pwm_ops = {
+ .set_invert = cadence_ttc_pwm_set_invert,
+ .set_config = cadence_ttc_pwm_set_config,
+ .set_enable = cadence_ttc_pwm_set_enable,
+};
+
+static const struct udevice_id cadence_ttc_pwm_ids[] = {
+ { .compatible = "cdns,ttc" },
+ { }
+};
+
+U_BOOT_DRIVER(cadence_ttc_pwm) = {
+ .name = "cadence_ttc_pwm",
+ .id = UCLASS_PWM,
+ .of_match = cadence_ttc_pwm_ids,
+ .ops = &cadence_ttc_pwm_ops,
+ .bind = cadence_ttc_pwm_bind,
+ .of_to_plat = cadence_ttc_pwm_of_to_plat,
+ .probe = cadence_ttc_pwm_probe,
+ .priv_auto = sizeof(struct cadence_ttc_pwm_priv),
+ .plat_auto = sizeof(struct cadence_ttc_pwm_plat),
+};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Basic support for the pwm module on imx6.
- *
- * Based on linux:drivers/pwm/pwm-imx.c
- * from
- * Sascha Hauer <s.hauer@pengutronix.de>
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/arch/imx-regs.h>
-
-/* pwm_id from 0..7 */
-struct pwm_regs *pwm_id_to_reg(int pwm_id)
-{
- switch (pwm_id) {
- case 0:
- return (struct pwm_regs *)PWM1_BASE_ADDR;
- case 1:
- return (struct pwm_regs *)PWM2_BASE_ADDR;
-#ifdef CONFIG_MX6
- case 2:
- return (struct pwm_regs *)PWM3_BASE_ADDR;
- case 3:
- return (struct pwm_regs *)PWM4_BASE_ADDR;
-#endif
-#ifdef CONFIG_MX6SX
- case 4:
- return (struct pwm_regs *)PWM5_BASE_ADDR;
- case 5:
- return (struct pwm_regs *)PWM6_BASE_ADDR;
- case 6:
- return (struct pwm_regs *)PWM7_BASE_ADDR;
- case 7:
- return (struct pwm_regs *)PWM8_BASE_ADDR;
-#endif
- default:
- printf("unknown pwm_id: %d\n", pwm_id);
- break;
- }
- return NULL;
-}
-
-int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
- unsigned long *duty_c, unsigned long *prescale)
-{
- unsigned long long c;
-
- /*
- * we have not yet a clock framework for imx6, so add the clock
- * value here as a define. Replace it when we have the clock
- * framework.
- */
- c = CONFIG_IMX6_PWM_PER_CLK;
- c = c * period_ns;
- do_div(c, 1000000000);
- *period_c = c;
-
- *prescale = *period_c / 0x10000 + 1;
-
- *period_c /= *prescale;
- c = *period_c * (unsigned long long)duty_ns;
- do_div(c, period_ns);
- *duty_c = c;
-
- /*
- * according to imx pwm RM, the real period value should be
- * PERIOD value in PWMPR plus 2.
- */
- if (*period_c > 2)
- *period_c -= 2;
- else
- *period_c = 0;
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Basic support for the pwm module on imx6.
- */
-
-#ifndef _pwm_imx_util_h_
-#define _pwm_imx_util_h_
-
-struct pwm_regs *pwm_id_to_reg(int pwm_id);
-int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
- unsigned long *duty_c, unsigned long *prescale);
-#endif
#include <pwm.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
-#include "pwm-imx-util.h"
-
-int pwm_init(int pwm_id, int div, int invert)
-{
- struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
-
- if (!pwm)
- return -1;
-
- writel(0, &pwm->ir);
- return 0;
-}
+#include <clk.h>
int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
unsigned long duty_cycles, unsigned long prescale)
return 0;
}
+#ifndef CONFIG_DM_PWM
+/* pwm_id from 0..7 */
+struct pwm_regs *pwm_id_to_reg(int pwm_id)
+{
+
+ switch (pwm_id) {
+ case 0:
+ return (struct pwm_regs *)PWM1_BASE_ADDR;
+ case 1:
+ return (struct pwm_regs *)PWM2_BASE_ADDR;
+#ifdef CONFIG_MX6
+ case 2:
+ return (struct pwm_regs *)PWM3_BASE_ADDR;
+ case 3:
+ return (struct pwm_regs *)PWM4_BASE_ADDR;
+#endif
+#ifdef CONFIG_MX6SX
+ case 4:
+ return (struct pwm_regs *)PWM5_BASE_ADDR;
+ case 5:
+ return (struct pwm_regs *)PWM6_BASE_ADDR;
+ case 6:
+ return (struct pwm_regs *)PWM7_BASE_ADDR;
+ case 7:
+ return (struct pwm_regs *)PWM8_BASE_ADDR;
+#endif
+ default:
+ printf("unknown pwm_id: %d\n", pwm_id);
+ break;
+ }
+ return NULL;
+}
+
+int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
+ unsigned long *duty_c, unsigned long *prescale)
+{
+ unsigned long long c;
+
+ /*
+ * we have not yet a clock framework for imx6, so add the clock
+ * value here as a define. Replace it when we have the clock
+ * framework.
+ */
+ c = CONFIG_IMX6_PWM_PER_CLK;
+ c = c * period_ns;
+ do_div(c, 1000000000);
+ *period_c = c;
+
+ *prescale = *period_c / 0x10000 + 1;
+
+ *period_c /= *prescale;
+ c = *period_c * (unsigned long long)duty_ns;
+ do_div(c, period_ns);
+ *duty_c = c;
+
+ /*
+ * according to imx pwm RM, the real period value should be
+ * PERIOD value in PWMPR plus 2.
+ */
+ if (*period_c > 2)
+ *period_c -= 2;
+ else
+ *period_c = 0;
+
+ return 0;
+}
+
+int pwm_init(int pwm_id, int div, int invert)
+{
+ struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+
+ if (!pwm)
+ return -1;
+
+ writel(0, &pwm->ir);
+ return 0;
+}
+
int pwm_config(int pwm_id, int duty_ns, int period_ns)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
clrbits_le32(&pwm->cr, PWMCR_EN);
}
-#if defined(CONFIG_DM_PWM)
+#else
struct imx_pwm_priv {
struct pwm_regs *regs;
bool invert;
+ struct clk per_clk;
+ struct clk ipg_clk;
};
+int pwm_dm_imx_get_parms(struct imx_pwm_priv *priv, int period_ns,
+ int duty_ns, unsigned long *period_c, unsigned long *duty_c,
+ unsigned long *prescale)
+{
+ unsigned long long c;
+
+ c = clk_get_rate(&priv->per_clk);
+ c = c * period_ns;
+ do_div(c, 1000000000);
+ *period_c = c;
+
+ *prescale = *period_c / 0x10000 + 1;
+
+ *period_c /= *prescale;
+ c = *period_c * (unsigned long long)duty_ns;
+ do_div(c, period_ns);
+ *duty_c = c;
+
+ /*
+ * according to imx pwm RM, the real period value should be
+ * PERIOD value in PWMPR plus 2.
+ */
+ if (*period_c > 2)
+ *period_c -= 2;
+ else
+ *period_c = 0;
+
+ return 0;
+}
+
static int imx_pwm_set_invert(struct udevice *dev, uint channel,
bool polarity)
{
debug("%s: Config '%s' channel: %d\n", __func__, dev->name, channel);
- pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
+ pwm_dm_imx_get_parms(priv, period_ns, duty_ns, &period_cycles, &duty_cycles,
&prescale);
return pwm_config_internal(regs, period_cycles, duty_cycles, prescale);
static int imx_pwm_of_to_plat(struct udevice *dev)
{
+ int ret;
struct imx_pwm_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr_ptr(dev);
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret) {
+ printf("Failed to get per_clk\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
+ if (ret) {
+ printf("Failed to get ipg_clk\n");
+ return ret;
+ }
+
return 0;
}
static int imx_pwm_probe(struct udevice *dev)
{
+ int ret;
+ struct imx_pwm_priv *priv = dev_get_priv(dev);
+
+ ret = clk_enable(&priv->per_clk);
+ if (ret) {
+ printf("Failed to enable per_clk\n");
+ return ret;
+ }
+
+ ret = clk_enable(&priv->ipg_clk);
+ if (ret) {
+ printf("Failed to enable ipg_clk\n");
+ return ret;
+ }
+
return 0;
}
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/pwm.h>
-#include <asm/arch/gpio.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
1, /* 1111 */
};
-static int sunxi_pwm_config_pinmux(void)
-{
-#ifdef CONFIG_MACH_SUN50I
- sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
-#endif
- return 0;
-}
-
static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
bool polarity)
{
return 0;
}
- sunxi_pwm_config_pinmux();
-
if (priv->invert)
v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
else
ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, cfg->ddrphy_dx2gcr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR1, cfg->ddrphy_dx2gcr1);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR2, cfg->ddrphy_dx2gcr2);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR3, cfg->ddrphy_dx2gcr3);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, cfg->ddrphy_dx3gcr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR1, cfg->ddrphy_dx3gcr1);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR2, cfg->ddrphy_dx3gcr2);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR3, cfg->ddrphy_dx3gcr3);
+
ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
device_get_supply_regulator(ddrss->dev, "vtt-supply",
&ddrss->vtt_supply);
ret = regulator_set_value(ddrss->vtt_supply, 3300000);
- if (ret)
- return ret;
- debug("VTT regulator enabled\n");
+ if (ret == 0)
+ debug("VTT regulator enabled\n");
#endif
return 0;
*/
#include <common.h>
+#include <config.h>
#include <clk.h>
+#include <div64.h>
#include <dm.h>
#include <dm/device_compat.h>
+#include <fdt_support.h>
#include <ram.h>
#include <hang.h>
#include <log.h>
#define DDRSS_V2A_R1_MAT_REG 0x0020
#define DDRSS_ECC_CTRL_REG 0x0120
+#define DDRSS_ECC_CTRL_REG_ECC_EN BIT(0)
+#define DDRSS_ECC_CTRL_REG_RMW_EN BIT(1)
+#define DDRSS_ECC_CTRL_REG_ECC_CK BIT(2)
+#define DDRSS_ECC_CTRL_REG_WR_ALLOC BIT(4)
+
+#define DDRSS_ECC_R0_STR_ADDR_REG 0x0130
+#define DDRSS_ECC_R0_END_ADDR_REG 0x0134
+#define DDRSS_ECC_R1_STR_ADDR_REG 0x0138
+#define DDRSS_ECC_R1_END_ADDR_REG 0x013c
+#define DDRSS_ECC_R2_STR_ADDR_REG 0x0140
+#define DDRSS_ECC_R2_END_ADDR_REG 0x0144
+#define DDRSS_ECC_1B_ERR_CNT_REG 0x0150
+
#define SINGLE_DDR_SUBSYSTEM 0x1
#define MULTI_DDR_SUBSYSTEM 0x2
enum emif_active active;
};
+#define K3_DDRSS_MAX_ECC_REGIONS 3
+
+struct k3_ddrss_ecc_region {
+ u32 start;
+ u32 range;
+};
+
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
void __iomem *ddrss_ctrl_mmr;
+ void __iomem *ddrss_ctl_cfg;
struct power_domain ddrcfg_pwrdmn;
struct power_domain ddrdata_pwrdmn;
struct clk ddr_clk;
lpddr4_obj *driverdt;
lpddr4_config config;
lpddr4_privatedata pd;
+ struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS];
+ u64 ecc_reserved_space;
+ bool ti_ecc_enabled;
};
struct reginitdata {
dev_err(dev, "No reg property for DDRSS wrapper logic\n");
return -EINVAL;
}
- ddrss->ddrss_ss_cfg = (void *)reg;
+ ddrss->ddrss_ctl_cfg = (void *)reg;
reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
if (reg == FDT_ADDR_T_NONE) {
}
ddrss->ddrss_ctrl_mmr = (void *)reg;
+ reg = dev_read_addr_name(dev, "ss_cfg");
+ if (reg == FDT_ADDR_T_NONE) {
+ dev_dbg(dev, "No reg property for SS Config region, but this is optional so continuing.\n");
+ ddrss->ddrss_ss_cfg = NULL;
+ } else {
+ ddrss->ddrss_ss_cfg = (void *)reg;
+ }
+
ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
if (ret) {
dev_err(dev, "power_domain_get() failed: %d\n", ret);
if (ret)
dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
+ ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable");
+
return ret;
}
hang();
}
- config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
+ config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ctl_cfg;
config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
status = driverdt->init(pd, config);
}
}
+static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size)
+{
+ writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG);
+ writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG);
+}
+
+static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word)
+{
+ int i;
+
+ printf("ECC is enabled, priming DDR which will take several seconds.\n");
+
+ for (i = 0; i < (size / 4); i++)
+ addr[i] = word;
+}
+
+static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
+{
+ fdtdec_setup_mem_size_base_lowest();
+
+ ddrss->ecc_reserved_space = gd->ram_size;
+ do_div(ddrss->ecc_reserved_space, 9);
+
+ /* Round to clean number */
+ ddrss->ecc_reserved_space = 1ull << (fls(ddrss->ecc_reserved_space));
+}
+
+static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
+{
+ u32 ecc_region_start = ddrss->ecc_regions[0].start;
+ u32 ecc_range = ddrss->ecc_regions[0].range;
+ u32 base = (u32)ddrss->ddrss_ss_cfg;
+ u32 val;
+
+ /* Only Program region 0 which covers full ddr space */
+ k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range);
+
+ /* Enable ECC, RMW, WR_ALLOC */
+ writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN |
+ DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG);
+
+ /* Preload ECC Mem region with 0's */
+ k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range,
+ 0x00000000);
+
+ /* Clear Error Count Register */
+ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);
+
+ /* Enable ECC Check */
+ val = readl(base + DDRSS_ECC_CTRL_REG);
+ val |= DDRSS_ECC_CTRL_REG_ECC_CK;
+ writel(val, base + DDRSS_ECC_CTRL_REG);
+}
+
static int k3_ddrss_probe(struct udevice *dev)
{
int ret;
k3_lpddr4_start(ddrss);
+ if (ddrss->ti_ecc_enabled) {
+ if (!ddrss->ddrss_ss_cfg) {
+ printf("%s: ss_cfg is required if ecc is enabled but not provided.",
+ __func__);
+ return -EINVAL;
+ }
+
+ k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss);
+
+ /* Always configure one region that covers full DDR space */
+ ddrss->ecc_regions[0].start = gd->ram_base;
+ ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space;
+ k3_ddrss_lpddr4_ecc_init(ddrss);
+ }
+
return ret;
}
+int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd)
+{
+ struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+ int bank;
+
+ if (ddrss->ecc_reserved_space == 0)
+ return 0;
+
+ for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) {
+ if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) {
+ ddrss->ecc_reserved_space -= bd->bi_dram[bank].size;
+ bd->bi_dram[bank].size = 0;
+ } else {
+ bd->bi_dram[bank].size -= ddrss->ecc_reserved_space;
+ break;
+ }
+ }
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start[bank] = bd->bi_dram[bank].start;
+ size[bank] = bd->bi_dram[bank].size;
+ }
+
+ return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
+
static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
{
return 0;
This driver provides support for the Random Number
Generator hardware found on Qualcomm SoCs.
+config RNG_OPTEE
+ bool "OP-TEE based Random Number Generator support"
+ depends on DM_RNG && OPTEE
+ help
+ This driver provides support for the OP-TEE based Random Number
+ Generator on ARM SoCs where hardware entropy sources are not
+ accessible to normal world but reserved and used by the OP-TEE
+ to avoid the weakness of a software PRNG.
+
config RNG_STM32MP1
bool "Enable random number generator for STM32MP1"
depends on ARCH_STM32MP
obj-$(CONFIG_RNG_MESON) += meson-rng.o
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
obj-$(CONFIG_RNG_MSM) += msm_rng.o
+obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ */
+#define LOG_CATEGORY UCLASS_RNG
+
+#include <common.h>
+
+#include <rng.h>
+#include <tee.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <linux/sizes.h>
+
+#define TEE_ERROR_HEALTH_TEST_FAIL 0x00000001
+
+/*
+ * TA_CMD_GET_ENTROPY - Get Entropy from RNG
+ *
+ * param[0] (inout memref) - Entropy buffer memory reference
+ * param[1] unused
+ * param[2] unused
+ * param[3] unused
+ *
+ * Result:
+ * TEE_SUCCESS - Invoke command success
+ * TEE_ERROR_BAD_PARAMETERS - Incorrect input param
+ * TEE_ERROR_NOT_SUPPORTED - Requested entropy size greater than size of pool
+ * TEE_ERROR_HEALTH_TEST_FAIL - Continuous health testing failed
+ */
+#define TA_CMD_GET_ENTROPY 0x0
+
+#define MAX_ENTROPY_REQ_SZ SZ_4K
+
+#define TA_HWRNG_UUID { 0xab7a617c, 0xb8e7, 0x4d8f, \
+ { 0x83, 0x01, 0xd0, 0x9b, 0x61, 0x03, 0x6b, 0x64 } }
+
+/** open_session_ta_hwrng() - Open session with hwrng Trusted App
+ *
+ * @dev: device
+ * @session_id: return the RNG TA session identifier
+ * Return: 0 if ok
+ */
+static int open_session_ta_hwrng(struct udevice *dev, u32 *session_id)
+{
+ const struct tee_optee_ta_uuid uuid = TA_HWRNG_UUID;
+ struct tee_open_session_arg sess_arg = {0};
+ int ret;
+
+ /* Open session with hwrng Trusted App */
+ tee_optee_ta_uuid_to_octets(sess_arg.uuid, &uuid);
+ sess_arg.clnt_login = TEE_LOGIN_PUBLIC;
+
+ ret = tee_open_session(dev->parent, &sess_arg, 0, NULL);
+ if (ret || sess_arg.ret) {
+ if (!ret)
+ ret = -EIO;
+ return ret;
+ }
+
+ *session_id = sess_arg.session;
+ return 0;
+}
+
+/**
+ * get_optee_rng_data() - read RNG data from OP-TEE TA
+ *
+ * @dev: device
+ * @session_id: the RNG TA session identifier
+ * @entropy_shm_pool: shared memory pool used for TEE message
+ * @buf: buffer to receive data
+ * @size: size of buffer, limited by entropy_shm_pool size
+ * Return: 0 if ok
+ */
+static int get_optee_rng_data(struct udevice *dev, u32 session_id,
+ struct tee_shm *entropy_shm_pool,
+ void *buf, size_t *size)
+{
+ int ret = 0;
+ struct tee_invoke_arg arg = {0};
+ struct tee_param param = {0};
+
+ /* Invoke TA_CMD_GET_ENTROPY function of Trusted App */
+ arg.func = TA_CMD_GET_ENTROPY;
+ arg.session = session_id;
+
+ /* Fill invoke cmd params */
+ param.attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT;
+ param.u.memref.shm = entropy_shm_pool;
+ param.u.memref.size = *size;
+
+ ret = tee_invoke_func(dev->parent, &arg, 1, ¶m);
+ if (ret || arg.ret) {
+ if (!ret)
+ ret = -EPROTO;
+ dev_err(dev, "TA_CMD_GET_ENTROPY invoke err: %d 0x%x\n", ret, arg.ret);
+ *size = 0;
+
+ return ret;
+ }
+
+ memcpy(buf, param.u.memref.shm->addr, param.u.memref.size);
+ *size = param.u.memref.size;
+
+ return 0;
+}
+
+/**
+ * optee_rng_read() - rng read ops for OP-TEE RNG device
+ *
+ * @dev: device
+ * @buf: buffer to receive data
+ * @len: size of buffer
+ * Return: 0 if ok
+ */
+static int optee_rng_read(struct udevice *dev, void *buf, size_t len)
+{
+ size_t read = 0, rng_size = 0;
+ struct tee_shm *entropy_shm_pool;
+ u8 *data = buf;
+ int ret;
+ u32 session_id = 0;
+
+ ret = open_session_ta_hwrng(dev, &session_id);
+ if (ret) {
+ dev_err(dev, "can't open session: %d\n", ret);
+ return ret;
+ }
+
+ ret = tee_shm_alloc(dev->parent, MAX_ENTROPY_REQ_SZ, 0, &entropy_shm_pool);
+ if (ret) {
+ dev_err(dev, "tee_shm_alloc failed: %d\n", ret);
+ goto session_close;
+ }
+
+ while (read < len) {
+ rng_size = min(len - read, (size_t)MAX_ENTROPY_REQ_SZ);
+ ret = get_optee_rng_data(dev, session_id, entropy_shm_pool, data, &rng_size);
+ if (ret)
+ goto shm_free;
+ data += rng_size;
+ read += rng_size;
+ }
+
+shm_free:
+ tee_shm_free(entropy_shm_pool);
+
+session_close:
+ tee_close_session(dev->parent, session_id);
+
+ return ret;
+}
+
+/**
+ * optee_rng_probe() - probe function for OP-TEE RNG device
+ *
+ * @dev: device
+ * Return: 0 if ok
+ */
+static int optee_rng_probe(struct udevice *dev)
+{
+ int ret;
+ u32 session_id;
+
+ ret = open_session_ta_hwrng(dev, &session_id);
+ if (ret) {
+ dev_err(dev, "can't open session: %d\n", ret);
+ return ret;
+ }
+ tee_close_session(dev->parent, session_id);
+
+ return 0;
+}
+
+static const struct dm_rng_ops optee_rng_ops = {
+ .read = optee_rng_read,
+};
+
+U_BOOT_DRIVER(optee_rng) = {
+ .name = "optee-rng",
+ .id = UCLASS_RNG,
+ .ops = &optee_rng_ops,
+ .probe = optee_rng_probe,
+};
ata_swap_buf_le16((u16 *)&bdesc->revision, sizeof(bd.revision) / 2);
}
+ ret = blk_probe_or_unbind(bdev);
+ if (ret < 0)
+ /* TODO: undo create */
+ return ret;
+
if (verbose) {
printf(" Device %d: ", bdesc->devnum);
dev_print(bdesc);
config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX
+ imply SERIAL_PUTS
help
Select this to enable a seral UART for sandbox. This is required to
operate correctly, otherwise you will see no serial output from
on systems with RCar or SH SoCs, say Y to this option. If unsure,
say N.
+choice
+ prompt "SCIF console port"
+ depends on SCIF_CONSOLE && (!DM_SERIAL || (SPL && !SPL_DM_SERIAL))
+
+config CONS_SCIF0
+ bool "SCIF0"
+
+config CONS_SCIF1
+ bool "SCIF1"
+
+config CONS_SCIF2
+ bool "SCIF2"
+
+config CONS_SCIF4
+ bool "SCIF4"
+
+config CONS_SCIFA0
+ bool "SCIFA0"
+
+endchoice
+
+config SH_SCIF_CLK_FREQ
+ int "SCIF console clock frequency"
+ depends on SCIF_CONSOLE && (!DM_SERIAL || (SPL && !SPL_DM_SERIAL))
+ default 65000000
+
config SEMIHOSTING_SERIAL
bool "Semihosting UART support"
depends on SEMIHOSTING && !SERIAL_RX_BUFFER
+ imply SERIAL_PUTS
help
Select this to enable a serial UART using semihosting. Special halt
instructions will be issued which an external debugger (such as a
DECLARE_GLOBAL_DATA_PTR;
+static size_t _sandbox_serial_written = 1;
+static bool sandbox_serial_enabled = true;
+
+size_t sandbox_serial_written(void)
+{
+ return _sandbox_serial_written;
+}
+
+void sandbox_serial_endisable(bool enabled)
+{
+ sandbox_serial_enabled = enabled;
+}
+
/**
* output_ansi_colour() - Output an ANSI colour code
*
return 0;
}
-static int sandbox_serial_putc(struct udevice *dev, const char ch)
+static void sandbox_print_color(struct udevice *dev)
{
struct sandbox_serial_priv *priv = dev_get_priv(dev);
struct sandbox_serial_plat *plat = dev_get_plat(dev);
priv->start_of_line = false;
output_ansi_colour(plat->colour);
}
+}
+
+static int sandbox_serial_putc(struct udevice *dev, const char ch)
+{
+ struct sandbox_serial_priv *priv = dev_get_priv(dev);
- os_write(1, &ch, 1);
if (ch == '\n')
priv->start_of_line = true;
+ if (sandbox_serial_enabled) {
+ sandbox_print_color(dev);
+ os_write(1, &ch, 1);
+ }
+ _sandbox_serial_written += 1;
return 0;
}
+static ssize_t sandbox_serial_puts(struct udevice *dev, const char *s,
+ size_t len)
+{
+ struct sandbox_serial_priv *priv = dev_get_priv(dev);
+ ssize_t ret;
+
+ if (s[len - 1] == '\n')
+ priv->start_of_line = true;
+
+ if (sandbox_serial_enabled) {
+ sandbox_print_color(dev);
+ ret = os_write(1, s, len);
+ if (ret < 0)
+ return ret;
+ } else {
+ ret = len;
+ }
+ _sandbox_serial_written += ret;
+ return ret;
+}
+
static int sandbox_serial_pending(struct udevice *dev, bool input)
{
struct sandbox_serial_priv *priv = dev_get_priv(dev);
static const struct dm_serial_ops sandbox_serial_ops = {
.putc = sandbox_serial_putc,
+ .puts = sandbox_serial_puts,
.pending = sandbox_serial_pending,
.getc = sandbox_serial_getc,
.getconfig = sandbox_serial_getconfig,
} while (err == -EAGAIN);
}
+static int __serial_puts(struct udevice *dev, const char *str, size_t len)
+{
+ struct dm_serial_ops *ops = serial_get_ops(dev);
+
+ do {
+ ssize_t written = ops->puts(dev, str, len);
+
+ if (written < 0)
+ return written;
+ str += written;
+ len -= written;
+ } while (len);
+
+ return 0;
+}
+
static void _serial_puts(struct udevice *dev, const char *str)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
do {
const char *newline = strchrnul(str, '\n');
- size_t len = newline - str + !!*newline;
+ size_t len = newline - str;
- do {
- ssize_t written = ops->puts(dev, str, len);
+ if (__serial_puts(dev, str, len))
+ return;
- if (written < 0)
- return;
- str += written;
- len -= written;
- } while (len);
+ if (*newline && __serial_puts(dev, "\r\n", 2))
+ return;
- if (*newline)
- _serial_putc(dev, '\r');
+ str += len + !!*newline;
} while (*str);
}
#include <common.h>
#include <dm.h>
+#include <malloc.h>
#include <serial.h>
#include <semihosting.h>
/**
* struct smh_serial_priv - Semihosting serial private data
* @infd: stdin file descriptor (or error)
+ * @outfd: stdout file descriptor (or error)
*/
struct smh_serial_priv {
int infd;
return 0;
}
+static ssize_t smh_serial_puts(struct udevice *dev, const char *s, size_t len)
+{
+ int ret;
+ struct smh_serial_priv *priv = dev_get_priv(dev);
+ unsigned long written;
+
+ if (priv->outfd < 0) {
+ char *buf;
+
+ /* Try and avoid a copy if we can */
+ if (!s[len + 1]) {
+ smh_puts(s);
+ return len;
+ }
+
+ buf = strndup(s, len);
+ smh_puts(buf);
+ free(buf);
+ return len;
+ }
+
+ ret = smh_write(priv->outfd, s, len, &written);
+ if (written)
+ return written;
+ return ret;
+}
+
static const struct dm_serial_ops smh_serial_ops = {
.putc = smh_serial_putc,
+ .puts = smh_serial_puts,
.getc = smh_serial_getc,
};
struct smh_serial_priv *priv = dev_get_priv(dev);
priv->infd = smh_open(":tt", MODE_READ);
+ priv->outfd = smh_open(":tt", MODE_WRITE);
return 0;
}
#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
+#define ZYNQ_UART_SR_TXEMPTY BIT(3) /* TX FIFO empty */
#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
#define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
{
- if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL)
- return -EAGAIN;
+ if (CONFIG_IS_ENABLED(DEBUG_UART_ZYNQ)) {
+ if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
+ return -EAGAIN;
+ } else {
+ if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL)
+ return -EAGAIN;
+ }
writel(c, ®s->tx_rx_fifo);
used to access the SPI NOR flash on platforms embedding this
Cadence IP core.
+config HAS_CQSPI_REF_CLK
+ bool "Cadence QSPI static reference clock"
+ depends on CADENCE_QSPI
+
+config CQSPI_REF_CLK
+ int "Cadence QSPI reference clock value in Hz"
+ depends on HAS_CQSPI_REF_CLK
+
config CF_SPI
bool "ColdFire SPI driver"
help
if (plat->ref_clk_hz == 0) {
ret = clk_get_by_index(bus, 0, &clk);
if (ret) {
-#ifdef CONFIG_CQSPI_REF_CLK
+#ifdef CONFIG_HAS_CQSPI_REF_CLK
plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
+#elif defined(CONFIG_ARCH_SOCFPGA)
+ plat->ref_clk_hz = cm_get_qspi_controller_clk_hz();
#else
return ret;
#endif
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
void cadence_qspi_apb_readdata_capture(void *reg_base,
unsigned int bypass, unsigned int delay);
+unsigned int cm_get_qspi_controller_clk_hz(void);
#endif /* __CADENCE_QSPI_H__ */
static const struct udevice_id nxp_fspi_ids[] = {
{ .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
{ .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, },
+ { .compatible = "nxp,imx8mp-fspi", .data = (ulong)&imx8mm_data, },
{ }
};
#include <linux/bitops.h>
#include <asm/bitops.h>
-#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/iopoll.h>
writel(reg, SPI_REG(priv, SPI_TCR));
}
-static int sun4i_spi_parse_pins(struct udevice *dev)
-{
- const void *fdt = gd->fdt_blob;
- const char *pin_name;
- const fdt32_t *list;
- u32 phandle;
- int drive, pull = 0, pin, i;
- int offset;
- int size;
-
- list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
- if (!list) {
- printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
- return -EINVAL;
- }
-
- while (size) {
- phandle = fdt32_to_cpu(*list++);
- size -= sizeof(*list);
-
- offset = fdt_node_offset_by_phandle(fdt, phandle);
- if (offset < 0)
- return offset;
-
- drive = fdt_getprop_u32_default_node(fdt, offset, 0,
- "drive-strength", 0);
- if (drive) {
- if (drive <= 10)
- drive = 0;
- else if (drive <= 20)
- drive = 1;
- else if (drive <= 30)
- drive = 2;
- else
- drive = 3;
- } else {
- drive = fdt_getprop_u32_default_node(fdt, offset, 0,
- "allwinner,drive",
- 0);
- drive = min(drive, 3);
- }
-
- if (fdt_get_property(fdt, offset, "bias-disable", NULL))
- pull = 0;
- else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
- pull = 1;
- else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
- pull = 2;
- else
- pull = fdt_getprop_u32_default_node(fdt, offset, 0,
- "allwinner,pull",
- 0);
- pull = min(pull, 2);
-
- for (i = 0; ; i++) {
- pin_name = fdt_stringlist_get(fdt, offset,
- "pins", i, NULL);
- if (!pin_name) {
- pin_name = fdt_stringlist_get(fdt, offset,
- "allwinner,pins",
- i, NULL);
- if (!pin_name)
- break;
- }
-
- pin = sunxi_name_to_gpio(pin_name);
- if (pin < 0)
- break;
-
- if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
- IS_ENABLED(CONFIG_SUN50I_GEN_H6))
- sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
- else
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
- sunxi_gpio_set_drv(pin, drive);
- sunxi_gpio_set_pull(pin, pull);
- }
- }
- return 0;
-}
-
static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
{
struct sun4i_spi_priv *priv = dev_get_priv(dev);
return ret;
}
- sun4i_spi_parse_pins(bus);
-
priv->variant = plat->variant;
priv->base = plat->base;
priv->freq = plat->max_hz;
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
+#include <dm/lists.h>
#include <log.h>
#include <malloc.h>
#include <tee.h>
{
struct optee_pdata *pdata = dev_get_plat(dev);
u32 sec_caps;
+ struct udevice *child;
+ int ret;
if (!is_optee_api(pdata->invoke_fn)) {
dev_err(dev, "OP-TEE api uid mismatch\n");
return -ENOENT;
}
+ /*
+ * in U-Boot, the discovery of TA on the TEE bus is not supported:
+ * only bind the drivers associated to the supported OP-TEE TA
+ */
+ if (IS_ENABLED(CONFIG_RNG_OPTEE)) {
+ ret = device_bind_driver(dev, "optee-rng", "optee-rng", &child);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
return 0;
}
+static int cadence_ttc_bind(struct udevice *dev)
+{
+ const char *cells;
+
+ cells = dev_read_prop(dev, "#pwm-cells", NULL);
+ if (cells)
+ return -ENODEV;
+
+ return 0;
+}
+
static const struct timer_ops cadence_ttc_ops = {
.get_count = cadence_ttc_get_count,
};
.priv_auto = sizeof(struct cadence_ttc_priv),
.probe = cadence_ttc_probe,
.ops = &cadence_ttc_ops,
+ .bind = cadence_ttc_bind,
};
obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
-obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
obj-$(CONFIG_USB_OHCI_PCI) += ohci-pci.o
obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013
- * Sergey Kostanbaev < sergey.kostanbaev <at> fairwaves.ru >
- */
-
-#include <config.h>
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-#include <asm/io.h>
-#include <asm/arch/ep93xx.h>
-
-int usb_cpu_init(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- unsigned long pwr = readl(&syscon->pwrcnt);
- writel(pwr | SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
-
- return 0;
-}
-
-int usb_cpu_stop(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- unsigned long pwr = readl(&syscon->pwrcnt);
- writel(pwr & ~SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
-
- return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
- return usb_cpu_stop();
-}
-
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
return ret;
}
- if (IS_ENABLED(CONFIG_VIDEO_LOGO) && !plat->hide_logo) {
+ if (IS_ENABLED(CONFIG_VIDEO_LOGO) &&
+ !IS_ENABLED(CONFIG_SPLASH_SCREEN) && !plat->hide_logo) {
ret = show_splash(dev);
if (ret) {
log_debug("Cannot show splash screen\n");
DECLARE_GLOBAL_DATA_PTR;
-static char *env_fat_device_and_part(void)
+__weak const char *env_fat_get_intf(void)
+{
+ return (const char *)CONFIG_ENV_FAT_INTERFACE;
+}
+
+__weak char *env_fat_get_dev_part(void)
{
#ifdef CONFIG_MMC
static char *part_str;
int dev, part;
int err;
loff_t size;
+ const char *ifname = env_fat_get_intf();
+ const char *dev_and_part = env_fat_get_dev_part();
err = env_export(&env_new);
if (err)
return err;
- part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
- env_fat_device_and_part(),
- &dev_desc, &info, 1);
+ part = blk_get_device_part_str(ifname, dev_and_part,
+ &dev_desc, &info, 1);
if (part < 0)
return 1;
* This printf is embedded in the messages from env_save that
* will calling it. The missing \n is intentional.
*/
- printf("Unable to use %s %d:%d... \n",
- CONFIG_ENV_FAT_INTERFACE, dev, part);
+ printf("Unable to use %s %d:%d...\n", ifname, dev, part);
return 1;
}
* This printf is embedded in the messages from env_save that
* will calling it. The missing \n is intentional.
*/
- printf("Unable to write \"%s\" from %s%d:%d... \n",
- file, CONFIG_ENV_FAT_INTERFACE, dev, part);
+ printf("Unable to write \"%s\" from %s%d:%d...\n", file, ifname, dev, part);
return 1;
}
struct disk_partition info;
int dev, part;
int err1;
+ const char *ifname = env_fat_get_intf();
+ const char *dev_and_part = env_fat_get_dev_part();
#ifdef CONFIG_MMC
- if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc"))
+ if (!strcmp(ifname, "mmc"))
mmc_initialize(NULL);
#endif
- part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
- env_fat_device_and_part(),
- &dev_desc, &info, 1);
+ part = blk_get_device_part_str(ifname, dev_and_part,
+ &dev_desc, &info, 1);
if (part < 0)
goto err_env_relocate;
* This printf is embedded in the messages from env_save that
* will calling it. The missing \n is intentional.
*/
- printf("Unable to use %s %d:%d... \n",
- CONFIG_ENV_FAT_INTERFACE, dev, part);
+ printf("Unable to use %s %d:%d...\n", ifname, dev, part);
goto err_env_relocate;
}
* will calling it. The missing \n is intentional.
*/
printf("Unable to read \"%s\" from %s%d:%d... \n",
- CONFIG_ENV_FAT_FILE, CONFIG_ENV_FAT_INTERFACE, dev, part);
+ CONFIG_ENV_FAT_FILE, ifname, dev, part);
goto err_env_relocate;
}
};
static struct fstype_info fstypes[] = {
-#ifdef CONFIG_FS_FAT
+#if CONFIG_IS_ENABLED(FS_FAT)
{
.fstype = FS_TYPE_FAT,
.name = "fat",
.ln = fs_ln_unsupported,
},
#endif
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_CMD_UBIFS
{
.fstype = FS_TYPE_UBIFS,
.ln = fs_ln_unsupported,
},
#endif
+#endif
#ifdef CONFIG_FS_BTRFS
{
.fstype = FS_TYPE_BTRFS,
NOT_ON_MEDIA = 3,
};
+static int try_read_node(const struct ubifs_info *c, void *buf, int type,
+ int len, int lnum, int offs);
+static int fallible_read_node(struct ubifs_info *c, const union ubifs_key *key,
+ struct ubifs_zbranch *zbr, void *node);
+
/**
* insert_old_idx - record an index node obsoleted since the last commit start.
* @c: UBIFS file-system description object
return 0;
}
- err = ubifs_tnc_read_node(c, zbr, node);
+ if (c->replaying) {
+ err = fallible_read_node(c, &zbr->key, zbr, node);
+ /*
+ * When the node was not found, return -ENOENT, 0 otherwise.
+ * Negative return codes stay as-is.
+ */
+ if (err == 0)
+ err = -ENOENT;
+ else if (err == 1)
+ err = 0;
+ } else {
+ err = ubifs_tnc_read_node(c, zbr, node);
+ }
if (err)
return err;
if (nm->name) {
if (err) {
/* Handle collisions */
- err = resolve_collision(c, key, &znode, &n, nm);
+ if (c->replaying)
+ err = fallible_resolve_collision(c, key, &znode, &n,
+ nm, 0);
+ else
+ err = resolve_collision(c, key, &znode, &n, nm);
dbg_tnc("rc returned %d, znode %p, n %d",
err, znode, n);
if (unlikely(err < 0))
/* CM926EJ-S */
/* CM1136-EJ-S */
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
-#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */
- /* - PLL test clock bypassed */
- /* - bus clock ratio 2 */
- /* - little endian */
- /* - vectors at zero */
-#endif /* CM1022xx */
-
-/* Determine CM characteristics */
-
-#undef CONFIG_CM_MULTIPLE_SSRAM
-#undef CONFIG_CM_SPD_DETECT
-#undef CONFIG_CM_REMAP
-#undef CONFIG_CM_INIT
-#undef CONFIG_CM_TCRAM
-
-#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
-#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
-#endif
-
-/* Excalibur core module has reduced functionality */
-#ifndef CONFIG_CM922T_XA10
-#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
-#define OS_SPD 0x00000100 /* Address of SPD data */
-#define CONFIG_CM_REMAP /* CM supports remapping */
-#define CONFIG_CM_INIT /* CM has initialization reg */
-#endif /* NOT EXCALIBUR */
-
-#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
- defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
- defined(CONFIG_CM1136JF_S)
-#define CONFIG_CM_TCRAM /* CM has TCRAM */
-#endif
-
-#ifdef CONFIG_CM_SPD_DETECT
#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
-#endif
#endif /* __ARMCOREMODULE_H */
*/
struct event_state event_state;
#endif
+ /**
+ * @dmtag_list: List of DM tags
+ */
+ struct list_head dmtag_list;
};
#ifndef DO_DEPS_ONLY
static_assert(sizeof(struct global_data) == GD_SIZE);
int gpio_request_by_name(struct udevice *dev, const char *list_name,
int index, struct gpio_desc *desc, int flags);
+/* gpio_request_by_line_name - Locate and request a GPIO by line name
+ *
+ * Request a GPIO using the offset of the provided line name in the
+ * gpio-line-names property found in the OF node of the GPIO udevice.
+ *
+ * This allows boards to implement common behaviours using GPIOs while not
+ * requiring specific GPIO offsets be used.
+ *
+ * @dev: An instance of a GPIO controller udevice
+ * @line_name: The name of the GPIO (e.g. "bmc-secure-boot")
+ * @desc: A GPIO descriptor that is populated with the requested GPIO
+ * upon return
+ * @flags: The GPIO settings apply to the request
+ * @return 0 if the named line was found and requested successfully, or a
+ * negative error code if the GPIO cannot be found or the request failed.
+ */
+int gpio_request_by_line_name(struct udevice *dev, const char *line_name,
+ struct gpio_desc *desc, int flags);
+
/**
* gpio_request_list_by_name() - Request a list of GPIOs
*
*/
int blk_next_device_err(enum blk_flag_t flags, struct udevice **devp);
+/**
+ * blk_find_first() - Return the first matching block device
+ * @flags: Indicates type of device to return
+ * @devp: Returns pointer to device, or NULL on error
+ *
+ * The device is not prepared for use - this is an internal function.
+ * The function uclass_get_device_tail() can be used to probe the device.
+ *
+ * Note that some devices are considered removable until they have been probed
+ *
+ * @return 0 if found, -ENODEV if not found
+ */
+int blk_find_first(enum blk_flag_t flags, struct udevice **devp);
+
+/**
+ * blk_find_next() - Return the next matching block device
+ * @flags: Indicates type of device to return
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the same uclass, or NULL if none
+ *
+ * The device is not prepared for use - this is an internal function.
+ * The function uclass_get_device_tail() can be used to probe the device.
+ *
+ * Note that some devices are considered removable until they have been probed
+ *
+ * @return 0 if found, -ENODEV if not found
+ */
+int blk_find_next(enum blk_flag_t flags, struct udevice **devp);
+
+/**
+ * blk_foreach() - iterate through block devices
+ *
+ * This creates a for() loop which works through the available block devices in
+ * order from start to end.
+ *
+ * If for some reason the uclass cannot be found, this does nothing.
+ *
+ * @_flags: Indicates type of device to return
+ * @_pos: struct udevice * to hold the current device. Set to NULL when there
+ * are no more devices.
+ */
+#define blk_foreach(_flags, _pos) \
+ for (int _ret = blk_find_first(_flags, &_pos); !_ret && _pos; \
+ _ret = blk_find_next(_flags, &_pos))
+
/**
* blk_foreach_probe() - Helper function to iteration through block devices
*
CBFS_TYPE_CBFSHEADER = 0x02,
CBFS_TYPE_STAGE = 0x10,
CBFS_TYPE_PAYLOAD = 0x20,
+ CBFS_TYPE_SELF = CBFS_TYPE_PAYLOAD,
+
CBFS_TYPE_FIT = 0x21,
CBFS_TYPE_OPTIONROM = 0x30,
CBFS_TYPE_BOOTSPLASH = 0x40,
u8 hash_data[];
} __packed;
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard" component types */
+
+/**
+ * struct cbfs_stage - sub-header for stage components
+ *
+ * Stages are loaded by coreboot during the normal boot process
+ */
+struct cbfs_stage {
+ u32 compression; /** Compression type */
+ u64 entry; /** entry point */
+ u64 load; /** Where to load in memory */
+ u32 len; /** length of data to load */
+ u32 memlen; /** total length of object in memory */
+} __packed;
+
+/**
+ * struct cbfs_payload_segment - sub-header for payload components
+ *
+ * Payloads are loaded by coreboot at the end of the boot process
+ */
+struct cbfs_payload_segment {
+ u32 type;
+ u32 compression;
+ u32 offset;
+ u64 load_addr;
+ u32 len;
+ u32 mem_len;
+} __packed;
+
+struct cbfs_payload {
+ struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE 0x45444F43
+#define PAYLOAD_SEGMENT_DATA 0x41544144
+#define PAYLOAD_SEGMENT_BSS 0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY 0x52544E45
+
struct cbfs_cachenode {
struct cbfs_cachenode *next;
void *data;
#define CONFIG_HOSTNAME "mpc837x_rdb"
#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
- "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
+ "ramdiskfile=rootfs.ext2.gz.uboot\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
/* DDR3 Controller Settings */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define QIXIS_BASE 0xffdf0000
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x0f
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
/*
* IFC Definitions
*/
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_CONS_SCIF2
-#define CONFIG_SH_SCIF_CLK_FREQ 65000000
-#endif
#endif /* __ALT_H */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */
-#define CONFIG_POWER_TPS65217
#define CONFIG_POWER_TPS65910
/* SPL */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-/* PMIC support */
-#define CONFIG_POWER_TPS65217
-
/* Bootcount using the RTC block */
#define CONFIG_SYS_BOOTCOUNT_LE
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-/* PMIC support */
-#define CONFIG_POWER_TPS65217
-
#endif /* ! __CONFIG_AM335X_SHC_H */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */
-#define CONFIG_POWER_TPS65217
#define CONFIG_POWER_TPS65910
/* SPL */
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define BOARD_EXTRA_ENV_SETTINGS \
UBOOT_UPDATE
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
-#define CONFIG_CONS_SCIF1
#define SCIF0_BASE 0xe6c40000
#define SCIF1_BASE 0xe6c50000
#define SCIF2_BASE 0xe6c60000
#define CONFIG_SH_ETHER_SH7734_MII (0x01)
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-/* Board Clock */
-#define CONFIG_SH_SCIF_CLK_FREQ get_board_sys_clk()
-
#endif /* __ARMADILLO_800EVA_H */
#define CONFIG_TEGRA_SLINK_CTRLS 6
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_SYS_FSL_QSPI_LE
#endif
-/* We boot from the gfxRAM area of the OCRAM. */
-#define CONFIG_BOARD_SIZE_LIMIT 520192
-
/* boot command, including the target-defined one if any */
/* Extra env settings (including the target-defined ones if any) */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_POWER_TPS65217
-
/*
* When we have NAND flash we expect to be making use of mtdparts,
* both for ease of use in U-Boot and for passing information on to
/* Timer information */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
-#define CONFIG_POWER_TPS65217
#include <asm/arch/omap.h>
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-/* PMIC support */
-#define CONFIG_POWER_TPS65217
-
/* SPL */
/* Bootcount using the RTC block */
#define CONFIG_SYS_BOOTCOUNT_BE
"${board}/flash_blk.img && source ${loadaddr}\0" \
"splashpos=m,m\0" \
"splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \
- "vidargs=video=mxsfb:640x480M-16@60"
-
+ "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0"
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
/*
* High Level Board Configuration Options
*/
-/* Avoid overwriting factory configuration block */
-#define CONFIG_BOARD_SIZE_LIMIT 0x40000
/*
* Environment settings
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define BOARD_EXTRA_ENV_SETTINGS \
UBOOT_UPDATE
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_FDTADDR 0x84000000
-/* We boot from the gfxRAM area of the OCRAM. */
-#define CONFIG_BOARD_SIZE_LIMIT 520192
-
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82000000\0" \
"ubi.fm_autoconvert=1\0" \
"ubiboot=run setup; " \
"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \
- "${setupargs} ${vidargs}; echo Booting from NAND...; " \
+ "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \
"ubi part ubi && " \
"ubi read ${kernel_addr_r} kernel && " \
"ubi read ${fdt_addr_r} dtb && " \
#ifndef _CONFIG_CONTROLCENTERDC_H
#define _CONFIG_CONTROLCENTERDC_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_CUSTOMER_BOARD_SUPPORT
-
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
-/* LED */
-#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
-#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
-
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#include <linux/sizes.h>
#include <asm/arch/cpu.h>
-/*
- * SoC and board defines
- */
-#define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */
-
/*
* RAM
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_BOOTM_LEN SZ_32M
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define EXYNOS_FDTFILE_SETTING
#endif
+/* Cannot use bootdelay > 0, because timer is not working */
#define EXTRA_ENV_SETTINGS \
+ "bootdelay=0\0" \
+ "bootcmd=source $prevbl_initrd_start_addr:bootscript\0" \
EXYNOS_DEVICE_SETTINGS \
EXYNOS_FDTFILE_SETTING \
MEM_LAYOUT_ENV_SETTINGS
"stderr=serial\0"
/* 10/100M Ethernet support */
-#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_ALTDESCRIPTOR
/* Environment configuration */
/* Environment settings */
-/*
- * Environment is right behind U-Boot in flash. Make sure U-Boot
- * doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
-
#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_CONS_SCIF0
-#define CONFIG_SH_SCIF_CLK_FREQ 65000000
-#endif
#endif /* __GOSE_H */
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
-/*
- * Environment is right behind U-Boot in flash. Make sure U-Boot
- * doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
/*
* Default environment variables
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE 0x30BE0000
-
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021-2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __IMX8MM_MX8MENLO_H
+#define __IMX8MM_MX8MENLO_H
+
+#include <configs/verdin-imx8mm.h>
+
+/* Custom initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "devtype=mmc\0" \
+ "devnum=1\0" \
+ "distro_bootpart=1\0" \
+ "altbootcmd=" \
+ "mmc partconf 0 mmcpart ; " \
+ "if test ${mmcpart} -eq 1 ; then " \
+ "mmc partconf 0 1 2 0 ; " \
+ "else " \
+ "mmc partconf 0 1 1 0 ; " \
+ "fi ; " \
+ "boot\0" \
+ "boot_file=fitImage\0" \
+ "console=ttymxc1\0" \
+ "fdt_addr=0x43000000\0" \
+ "initrd_addr=0x43800000\0" \
+ "kernel_image=fitImage\0"
+
+#undef CONFIG_MXC_UART_BASE
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+
+#endif /* __IMX8MM_MX8MENLO_H */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
-/* FEC*/
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE 0x30BE0000
-
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __IMX8MM_DATA_MODUL_EDM_SBC_H
+#define __IMX8MM_DATA_MODUL_EDM_SBC_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN SZ_128M
+
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_1M
+
+#define CONFIG_SPL_STACK 0x920000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_BSS_START_ADDR 0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 kiB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M /* 16 MiB */
+
+#define CONFIG_MALLOC_F_ADDR 0x930000
+
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
+
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* PHY needs a longer autonegotiation timeout after reset */
+#define PHY_ANEG_TIMEOUT 20000
+#define FEC_QUIRK_ENET_MAC
+
+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
+ "bootlimit=3\0" \
+ "devtype=mmc\0" \
+ "devpart=1\0" \
+ /* Give slow devices beyond USB HUB chance to come up. */ \
+ "usb_pgood_delay=2000\0" \
+ "dfu_alt_info=" \
+ /* RAM block at DRAM offset 256..768 MiB */ \
+ "ram ram0=ram ram 0x50000000 0x20000000&" \
+ /* 16 MiB SPI NOR */ \
+ "mtd nor0=sf raw 0x0 0x1000000\0" \
+ "dmo_preboot=" \
+ "sf probe ; " /* Scan for SPI NOR, needed by DFU */ \
+ "run dmo_usb_start_hub ; " \
+ /* Attempt to start USB and Network console */ \
+ "run dmo_usb_cdc_acm_start ; " \
+ "run dmo_netconsole_start\0" \
+ "dmo_update_env=" \
+ "setenv dmo_update_env true ; saveenv ; saveenv\0" \
+ "dmo_usb_cdc_acm_start=" \
+ "if test \"${dmo_usb_cdc_acm_enabled}\" = \"true\" ; then "\
+ /* Ungate IMX8MM_CLK_USB1_CTRL_ROOT */ \
+ "mw 0x303844d0 3 ; " \
+ /* Read USBNC_n_PHY_STATUS BIT(4) VBUS_VLD */ \
+ "setexpr.l usbnc_n_phy_status *0x32e4023c \\\\& 0x8 ; " \
+ /* If USB OTG has valid VBUS, enable CDC ACM */ \
+ "if test \"${usbnc_n_phy_status}\" -eq 8 ; then "\
+ "usb start && " \
+ "setenv stderr ${stderr},usbacm && " \
+ "setenv stdout ${stdout},usbacm && " \
+ "setenv stdin ${stdin},usbacm ; " \
+ "fi ; " \
+ "fi\0" \
+ "dmo_usb_start_hub=" \
+ "i2c dev 1 ; " \
+ /* Reset the USB USB */ \
+ "gpio clear GPIO5_2 ; sleep 0.01 ; " /* t1 > 1us */ \
+ "gpio set GPIO5_2 ; sleep 0.01 ; " /* t5 > 3us */ \
+ /* Write chunks of descriptor into the USB HUB */ \
+ "mw.l 0x7e1000 0x14042417 ; mw.l 0x7e1004 0x9b0bb325 ; "\
+ "mw.l 0x7e1008 0x00000220 ; mw.l 0x7e100c 0x01320100 ; "\
+ "mw.l 0x7e1010 0x00003232 ; mw.l 0x7e1014 0x4d000909 ; "\
+ "i2c write 0x7e1000 0x2c 0x00 0x18 -s ; " \
+ "mw.l 0x7e1000 0x6300690f ; mw.l 0x7e1004 0x6f007200 ; "\
+ "mw.l 0x7e1008 0x68006300 ; mw.l 0x7e100c 0x70006900 ; "\
+ "i2c write 0x7e1000 0x2c 0x18 0x10 -s ; " \
+ "mw.l 0x7e1000 0x53005511 ; mw.l 0x7e1004 0x32004200 ; "\
+ "mw.l 0x7e1008 0x31003500 ; mw.l 0x7e100c 0x42003400 ; "\
+ "mw.l 0x7e1010 0x00006900 ; " \
+ "i2c write 0x7e1000 0x2c 0x54 0x12 -s ; " \
+ "mw.l 0x7e1000 0x00000101 ; " \
+ "i2c write 0x7e1000 0x2c 0xff 0x2 -s\0" \
+ "dmo_netconsole_start=" \
+ "if test \"${dmo_netconsole_enabled}\" = \"true\" ; then "\
+ "setenv autoload false && " \
+ "dhcp && " \
+ "setenv autoload && " \
+ "setenv ncip ${serverip} && " \
+ "setenv stderr ${stderr},nc && " \
+ "setenv stdout ${stdout},nc && " \
+ "setenv stdin ${stdin},nc ; " \
+ "fi"
+
+#endif
+
+#endif
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE 0x30BE0000
-
#endif
"setexpr blkcnt $blkcnt / 0x200 && " \
"mmc dev $dev && " \
"mmc write $loadaddr 0x42 $blkcnt\0" \
+ "loadfdt=" \
+ "if $fsload $fdt_addr_r $dir/$fdt_file1; " \
+ "then echo loaded $fdt_file1; " \
+ "elif $fsload $fdt_addr_r $dir/$fdt_file2; " \
+ "then echo loaded $fdt_file2; " \
+ "elif $fsload $fdt_addr_r $dir/$fdt_file3; " \
+ "then echo loaded $fdt_file3; " \
+ "elif $fsload $fdt_addr_r $dir/$fdt_file4; " \
+ "then echo loaded $fdt_file4; " \
+ "elif $fsload $fdt_addr_r $dir/$fdt_file5; " \
+ "then echo loaded $fdt_file5; " \
+ "fi\0" \
"boot_net=" \
- "tftpboot $kernel_addr_r $image && " \
- "booti $kernel_addr_r - $fdtcontroladdr\0" \
+ "setenv fsload tftpboot; " \
+ "run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \
+ "booti $kernel_addr_r - $fdt_addr_r\0" \
"update_rootfs=" \
"tftpboot $loadaddr $image && " \
"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
-#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
+#define PHYS_SDRAM_SIZE SZ_4G
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
-/* ENET Config */
-#if defined(CONFIG_FEC_MXC)
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE 0x30BE0000
-#endif /* CONFIG_FEC_MXC */
-
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+#ifndef __IMX8MN_BSH_SMM_S2_H
+#define __IMX8MN_BSH_SMM_S2_H
+
+#include <configs/imx8mn_bsh_smm_s2_common.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(NAND, nand, 0) \
+
+#include <config_distro_bootcmd.h>
+
+#define NANDARGS \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:root rw ubi.mtd=nandrootfs\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${fdt_addr_r} nanddtb; " \
+ "nand read ${loadaddr} nandkernel; " \
+ "booti ${loadaddr} - ${fdt_addr_r}\0"
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ MEM_LAYOUT_ENV_SETTINGS \
+ NANDARGS \
+ BOOTENV
+
+#define PHYS_SDRAM_SIZE SZ_256M
+
+/* NAND */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define CONFIG_SYS_NAND_BASE 0x20000000
+
+#endif /* __IMX8MN_BSH_SMM_S2_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+#ifndef __IMX8MN_BSH_SMM_S2_COMMON_H
+#define __IMX8MN_BSH_SMM_S2_COMMON_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+
+#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#define CONFIG_SPL_STACK 0x980000
+#define CONFIG_SPL_BSS_START_ADDR 0x950000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
+
+
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramdisk_addr_r=0x43800000\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "bootcmd_mfg=echo Running fastboot mode; fastboot usb 0\0" \
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+
+#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE SZ_2K
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* I2C */
+
+#endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+#ifndef __IMX8MN_BSH_SMM_S2PRO_H
+#define __IMX8MN_BSH_SMM_S2PRO_H
+
+#include <configs/imx8mn_bsh_smm_s2_common.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+
+#include <config_distro_bootcmd.h>
+
+#define EMMCARGS \
+ "fastboot_partition_alias_all=" \
+ __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \
+ "fastboot_partition_alias_bootloader=" \
+ __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \
+ "emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \
+ "emmc_ack=1\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ MEM_LAYOUT_ENV_SETTINGS \
+ EMMCARGS \
+ BOOTENV
+
+#define PHYS_SDRAM_SIZE SZ_512M
+
+/* USDHC */
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#endif /* __IMX8MN_BSH_SMM_S2PRO_H */
"setexpr blkcnt $blkcnt / 0x200 && " \
"mmc dev $dev && " \
"mmc write $loadaddr 0x40 $blkcnt\0" \
+ "loadfdt=" \
+ "if $fsload $fdt_addr_r $dir/$fdt_file1; " \
+ "then echo loaded $fdt_file1; " \
+ "elif $fsload $fdt_addr_r $dir/$fdt_file2; " \
+ "then echo loaded $fdt_file2; " \
+ "elif $fsload $fdt_addr_r $dir/$fdt_file3; " \
+ "then echo loaded $fdt_file3; " \
+ "elif $fsload $fdt_addr_r $dir/$fdt_file4; " \
+ "then echo loaded $fdt_file4; " \
+ "elif $fsload $fdt_addr_r $dir/$fdt_file5; " \
+ "then echo loaded $fdt_file5; " \
+ "fi\0" \
"boot_net=" \
- "tftpboot $kernel_addr_r $image && " \
- "booti $kernel_addr_r - $fdtcontroladdr\0" \
+ "setenv fsload tftpboot; " \
+ "run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \
+ "booti $kernel_addr_r - $fdt_addr_r\0" \
"update_rootfs=" \
"tftpboot $loadaddr $image && " \
"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
-#define PHYS_SDRAM_SIZE SZ_1G
+#define PHYS_SDRAM_SIZE SZ_4G
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-
-#define IMX_FEC_BASE 0x30BE0000
#endif
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-
-#define IMX_FEC_BASE 0x30BE0000
#endif
#define CONFIG_MFG_ENV_SETTINGS \
#endif
+#define COUNTER_FREQUENCY 1000000 /* 1MHz */
+
/* ENET Config */
#if defined(CONFIG_FEC_MXC)
#define PHY_ANEG_TIMEOUT 20000
#define CONFIG_FEC_MXC_PHYADDR 1
-
-#define IMX_FEC_BASE 0x29950000
#endif
#ifdef CONFIG_DISTRO_DEFAULTS
#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
-/*
- * There are various dependencies on the core module (CM) fitted
- * Users should refer to their CM user guide
- */
-#include "armcoremodule.h"
-
-/*
- * Initialize and remap the core module, use SPD to detect memory size
- * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
- * the core module has a CM_INIT register
- * then the U-Boot initialisation code will
- * e.g. ARM Boot Monitor or pre-loader is repeated once
- * (to re-initialise any existing CM_INIT settings to safe values).
- *
- * This is usually not the desired behaviour since the platform
- * will either reboot into the ARM monitor (or pre-loader)
- * or continuously cycle thru it without U-Boot running,
- * depending upon the setting of Integrator/CP switch S2-4.
- *
- * However it may be needed if Integrator/CP switch S2-1
- * is set OFF to boot direct into U-Boot.
- * In that case comment out the line below.
- */
-#define CONFIG_CM_INIT
-#define CONFIG_CM_REMAP
-#define CONFIG_CM_SPD_DETECT
-
/*
* The ARM boot monitor initializes the board.
* However, the default U-Boot code also performs the initialization.
* PCI definitions
*/
-/*-----------------------------------------------------------------------
- * There are various dependencies on the core module (CM) fitted
- * Users should refer to their CM user guide
- * - when porting adjust u-boot/Makefile accordingly
- * to define the necessary CONFIG_ s for the CM involved
- * see e.g. integratorcp_CM926EJ-S_config
- */
-#include "armcoremodule.h"
-
#endif /* __CONFIG_H */
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
-#define CONFIG_CQSPI_REF_CLK 133333333
/* HyperFlash related configuration */
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
-#define CONFIG_CQSPI_REF_CLK 133333333
/* U-Boot general configuration */
#define EXTRA_ENV_J721S2_BOARD_SETTINGS \
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CQSPI_REF_CLK 384000000
-#endif
-
#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS
#include <configs/ti_armv7_keystone2.h>
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_CONS_SCIF0
-#define CONFIG_SH_SCIF_CLK_FREQ 65000000
-#endif
#endif /* __KOELSCH_H */
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE 0x30BE0000
#define PHY_ANEG_TIMEOUT 20000
#endif
#define ENV_MEM_LAYOUT_SETTINGS \
- "kernel_addr_r=0x40880000\0" \
- "fdt_addr_r=0x43000000\0" \
- "scriptaddr=0x43500000\0" \
- "initrd_addr=0x43800000\0" \
- "pxefile_addr_r=0x43500000\0" \
- "bootm_size=0x10000000\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "fdt_addr_r=0x48000000\0" \
+ "fdtoverlay_addr_r=0x49000000\0" \
+ "ramdisk_addr_r=0x48080000\0" \
+ "scriptaddr=0x40000000\0" \
+ "pxefile_addr_r=0x40100000\0"
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
-#define CONFIG_CONS_SCIF4
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
/* Clock */
#define CONFIG_GLOBAL_TIMER
#define CONFIG_SYS_CPU_CLK (1196000000)
-#define CONFIG_SH_SCIF_CLK_FREQ get_board_sys_clk()
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
#endif /* __KZM9G_H */
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_CONS_SCIF0
-#define CONFIG_SH_SCIF_CLK_FREQ 65000000
-#endif
#endif /* __LAGER_H */
/* Environment settings */
-/*
- * Environment is right behind U-Boot in flash. Make sure U-Boot
- * doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
-
#endif /* __CONFIG_LINKIT_SMART_7688_H */
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/* SATA */
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifndef CONFIG_SPL_BUILD
#define BOARD_REV_C 0x00080000
#define BOARD_REV_MASK 0x001A0000
/* DDR */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define SYS_SDRAM_SIZE_512 0x20000000
#define SYS_SDRAM_SIZE_1024 0x40000000
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/*
* QIXIS Definitions
*/
-#define CONFIG_FSL_QIXIS
#ifdef CONFIG_FSL_QIXIS
-#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_BRDCFG_REG 0x04
#define QIXIS_LBMAP_SWITCH 6
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/*
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_QIXIS_I2C_ACCESS
-#endif
-
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/*
* QIXIS Definitions
*/
-#define CONFIG_FSL_QIXIS
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
-/* DDR */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-
-#define CONFIG_QIXIS_I2C_ACCESS
-
/*
* QIXIS Definitions
*/
-#define CONFIG_FSL_QIXIS
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
/* Store environment at top of flash */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-#define CONFIG_QIXIS_I2C_ACCESS
-
/*
* QIXIS Definitions
*/
-#define CONFIG_FSL_QIXIS
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define SPD_EEPROM_ADDRESS 0x51
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_QIXIS_I2C_ACCESS
#endif
/*
* QIXIS Definitions
*/
-#define CONFIG_FSL_QIXIS
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
#define CONFIG_SYS_UBOOT_BASE 0x40100000
/*
#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define SPD_EEPROM_ADDRESS 0x51
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_QIXIS_I2C_ACCESS
#endif
/*
* QIXIS Definitions
*/
-#define CONFIG_FSL_QIXIS
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define SPD_EEPROM_ADDRESS 0x51
#include "ls1088a_common.h"
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_QIXIS_I2C_ACCESS
#define SYS_NO_FLASH
-#else
-#define CONFIG_QIXIS_I2C_ACCESS
#endif
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_FSL_QIXIS
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_QMAP_MASK 0xe0
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_QIXIS_I2C_ACCESS
-#endif
#define SYS_NO_FLASH
#endif
#endif
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#ifndef SPL_NO_QIXIS
-#define CONFIG_FSL_QIXIS
-#endif
-
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_BRDCFG4_OFFSET 0x54
#define QIXIS_LBMAP_SWITCH 2
#define CPU_RELEASE_ADDR secondary_boot_addr
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
-/*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
-#define CONFIG_SYS_DP_DDR_BASE_PHY 0
-#define CONFIG_DP_DDR_CTRL 2
-#define CONFIG_DP_DDR_NUM_CTRLS 1
-#endif
/* Generic Timer Definitions */
/*
#include "ls2080a_common.h"
#ifdef CONFIG_FSL_QSPI
-#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
#endif
#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
#include "ls2080a_common.h"
-#ifdef CONFIG_FSL_QSPI
-#ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_QIXIS_I2C_ACCESS
-#endif
-#endif
-
#define I2C_MUX_CH_VOL_MONITOR 0xa
#define I2C_VOL_MONITOR_ADDR 0x38
#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define QIXIS_QMAP_MASK 0x07
#define QIXIS_QMAP_SHIFT 5
#define QIXIS_LBMAP_DFLTBANK 0x00
#define SPD_EEPROM_ADDRESS6 0x56
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
/* Miscellaneous configurable options */
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* Qixis */
-#define CONFIG_FSL_QIXIS
-#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
/* PCI */
#ifdef CONFIG_CMD_NET
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_DISCOVER_PHY
#endif
#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
# define CONFIG_SYS_MAX_FLASH_SECT 2048
#endif
-#define CONFIG_ICACHE
-#define CONFIG_DCACHE
-
#ifndef XILINX_DCACHE_BYTE_SIZE
#define XILINX_DCACHE_BYTE_SIZE 32768
#endif
* environment organization
*/
-/*
- * Environment starts at CONFIG_ENV_OFFSET=0xC0000 = 768k = 768 * 1024 = 786432
- *
- * Detect overlap between U-Boot image and environment area in build-time
- *
- * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
- * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
- *
- * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
- * write the direct value here
- */
-#define CONFIG_BOARD_SIZE_LIMIT 785408
-
#endif
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* Environment starts at 768k = 768 * 1024 = 786432 */
-/*
- * Detect overlap between U-Boot image and environment area in build-time
- *
- * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
- * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
- *
- * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
- * write the direct value here
- */
-#define CONFIG_BOARD_SIZE_LIMIT 785408
-
#ifdef CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
#define CONFIG_SYS_BOOTM_LEN 0x1000000
-/*
- * Detect overlap between U-Boot image and environment area in build-time
- *
- * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-dtb.imx offset
- * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
- *
- * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
- * write the direct value here
- */
-#define CONFIG_BOARD_SIZE_LIMIT 785408
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
/* Using ULP WDOG for reset */
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
-/*
- * Environment is right behind U-Boot in flash. Make sure U-Boot
- * doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
/*
* Default environment variables
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
/* Default settings for DDR3 */
#ifndef CONFIG_TARGET_P2020RDB
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* _P2371_0000_H */
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
/* Crystal is 38.4MHz. clk_m runs at half that rate */
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* _P2571_H */
"fi\0"
/* General networking support */
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
/* Crystal is 38.4MHz. clk_m runs at half that rate */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* We boot from the gfxRAM area of the OCRAM. */
-#define CONFIG_BOARD_SIZE_LIMIT 520192
-
/* if no target-specific extra environment settings were defined by the
target, define an empty one */
#ifndef PCM052_EXTRA_ENV_SETTINGS
/* Environment organization */
-/* Environment starts at 768k = 768 * 1024 = 786432 */
-/*
- * Detect overlap between U-Boot image and environment area in build-time
- *
- * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset
- * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776
- *
- * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
- * write the direct value here
- */
-#define CONFIG_BOARD_SIZE_LIMIT 715776
-
/* Ethernet Configuration */
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 1
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
-/* Environment starts at 768k = 768 * 1024 = 786432 */
-/*
- * Detect overlap between U-Boot image and environment area in build-time
- *
- * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset
- * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776
- *
- * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
- * write the direct value here
- */
-#define CONFIG_BOARD_SIZE_LIMIT 715776
#ifdef CONFIG_DM_VIDEO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
/* FLASH and environment organization */
/* Environment starts at 768k = 768 * 1024 = 786432 */
-/*
- * Detect overlap between U-Boot image and environment area in build-time
- *
- * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset
- * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776
- *
- * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
- * write the direct value here
- */
-#define CONFIG_BOARD_SIZE_LIMIT 715776
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 1
#define FEC_QUIRK_ENET_MAC
-
-#define IMX_FEC_BASE 0x30BE0000
#endif
/* Initial environment variables */
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_CONS_SCIF0
-#define CONFIG_SH_SCIF_CLK_FREQ 65000000
-#endif
#endif /* __PORTER_H */
# define BOOT_TARGET_VIRTIO(func)
#endif
+#if CONFIG_IS_ENABLED(CMD_NVME)
+# define BOOT_TARGET_NVME(func) func(NVME, nvme, 0)
+#else
+# define BOOT_TARGET_NVME(func)
+#endif
+
#if CONFIG_IS_ENABLED(CMD_DHCP)
# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
#else
BOOT_TARGET_USB(func) \
BOOT_TARGET_SCSI(func) \
BOOT_TARGET_VIRTIO(func) \
+ BOOT_TARGET_NVME(func) \
BOOT_TARGET_DHCP(func)
#include <config_distro_bootcmd.h>
#define __LITTLE_ENDIAN__ 1
/* SCIF */
-#define CONFIG_CONS_SCIF1 1
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x8C000000
#define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
-/* The HF/QSPI layout permits up to 1 MiB large bootloader blob */
-#define CONFIG_BOARD_SIZE_LIMIT 1048576
-
/* ENV setting */
#define CONFIG_EXTRA_ENV_SETTINGS \
#endif
#define CONFIG_SPL_STACK 0xe6304000
#define CONFIG_SPL_MAX_SIZE 0x7000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_CONS_SCIF2
-#define CONFIG_SH_SCIF_CLK_FREQ 65000000
-#endif
#endif /* __RCAR_GEN3_COMMON_H */
"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
-#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \
- " ${console} ${meminfo}"
-
-#define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}"
-
-#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \
- " onenand write 0x32008000 0x0 0x100000\0"
+#define COMMON_BOOT "${console} ${meminfo} ${mtdparts}"
#define CONFIG_MISC_COMMON
#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_UPDATEB \
+ "updateb=" \
+ "onenand erase 0x0 0x100000;" \
+ "onenand write 0x32008000 0x0 0x100000\0" \
"updatek=" \
"onenand erase 0xc00000 0x600000;" \
"onenand write 0x31008000 0xc00000 0x600000\0" \
"flashboot=" \
"set bootargs root=/dev/mtdblock${bootblock} " \
"rootfstype=${rootfstype} ${opts} " \
- "${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \
+ "${lcdinfo} " COMMON_BOOT "; run bootk\0" \
"ubifsboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
"${opts} ${lcdinfo} " \
- CONFIG_COMMON_BOOT "; run bootk\0" \
+ COMMON_BOOT "; run bootk\0" \
"tftpboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
- "${opts} ${lcdinfo} " CONFIG_COMMON_BOOT \
+ "${opts} ${lcdinfo} " COMMON_BOOT \
"; tftp 0x30007FC0 uImage; bootm 0x30007FC0\0" \
"ramboot=" \
- "set bootargs " CONFIG_RAMDISK_BOOT \
+ "set bootargs root=/dev/ram0 rw rootfstype=ext4" \
+ " ${console} ${meminfo} " \
"initrd=0x33000000,8M ramdisk=8192\0" \
"mmcboot=" \
"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
"rootfstype=${rootfstype} ${opts} ${lcdinfo} " \
- CONFIG_COMMON_BOOT "; run bootk\0" \
+ COMMON_BOOT "; run bootk\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
"verify=n\0" \
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 19000000
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootm_size=0x4000000\0" \
+ "bootm_low=0x80000000\0" \
+ "stdout=vidconsole\0" \
+ "stderr=vidconsole\0" \
+ "preboot=source $prevbl_initrd_start_addr:prebootscript\0" \
+ "bootcmd=source $prevbl_initrd_start_addr:bootscript\0"
+
/* Size of malloc() pool */
#define CONFIG_SYS_BOOTM_LEN SZ_64M
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
-/*
- * Environment is right behind U-Boot in flash. Make sure U-Boot
- * doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
/*
* Default environment variables
#include <asm/arch/omap.h>
-#define CONFIG_DMA_COHERENT
-#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
-
/* commands to include */
#ifndef CONFIG_SPL_BUILD
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_CONS_SCIF2
-#define CONFIG_SH_SCIF_CLK_FREQ 65000000
-#endif
#endif /* __SILK_H */
/* setting board specific options */
#define CONFIG_SYS_AUTOLOAD "yes"
-/* The LED PINs */
-#define CONFIG_RED_LED AT91_PIN_PA9
-#define CONFIG_GREEN_LED AT91_PIN_PA6
-
/*
* SDRAM: 1 bank, 64 MB, base address 0x20000000
* Already initialized before u-boot gets started.
/* PWM */
#define CONFIG_PWM 1
-#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \
- " console=ttySAC0,115200n8" \
- " mem=128M"
-
-#define CONFIG_COMMON_BOOT "console=ttySAC0,115200n8" \
+#define COMMON_BOOT "console=ttySAC0,115200n8" \
" mem=128M " \
" " CONFIG_MTDPARTS_DEFAULT
-#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
- " onenand write 0x32008000 0x0 0x40000\0"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_UPDATEB \
+ "updateb=" \
+ "onenand erase 0x0 0x40000;" \
+ "onenand write 0x32008000 0x0 0x40000\0" \
"updatek=" \
"onenand erase 0x60000 0x300000;" \
"onenand write 0x31008000 0x60000 0x300000\0" \
"flashboot=" \
"set bootargs root=/dev/mtdblock${bootblock} " \
"rootfstype=${rootfstype} " \
- "ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
+ "ubi.mtd=${ubiblock} ${opts} " COMMON_BOOT ";" \
"run bootk\0" \
"ubifsboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
- " ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+ " ubi.mtd=${ubiblock} ${opts} " COMMON_BOOT "; " \
"run bootk\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"android=" \
"set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
- "rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
+ "rootfstype=ubifs init=/init.sh " COMMON_BOOT "; " \
"run bootk\0" \
"nfsboot=" \
"set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
"nfsroot=${nfsroot},nolock " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
+ "${netmask}:nowplus:usb0:off " COMMON_BOOT "; " \
"run bootk\0" \
"ramboot=" \
- "set bootargs " CONFIG_RAMDISK_BOOT \
+ "set bootargs root=/dev/ram0 rw rootfstype=ext2" \
+ " console=ttySAC0,115200n8 mem=128M" \
" initrd=0x33000000,8M ramdisk=8192\0" \
"rootfstype=cramfs\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
-/*
- * QSPI support
- */
-/* QSPI reference clock */
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
-#endif
-
/*
* USB
*/
#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
#endif /* CONFIG_SPL_BUILD */
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
-#endif
-
#endif /* CONFIG_CADENCE_QSPI */
/*
"256k(softing1)," \
"256k(softing2)," \
"14720k(rcvrfs)," /* Recovery */ \
- "64m(rootfs)," /* Root */ \
+ "192m(rootfs)," /* Root */ \
"-(userfs)\0" /* User */ \
"mtdparts_1_128m=ff705000.spi.1:" /* 16MiB+128MiB SF config */ \
"64m(rootfs)," \
"fi\0" \
"socfpga_legacy_reset_compat=1\0"
-/* Support changing the prompt string */
-#define CONFIG_CMDLINE_PS_SUPPORT
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
#define CONFIG_SYS_MAX_FLASH_SECT 12
-#define CONFIG_RED_LED 110
-#define CONFIG_GREEN_LED 109
-
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_SYS_CBSIZE 1024
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_CONS_SCIFA0
-#define CONFIG_SH_SCIF_CLK_FREQ 52000000
-#endif
#endif /* __STOUT_H */
/* Misc configuration */
-/*
-+ * QSPI support
-+ */
-#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
-#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
-
-#endif
-
#endif /* __CONFIG_H */
/* mmc config */
#define CONFIG_MMC_SUNXI_SLOT 0
-#if defined(CONFIG_ENV_IS_IN_MMC)
-/*
- * This is actually (CONFIG_ENV_OFFSET -
- * (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)), but the value will be used
- * directly in a makefile, without the preprocessor expansion.
- */
-#define CONFIG_BOARD_SIZE_LIMIT 0x7e000
-#endif
-
#define CONFIG_SYS_MMC_MAX_DEVICE 4
/*
#endif /* CONFIG_CMD_USB_MASS_STORAGE */
#endif /* CONFIG_CMD_USB */
-#define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
#define BOARD_EXTRA_ENV_SETTINGS
#endif
-#ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
-#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
-#endif
-
#ifdef CONFIG_ARM64
#define FDT_HIGH "ffffffffffffffff"
#define INITRD_HIGH "ffffffffffffffff"
"fdt_high=" FDT_HIGH "\0" \
"initrd_high=" INITRD_HIGH "\0" \
BOOTENV \
- BOARD_EXTRA_ENV_SETTINGS \
- CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
+ BOARD_EXTRA_ENV_SETTINGS
#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
#define CONFIG_TEGRA_SPI
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2014
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA_COMMON_USB_GADGET_H_
-#define _TEGRA_COMMON_USB_GADGET_H_
-
-#ifndef CONFIG_SPL_BUILD
-/* USB gadget mode support*/
-#ifndef CONFIG_TEGRA20
-#define CONFIG_CI_UDC_HAS_HOSTPC
-#endif
-/* DFU protocol */
-#endif
-
-#endif /* _TEGRA_COMMON_USB_GADGET_H_ */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd"
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
/* ENET */
#define CONFIG_FEC_MXC_PHYADDR 7
#define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE 0x30BE0000
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/* I2C Configs */
#define CONFIG_SYS_SPD_BUS_NUM 0
-/* We boot from the gfxRAM area of the OCRAM. */
-#define CONFIG_BOARD_SIZE_LIMIT 520192
-
/*
* We do have 128MB of memory on the Vybrid Tower board. Leave the last
* 16MB alone to avoid conflicts with Cortex-M4 firmwares running from
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/*
- * Environment starts at CONFIG_ENV_OFFSET= 0xC0000 = 768k = 768*1024 = 786432
- *
- * Detect overlap between U-Boot image and environment area in build-time
- *
- * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
- * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
- *
- * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
- * write the direct value here
- */
-#define CONFIG_BOARD_SIZE_LIMIT 785408
-
/* environment organization */
#define CONFIG_SYS_FSL_USDHC_NUM 1
# define PHY_ANEG_TIMEOUT 20000
#endif
-#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024)
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
# define PHY_ANEG_TIMEOUT 20000
#endif
-#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024)
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
*
* @dev: CROS-EC device
* @chargep: Return battery-charge state as a percentage
+ * Return: 0 if OK, -ve on error
*/
int cros_ec_read_batt_charge(struct udevice *dev, uint *chargep);
#include <dm/ofnode.h>
struct device_node;
+struct driver_info;
struct udevice;
/*
* Look at the compatible property of a device node that represents a eth phy
* device and extract phy vendor id and device id from it.
*
- * @param node node to examine
- * @param vendor vendor id of the eth phy device
- * @param device device id of the eth phy device
- * @return 0 if ok, negative on error
+ * @node: node to examine
+ * @vendor: vendor id of the eth phy device
+ * @device: device id of the eth phy device
+ * Return: 0 if ok, negative on error
*/
int ofnode_read_eth_phy_id(ofnode node, u16 *vendor, u16 *device);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Linaro Limited
+ * Author: AKASHI Takahiro
+ */
+
+#ifndef _DM_TAG_H
+#define _DM_TAG_H
+
+#include <linux/list.h>
+#include <linux/types.h>
+
+struct udevice;
+
+enum dm_tag_t {
+ /* EFI_LOADER */
+ DM_TAG_EFI = 0,
+
+ DM_TAG_COUNT,
+};
+
+/**
+ * dmtag_node
+ *
+ * @sibling: List of dm-tag nodes
+ * @dev: Associated udevice
+ * @tag: Tag type
+ * @ptr: Pointer as a value
+ * @val: Value
+ */
+struct dmtag_node {
+ struct list_head sibling;
+ struct udevice *dev;
+ enum dm_tag_t tag;
+ union {
+ void *ptr;
+ ulong val;
+ };
+};
+
+/**
+ * dev_tag_set_ptr() - set a tag's value as a pointer
+ * @dev: Device to operate
+ * @tag: Tag type
+ * @ptr: Pointer to set
+ *
+ * Set the value, @ptr, as of @tag associated with the device, @dev
+ *
+ * Return: 0 on success, -ve on error
+ */
+int dev_tag_set_ptr(struct udevice *dev, enum dm_tag_t tag, void *ptr);
+
+/**
+ * dev_tag_set_val() set a tag's value as an integer
+ * @dev: Device to operate
+ * @tag: Tag type
+ * @val: Value to set
+ *
+ * Set the value, @val, as of @tag associated with the device, @dev
+ *
+ * Return: on success, -ve on error
+ */
+int dev_tag_set_val(struct udevice *dev, enum dm_tag_t tag, ulong val);
+
+/**
+ * dev_tag_get_ptr() - get a tag's value as a pointer
+ * @dev: Device to operate
+ * @tag: Tag type
+ * @ptrp: Pointer to tag's value (pointer)
+ *
+ * Get a tag's value as a pointer
+ *
+ * Return: on success, -ve on error
+ */
+int dev_tag_get_ptr(struct udevice *dev, enum dm_tag_t tag, void **ptrp);
+
+/**
+ * dev_tag_get_val() - get a tag's value as an integer
+ * @dev: Device to operate
+ * @tag: Tag type
+ * @valp: Pointer to tag's value (ulong)
+ *
+ * Get a tag's value as an integer
+ *
+ * Return: 0 on success, -ve on error
+ */
+int dev_tag_get_val(struct udevice *dev, enum dm_tag_t tag, ulong *valp);
+
+/**
+ * dev_tag_del() - delete a tag
+ * @dev: Device to operate
+ * @tag: Tag type
+ *
+ * Delete a tag of @tag associated with the device, @dev
+ *
+ * Return: 0 on success, -ve on error
+ */
+int dev_tag_del(struct udevice *dev, enum dm_tag_t tag);
+
+/**
+ * dev_tag_del_all() - delete all tags
+ * @dev: Device to operate
+ *
+ * Delete all the tags associated with the device, @dev
+ *
+ * Return: 0 on success, -ve on error
+ */
+int dev_tag_del_all(struct udevice *dev);
+
+#endif /* _DM_TAG_H */
*
* @_name: Name of the uclass. This must be a valid C identifier, used by the
* linker_list
- * @returns struct uclass * for the device
+ * Return: struct uclass * for the device
*/
#define DM_UCLASS_REF(_name) \
ll_entry_ref(struct uclass, _name, uclass)
* uclass_find_device() - Return n-th child of uclass
* @id: Id number of the uclass
* @index: Position of the child in uclass's list
- * #devp: Returns pointer to device, or NULL on error
+ * @devp: Returns pointer to device, or NULL on error
*
* The device is not prepared for use - this is an internal function.
* The function uclass_get_device_tail() can be used to probe the device.
/**
* uclass_find_first_device() - Return the first device in a uclass
* @id: Id number of the uclass
- * #devp: Returns pointer to device, or NULL on error
+ * @devp: Returns pointer to device, or NULL on error
*
* The device is not prepared for use - this is an internal function.
* The function uclass_get_device_tail() can be used to probe the device.
* Connect the device into uclass's list of devices.
*
* @dev: Pointer to the device
- * #return 0 on success, -ve on error
+ * Return: 0 on success, -ve on error
*/
int uclass_bind_device(struct udevice *dev);
* Call any handled needed before uclass_unbind_device() is called
*
* @dev: Pointer to the device
- * #return 0 on success, -ve on error
+ * Return: 0 on success, -ve on error
*/
int uclass_pre_unbind_device(struct udevice *dev);
* Disconnect the device from uclass's list of devices.
*
* @dev: Pointer to the device
- * #return 0 on success, -ve on error
+ * Return: 0 on success, -ve on error
*/
int uclass_unbind_device(struct udevice *dev);
* uclass' child_pre_probe() method.
*
* @dev: Pointer to the device
- * #return 0 on success, -ve on error
+ * Return: 0 on success, -ve on error
*/
int uclass_pre_probe_device(struct udevice *dev);
* uclass.
*
* @dev: Pointer to the device
- * #return 0 on success, -ve on error
+ * Return: 0 on success, -ve on error
*/
int uclass_post_probe_device(struct udevice *dev);
* Perform any pre-processing of a device that is about to be removed.
*
* @dev: Pointer to the device
- * #return 0 on success, -ve on error
+ * Return: 0 on success, -ve on error
*/
#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
int uclass_pre_remove_device(struct udevice *dev);
int uclass_id_count(enum uclass_id id);
/**
- * uclass_id_foreach_dev() - Helper function to iteration through devices
+ * uclass_id_foreach_dev() - iterate through devices of a given uclass ID
*
* This creates a for() loop which works through the available devices in
* a uclass ID in order from start to end.
list_for_each_entry(pos, &uc->dev_head, uclass_node)
/**
- * uclass_foreach_dev() - Helper function to iteration through devices
+ * uclass_foreach_dev() - iterate through devices of a given uclass
*
* This creates a for() loop which works through the available devices in
* a uclass in order from start to end.
*
* @pos: struct udevice * to hold the current device. Set to NULL when there
* are no more devices.
- * @uc: uclass to scan
+ * @uc: uclass to scan (`struct uclass *`)
*/
#define uclass_foreach_dev(pos, uc) \
list_for_each_entry(pos, &uc->dev_head, uclass_node)
/**
- * uclass_foreach_dev_safe() - Helper function to safely iteration through devs
+ * uclass_foreach_dev_safe() - safely iterate through devices of a given uclass
*
* This creates a for() loop which works through the available devices in
* a uclass in order from start to end. Inside the loop, it is safe to remove
* @pos: struct udevice * to hold the current device. Set to NULL when there
* are no more devices.
* @next: struct udevice * to hold the next next
- * @uc: uclass to scan
+ * @uc: uclass to scan (`struct uclass *`)
*/
#define uclass_foreach_dev_safe(pos, next, uc) \
list_for_each_entry_safe(pos, next, &uc->dev_head, uclass_node)
/**
- * uclass_foreach_dev_probe() - Helper function to iteration through devices
- * of given uclass
+ * uclass_foreach_dev_probe() - iterate through devices of a given uclass ID
*
* This creates a for() loop which works through the available devices in
* a uclass in order from start to end. Devices are probed if necessary,
#define IMX8MQ_CLK_A53_CORE 289
-#define IMX8MQ_CLK_END 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291
+#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292
+#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293
+#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294
+#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295
+#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296
+#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297
+#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298
+#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299
+#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300
+#define IMX8MQ_CLK_MON_SEL 301
+#define IMX8MQ_CLK_MON_CLK2_OUT 302
+
+#define IMX8MQ_CLK_END 303
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* This header provides constants for the phy framework
*
* Copyright (C) 2014 STMicroelectronics
* Author: Gabriel Fernandez <gabriel.fernandez@st.com>
- * License terms: GNU General Public License (GPL), version 2
*/
#ifndef _DT_BINDINGS_PHY
#define PHY_TYPE_XPCS 7
#define PHY_TYPE_SGMII 8
#define PHY_TYPE_QSGMII 9
+#define PHY_TYPE_DPHY 10
+#define PHY_TYPE_CPHY 11
#endif /* _DT_BINDINGS_PHY */
#ifndef _DT_BINDINGS_VERSAL_POWER_H
#define _DT_BINDINGS_VERSAL_POWER_H
+#define PM_DEV_RPU0_0 (0x18110005U)
+#define PM_DEV_RPU0_1 (0x18110006U)
+#define PM_DEV_OCM_0 (0x18314007U)
+#define PM_DEV_OCM_1 (0x18314008U)
+#define PM_DEV_OCM_2 (0x18314009U)
+#define PM_DEV_OCM_3 (0x1831400aU)
+#define PM_DEV_TCM_0_A (0x1831800bU)
+#define PM_DEV_TCM_0_B (0x1831800cU)
+#define PM_DEV_TCM_1_A (0x1831800dU)
+#define PM_DEV_TCM_1_B (0x1831800eU)
#define PM_DEV_USB_0 (0x18224018U)
#define PM_DEV_GEM_0 (0x18224019U)
#define PM_DEV_GEM_1 (0x1822401aU)
#define PM_DEV_ADMA_5 (0x1822403aU)
#define PM_DEV_ADMA_6 (0x1822403bU)
#define PM_DEV_ADMA_7 (0x1822403cU)
+#define PM_DEV_AMS_ROOT (0x18224055U)
#define PM_DEV_AI (0x18224072U)
#endif
#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
#define _DT_BINDINGS_ZYNQMP_POWER_H
+#define PD_RPU_0 6
+#define PD_RPU_1 7
+#define PD_OCM_BANK_0 11
+#define PD_OCM_BANK_1 12
+#define PD_OCM_BANK_2 13
+#define PD_OCM_BANK_3 14
+#define PD_TCM_BANK_0 15
+#define PD_TCM_BANK_1 16
+#define PD_TCM_BANK_2 17
+#define PD_TCM_BANK_3 18
#define PD_USB_0 22
#define PD_USB_1 23
#define PD_TTC_0 24
#define PD_CAN_1 48
#define PD_GPU 58
#define PD_PCIE 59
+#define PD_PL 69
#endif
* Return: an enum env_location value on success, or -ve error code.
*/
enum env_location env_get_location(enum env_operation op, int prio);
+
+/**
+ * env_fat_get_intf() - Provide the interface for env in FAT
+ *
+ * It is a weak function allowing board to overidde the default interface for
+ * U-Boot env in FAT: CONFIG_ENV_FAT_INTERFACE
+ *
+ * Return: string of interface, empty if not supported
+ */
+const char *env_fat_get_intf(void);
+
+/**
+ * env_fat_get_dev_part() - Provide the device and partition for env in FAT
+ *
+ * It is a weak function allowing board to overidde the default device and
+ * partition used for U-Boot env in FAT: CONFIG_ENV_FAT_DEVICE_AND_PART
+ *
+ * Return: string of device and partition
+ */
+char *env_fat_get_dev_part(void);
#endif /* DO_DEPS_ONLY */
#endif /* _ENV_INTERNAL_H_ */
* Return: string describing the error. If CONFIG_ERRNO_STR is not
* defined an empty string is returned.
*/
-#ifdef CONFIG_ERRNO_STR
+#if CONFIG_IS_ENABLED(ERRNO_STR)
const char *errno_str(int errno);
#else
static const char error_message[] = "";
* Common internal memory map for some Freescale SoCs
*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __FSL_SEC_H
#define SEC_CHAVID_LS_RNG_SHIFT 16
#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
-#define CONFIG_JRSTARTR_JR0 0x00000001
-
struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
u32 irba_l;
u32 irba_h;
#else
u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
u32 orba_l;
u32 orba_h;
#else
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
uint32_t addr_lo; /* Memory Address - lo */
uint32_t addr_hi; /* Memory Address of start of buffer - hi */
#else
};
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
/* Job Ring Base Address */
#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#ifndef _GSC_H_
+#define _GSC_H_
+
+/*
+ * board_gsc_info - Display additional board info
+ */
+void board_gsc_info(void);
+
+/*
+ * gsc_boot_wd_disable - disable the BOOT watchdog
+ *
+ * Return: 0 on success or negative error on failure
+ */
+int gsc_boot_wd_disable(void);
+
+#endif
IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */
IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/
IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */
+ IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */
IH_TYPE_COUNT, /* Number of image types */
};
struct padding_algo {
const char *name;
int (*verify)(struct image_sign_info *info,
- uint8_t *pad, int pad_len,
+ const uint8_t *pad, int pad_len,
const uint8_t *hash, int hash_len);
};
*/
int setup_bdinfo(void);
+#if defined(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) || \
+defined(CONFIG_SAVE_PREV_BL_FDT_ADDR)
+/**
+ * save_prev_bl_data - Save prev bl data in env vars.
+ *
+ * When u-boot is chain-loaded, save previous bootloader data,
+ * like initramfs address to environment variables.
+ *
+ * Return: 0 if ok; -ENODATA on error
+ */
+int save_prev_bl_data(void);
+#endif
+
/**
* cpu_secondary_init_r() - CPU-specific secondary initialization
*
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments' K3 DDRSS Driver
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#ifndef _K3_DDRSS_
+#define _K3_DDRSS_
+
+struct udevice;
+
+int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd);
+
+#endif
struct udevice;
+enum led_state_t {
+ LEDST_OFF = 0,
+ LEDST_ON = 1,
+ LEDST_TOGGLE,
+#ifdef CONFIG_LED_BLINK
+ LEDST_BLINK,
+#endif
+
+ LEDST_COUNT,
+};
+
/**
* struct led_uc_plat - Platform data the uclass stores about each device
*
* @label: LED label
+ * @default_state: LED default state
*/
struct led_uc_plat {
const char *label;
+ enum led_state_t default_state;
};
/**
int period_ms;
};
-enum led_state_t {
- LEDST_OFF = 0,
- LEDST_ON = 1,
- LEDST_TOGGLE,
-#ifdef CONFIG_LED_BLINK
- LEDST_BLINK,
-#endif
-
- LEDST_COUNT,
-};
-
struct led_ops {
/**
* set_state() - set the state of an LED
static inline void cpu_to_be32_array(__be32 *dst, const u32 *src, size_t len)
{
- int i;
+ size_t i;
for (i = 0; i < len; i++)
dst[i] = cpu_to_be32(src[i]);
static inline void be32_to_cpu_array(u32 *dst, const __be32 *src, size_t len)
{
- int i;
+ size_t i;
for (i = 0; i < len; i++)
dst[i] = be32_to_cpu(src[i]);
/**
* read_poll_timeout - Periodically poll an address until a condition is met or a timeout occurs
* @op: accessor function (takes @addr as its only argument)
- * @addr: Address to poll
* @val: Variable to read the value into
* @cond: Break condition (usually involving @val)
* @sleep_us: Maximum time to sleep in us
* @timeout_us: Timeout in us, 0 means never timeout
+ * @args: arguments for @op poll
*
* Returns 0 on success and -ETIMEDOUT upon a timeout. In either
* case, the last read value at @addr is stored in @val.
* When available, you'll probably want to use one of the specialized
* macros defined below rather than this macro directly.
*/
-#define read_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \
+#define read_poll_timeout(op, val, cond, sleep_us, timeout_us, args...) \
({ \
unsigned long timeout = timer_get_us() + timeout_us; \
for (;;) { \
- (val) = op(addr); \
+ (val) = op(args); \
if (cond) \
break; \
if (timeout_us && time_after(timer_get_us(), timeout)) { \
- (val) = op(addr); \
+ (val) = op(args); \
break; \
} \
if (sleep_us) \
})
#define readx_poll_sleep_timeout(op, addr, val, cond, sleep_us, timeout_us) \
- read_poll_timeout(op, addr, val, cond, sleep_us, timeout_us)
+ read_poll_timeout(op, val, cond, sleep_us, timeout_us, addr)
#define readl_poll_sleep_timeout(addr, val, cond, sleep_us, timeout_us) \
readx_poll_sleep_timeout(readl, addr, val, cond, sleep_us, timeout_us)
#define readx_poll_timeout(op, addr, val, cond, timeout_us) \
- read_poll_timeout(op, addr, val, cond, false, timeout_us)
+ read_poll_timeout(op, val, cond, false, timeout_us, addr)
#define readb_poll_timeout(addr, val, cond, timeout_us) \
readx_poll_timeout(readb, addr, val, cond, timeout_us)
#if IS_ENABLED(CONFIG_DM)
#include <dm/device.h>
#endif
+#include <dm/ofnode.h>
#define MAX_MTD_DEVICES 32
#endif
struct device dev;
#else
struct udevice *dev;
+ ofnode flash_node;
#endif
int usecount;
#define malloc malloc_simple
#define realloc realloc_simple
#define memalign memalign_simple
+#if IS_ENABLED(CONFIG_VALGRIND)
+#define free free_simple
+#else
static inline void free(void *ptr) {}
+#endif
void *calloc(size_t nmemb, size_t size);
void *realloc_simple(void *ptr, size_t size);
#else
/*
* IMMRBAR - Internal Memory Register Base Address
*/
-#ifndef CONFIG_DEFAULT_IMMR
-/* Default IMMR base address */
-#define CONFIG_DEFAULT_IMMR 0xFF400000
-#endif
/* Register offset to immr */
#define IMMRBAR 0x0000
#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
* @return: pointer to phy_device if a PHY is found,
* or NULL otherwise
*/
-struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev);
+struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
+ int phyaddr);
static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
+int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
+ u16 set);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
+int phy_nxp_c45_tja11xx_init(void);
int phy_nxp_tja11xx_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
#include <asm/global_data.h>
#include <asm/spl.h>
#include <handoff.h>
+#include <mmc.h>
struct blk_desc;
struct image_header;
* Note: It is important to use the boot_device parameter instead of e.g.
* spl_boot_device() as U-Boot is not always loaded from the same device as SPL.
*/
-u32 spl_mmc_boot_mode(const u32 boot_device);
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device);
/**
* spl_mmc_boot_partition() - MMC partition to load U-Boot from.
*
* U-Boot uses linux types (linux/types.h) so does not make use of stdint.h
*/
+
+#ifndef __UB_STDINT_H
+#define __UB_STDINT_H
+
+#define UINT8_MAX 0xff
+
+#endif
*
* Shared between mkimage and the SPL.
*/
+
#ifndef SUNXI_IMAGE_H
#define SUNXI_IMAGE_H
+#include <linux/compiler_attributes.h>
+#include <linux/types.h>
+
#define BOOT0_MAGIC "eGON.BT0"
#define BROM_STAMP_VALUE 0x5f0a6c39
#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
/* Compile time check to assure proper alignment of structure */
typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)];
+struct __packed toc0_main_info {
+ uint8_t name[8];
+ __le32 magic;
+ __le32 checksum;
+ __le32 serial;
+ __le32 status;
+ __le32 num_items;
+ __le32 length;
+ uint8_t platform[4];
+ uint8_t reserved[8];
+ uint8_t end[4];
+};
+
+#define TOC0_MAIN_INFO_NAME "TOC0.GLH"
+#define TOC0_MAIN_INFO_MAGIC 0x89119800
+#define TOC0_MAIN_INFO_END "MIE;"
+
+struct __packed toc0_item_info {
+ __le32 name;
+ __le32 offset;
+ __le32 length;
+ __le32 status;
+ __le32 type;
+ __le32 load_addr;
+ uint8_t reserved[4];
+ uint8_t end[4];
+};
+
+#define TOC0_ITEM_INFO_NAME_CERT 0x00010101
+#define TOC0_ITEM_INFO_NAME_FIRMWARE 0x00010202
+#define TOC0_ITEM_INFO_NAME_KEY 0x00010303
+#define TOC0_ITEM_INFO_END "IIE;"
+
#endif
#ifndef _TABLES_CSUM_H_
#define _TABLES_CSUM_H_
-static inline u8 table_compute_checksum(void *v, int len)
-{
- u8 *bytes = v;
- u8 checksum = 0;
- int i;
-
- for (i = 0; i < len; i++)
- checksum -= bytes[i];
-
- return checksum;
-}
+/**
+ * table_compute_checksum() - Compute a table checksum
+ *
+ * This computes an 8-bit checksum for the configuration table.
+ * All bytes in the configuration table, including checksum itself and
+ * reserved bytes must add up to zero.
+ *
+ * @v: configuration table base address
+ * @len: configuration table size
+ * @return: the 8-bit checksum
+ */
+u8 table_compute_checksum(void *v, int len);
#endif
const void *hash, uint8_t *sig, uint sig_len);
int padding_pkcs_15_verify(struct image_sign_info *info,
- uint8_t *msg, int msg_len,
+ const uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
int padding_pss_verify(struct image_sign_info *info,
- uint8_t *msg, int msg_len,
+ const uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
#define RSA_DEFAULT_PADDING_NAME "pkcs-1.5"
--- /dev/null
+/* SPDX-License-Identifier: bzip2-1.0.6 */
+/*
+ This file is part of MemCheck, a heavyweight Valgrind tool for
+ detecting memory errors.
+
+ Copyright (C) 2000-2017 Julian Seward. All rights reserved.
+ */
+
+#ifndef __MEMCHECK_H
+#define __MEMCHECK_H
+
+
+/* This file is for inclusion into client (your!) code.
+
+ You can use these macros to manipulate and query memory permissions
+ inside your own programs.
+
+ See comment near the top of valgrind.h on how to use them.
+*/
+
+#include "valgrind.h"
+
+/* !! ABIWARNING !! ABIWARNING !! ABIWARNING !! ABIWARNING !!
+ This enum comprises an ABI exported by Valgrind to programs
+ which use client requests. DO NOT CHANGE THE ORDER OF THESE
+ ENTRIES, NOR DELETE ANY -- add new ones at the end. */
+typedef
+ enum {
+ VG_USERREQ__MAKE_MEM_NOACCESS = VG_USERREQ_TOOL_BASE('M','C'),
+ VG_USERREQ__MAKE_MEM_UNDEFINED,
+ VG_USERREQ__MAKE_MEM_DEFINED,
+ VG_USERREQ__DISCARD,
+ VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE,
+ VG_USERREQ__CHECK_MEM_IS_DEFINED,
+ VG_USERREQ__DO_LEAK_CHECK,
+ VG_USERREQ__COUNT_LEAKS,
+
+ VG_USERREQ__GET_VBITS,
+ VG_USERREQ__SET_VBITS,
+
+ VG_USERREQ__CREATE_BLOCK,
+
+ VG_USERREQ__MAKE_MEM_DEFINED_IF_ADDRESSABLE,
+
+ /* Not next to VG_USERREQ__COUNT_LEAKS because it was added later. */
+ VG_USERREQ__COUNT_LEAK_BLOCKS,
+
+ VG_USERREQ__ENABLE_ADDR_ERROR_REPORTING_IN_RANGE,
+ VG_USERREQ__DISABLE_ADDR_ERROR_REPORTING_IN_RANGE,
+
+ /* This is just for memcheck's internal use - don't use it */
+ _VG_USERREQ__MEMCHECK_RECORD_OVERLAP_ERROR
+ = VG_USERREQ_TOOL_BASE('M','C') + 256
+ } Vg_MemCheckClientRequest;
+
+
+
+/* Client-code macros to manipulate the state of memory. */
+
+/* Mark memory at _qzz_addr as unaddressable for _qzz_len bytes. */
+#define VALGRIND_MAKE_MEM_NOACCESS(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT( \
+ VG_USERREQ__MAKE_MEM_NOACCESS, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Similarly, mark memory at _qzz_addr as addressable but undefined
+ for _qzz_len bytes. */
+#define VALGRIND_MAKE_MEM_UNDEFINED(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT( \
+ VG_USERREQ__MAKE_MEM_UNDEFINED, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Similarly, mark memory at _qzz_addr as addressable and defined
+ for _qzz_len bytes. */
+#define VALGRIND_MAKE_MEM_DEFINED(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT( \
+ VG_USERREQ__MAKE_MEM_DEFINED, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Similar to VALGRIND_MAKE_MEM_DEFINED except that addressability is
+ not altered: bytes which are addressable are marked as defined,
+ but those which are not addressable are left unchanged. */
+#define VALGRIND_MAKE_MEM_DEFINED_IF_ADDRESSABLE(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT( \
+ VG_USERREQ__MAKE_MEM_DEFINED_IF_ADDRESSABLE, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Create a block-description handle. The description is an ascii
+ string which is included in any messages pertaining to addresses
+ within the specified memory range. Has no other effect on the
+ properties of the memory range. */
+#define VALGRIND_CREATE_BLOCK(_qzz_addr,_qzz_len, _qzz_desc) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT( \
+ VG_USERREQ__CREATE_BLOCK, \
+ (_qzz_addr), (_qzz_len), (_qzz_desc), \
+ 0, 0)
+
+/* Discard a block-description-handle. Returns 1 for an
+ invalid handle, 0 for a valid handle. */
+#define VALGRIND_DISCARD(_qzz_blkindex) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__DISCARD, \
+ 0, (_qzz_blkindex), 0, 0, 0)
+
+
+/* Client-code macros to check the state of memory. */
+
+/* Check that memory at _qzz_addr is addressable for _qzz_len bytes.
+ If suitable addressibility is not established, Valgrind prints an
+ error message and returns the address of the first offending byte.
+ Otherwise it returns zero. */
+#define VALGRIND_CHECK_MEM_IS_ADDRESSABLE(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Check that memory at _qzz_addr is addressable and defined for
+ _qzz_len bytes. If suitable addressibility and definedness are not
+ established, Valgrind prints an error message and returns the
+ address of the first offending byte. Otherwise it returns zero. */
+#define VALGRIND_CHECK_MEM_IS_DEFINED(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__CHECK_MEM_IS_DEFINED, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Use this macro to force the definedness and addressibility of an
+ lvalue to be checked. If suitable addressibility and definedness
+ are not established, Valgrind prints an error message and returns
+ the address of the first offending byte. Otherwise it returns
+ zero. */
+#define VALGRIND_CHECK_VALUE_IS_DEFINED(__lvalue) \
+ VALGRIND_CHECK_MEM_IS_DEFINED( \
+ (volatile unsigned char *)&(__lvalue), \
+ (unsigned long)(sizeof (__lvalue)))
+
+
+/* Do a full memory leak check (like --leak-check=full) mid-execution. */
+#define VALGRIND_DO_LEAK_CHECK \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK, \
+ 0, 0, 0, 0, 0)
+
+/* Same as VALGRIND_DO_LEAK_CHECK but only showing the entries for
+ which there was an increase in leaked bytes or leaked nr of blocks
+ since the previous leak search. */
+#define VALGRIND_DO_ADDED_LEAK_CHECK \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK, \
+ 0, 1, 0, 0, 0)
+
+/* Same as VALGRIND_DO_ADDED_LEAK_CHECK but showing entries with
+ increased or decreased leaked bytes/blocks since previous leak
+ search. */
+#define VALGRIND_DO_CHANGED_LEAK_CHECK \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK, \
+ 0, 2, 0, 0, 0)
+
+/* Do a summary memory leak check (like --leak-check=summary) mid-execution. */
+#define VALGRIND_DO_QUICK_LEAK_CHECK \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK, \
+ 1, 0, 0, 0, 0)
+
+/* Return number of leaked, dubious, reachable and suppressed bytes found by
+ all previous leak checks. They must be lvalues. */
+#define VALGRIND_COUNT_LEAKS(leaked, dubious, reachable, suppressed) \
+ /* For safety on 64-bit platforms we assign the results to private
+ unsigned long variables, then assign these to the lvalues the user
+ specified, which works no matter what type 'leaked', 'dubious', etc
+ are. We also initialise '_qzz_leaked', etc because
+ VG_USERREQ__COUNT_LEAKS doesn't mark the values returned as
+ defined. */ \
+ { \
+ unsigned long _qzz_leaked = 0, _qzz_dubious = 0; \
+ unsigned long _qzz_reachable = 0, _qzz_suppressed = 0; \
+ VALGRIND_DO_CLIENT_REQUEST_STMT( \
+ VG_USERREQ__COUNT_LEAKS, \
+ &_qzz_leaked, &_qzz_dubious, \
+ &_qzz_reachable, &_qzz_suppressed, 0); \
+ leaked = _qzz_leaked; \
+ dubious = _qzz_dubious; \
+ reachable = _qzz_reachable; \
+ suppressed = _qzz_suppressed; \
+ }
+
+/* Return number of leaked, dubious, reachable and suppressed bytes found by
+ all previous leak checks. They must be lvalues. */
+#define VALGRIND_COUNT_LEAK_BLOCKS(leaked, dubious, reachable, suppressed) \
+ /* For safety on 64-bit platforms we assign the results to private
+ unsigned long variables, then assign these to the lvalues the user
+ specified, which works no matter what type 'leaked', 'dubious', etc
+ are. We also initialise '_qzz_leaked', etc because
+ VG_USERREQ__COUNT_LEAKS doesn't mark the values returned as
+ defined. */ \
+ { \
+ unsigned long _qzz_leaked = 0, _qzz_dubious = 0; \
+ unsigned long _qzz_reachable = 0, _qzz_suppressed = 0; \
+ VALGRIND_DO_CLIENT_REQUEST_STMT( \
+ VG_USERREQ__COUNT_LEAK_BLOCKS, \
+ &_qzz_leaked, &_qzz_dubious, \
+ &_qzz_reachable, &_qzz_suppressed, 0); \
+ leaked = _qzz_leaked; \
+ dubious = _qzz_dubious; \
+ reachable = _qzz_reachable; \
+ suppressed = _qzz_suppressed; \
+ }
+
+
+/* Get the validity data for addresses [zza..zza+zznbytes-1] and copy it
+ into the provided zzvbits array. Return values:
+ 0 if not running on valgrind
+ 1 success
+ 2 [previously indicated unaligned arrays; these are now allowed]
+ 3 if any parts of zzsrc/zzvbits are not addressable.
+ The metadata is not copied in cases 0, 2 or 3 so it should be
+ impossible to segfault your system by using this call.
+*/
+#define VALGRIND_GET_VBITS(zza,zzvbits,zznbytes) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__GET_VBITS, \
+ (const char*)(zza), \
+ (char*)(zzvbits), \
+ (zznbytes), 0, 0)
+
+/* Set the validity data for addresses [zza..zza+zznbytes-1], copying it
+ from the provided zzvbits array. Return values:
+ 0 if not running on valgrind
+ 1 success
+ 2 [previously indicated unaligned arrays; these are now allowed]
+ 3 if any parts of zza/zzvbits are not addressable.
+ The metadata is not copied in cases 0, 2 or 3 so it should be
+ impossible to segfault your system by using this call.
+*/
+#define VALGRIND_SET_VBITS(zza,zzvbits,zznbytes) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__SET_VBITS, \
+ (const char*)(zza), \
+ (const char*)(zzvbits), \
+ (zznbytes), 0, 0 )
+
+/* Disable and re-enable reporting of addressing errors in the
+ specified address range. */
+#define VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__DISABLE_ADDR_ERROR_REPORTING_IN_RANGE, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+#define VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__ENABLE_ADDR_ERROR_REPORTING_IN_RANGE, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+#endif
+
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ AND bzip2-1.0.6 */
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2000-2017 Julian Seward. All rights reserved.
+ Copyright (C) 2021 Sean Anderson <seanga2@gmail.com>
+*/
+
+/* This file is for inclusion into client (your!) code.
+
+ You can use these macros to manipulate and query Valgrind's
+ execution inside your own programs.
+
+ The resulting executables will still run without Valgrind, just a
+ little bit more slowly than they otherwise would, but otherwise
+ unchanged. When not running on valgrind, each client request
+ consumes very few (eg. 7) instructions, so the resulting performance
+ loss is negligible unless you plan to execute client requests
+ millions of times per second. Nevertheless, if that is still a
+ problem, you can compile with the NVALGRIND symbol defined (gcc
+ -DNVALGRIND) so that client requests are not even compiled in. */
+
+#ifndef __VALGRIND_H
+#define __VALGRIND_H
+
+
+/* ------------------------------------------------------------------ */
+/* VERSION NUMBER OF VALGRIND */
+/* ------------------------------------------------------------------ */
+
+/* Specify Valgrind's version number, so that user code can
+ conditionally compile based on our version number. Note that these
+ were introduced at version 3.6 and so do not exist in version 3.5
+ or earlier. The recommended way to use them to check for "version
+ X.Y or later" is (eg)
+
+#if defined(__VALGRIND_MAJOR__) && defined(__VALGRIND_MINOR__) \
+ && (__VALGRIND_MAJOR__ > 3 \
+ || (__VALGRIND_MAJOR__ == 3 && __VALGRIND_MINOR__ >= 6))
+*/
+#define __VALGRIND_MAJOR__ 3
+#define __VALGRIND_MINOR__ 16
+
+
+#include <stdarg.h>
+
+/* Nb: this file might be included in a file compiled with -ansi. So
+ we can't use C++ style "//" comments nor the "asm" keyword (instead
+ use "__asm__"). */
+
+/* Derive some tags indicating what the target platform is. Note
+ that in this file we're using the compiler's CPP symbols for
+ identifying architectures, which are different to the ones we use
+ within the rest of Valgrind. Note, __powerpc__ is active for both
+ 32 and 64-bit PPC, whereas __powerpc64__ is only active for the
+ latter (on Linux, that is).
+
+ Misc note: how to find out what's predefined in gcc by default:
+ gcc -Wp,-dM somefile.c
+*/
+#undef PLAT_x86_darwin
+#undef PLAT_amd64_darwin
+#undef PLAT_x86_win32
+#undef PLAT_amd64_win64
+#undef PLAT_x86_linux
+#undef PLAT_amd64_linux
+#undef PLAT_ppc32_linux
+#undef PLAT_ppc64be_linux
+#undef PLAT_ppc64le_linux
+#undef PLAT_arm_linux
+#undef PLAT_arm64_linux
+#undef PLAT_s390x_linux
+#undef PLAT_mips32_linux
+#undef PLAT_mips64_linux
+#undef PLAT_nanomips_linux
+#undef PLAT_x86_solaris
+#undef PLAT_amd64_solaris
+
+
+#if defined(__APPLE__) && defined(__i386__)
+# define PLAT_x86_darwin 1
+#elif defined(__APPLE__) && defined(__x86_64__)
+# define PLAT_amd64_darwin 1
+#elif (defined(__MINGW32__) && defined(__i386__)) \
+ || defined(__CYGWIN32__) \
+ || (defined(_WIN32) && defined(_M_IX86))
+# define PLAT_x86_win32 1
+#elif (defined(__MINGW32__) && defined(__x86_64__)) \
+ || (defined(_WIN32) && defined(_M_X64))
+/* __MINGW32__ and _WIN32 are defined in 64 bit mode as well. */
+# define PLAT_amd64_win64 1
+#elif defined(__linux__) && defined(__i386__)
+# define PLAT_x86_linux 1
+#elif defined(__linux__) && defined(__x86_64__) && !defined(__ILP32__)
+# define PLAT_amd64_linux 1
+#elif defined(__linux__) && defined(__powerpc__) && !defined(__powerpc64__)
+# define PLAT_ppc32_linux 1
+#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) && _CALL_ELF != 2
+/* Big Endian uses ELF version 1 */
+# define PLAT_ppc64be_linux 1
+#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) && _CALL_ELF == 2
+/* Little Endian uses ELF version 2 */
+# define PLAT_ppc64le_linux 1
+#elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__)
+# define PLAT_arm_linux 1
+#elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__)
+# define PLAT_arm64_linux 1
+#elif defined(__linux__) && defined(__s390__) && defined(__s390x__)
+# define PLAT_s390x_linux 1
+#elif defined(__linux__) && defined(__mips__) && (__mips==64)
+# define PLAT_mips64_linux 1
+#elif defined(__linux__) && defined(__mips__) && (__mips==32)
+# define PLAT_mips32_linux 1
+#elif defined(__linux__) && defined(__nanomips__)
+# define PLAT_nanomips_linux 1
+#elif defined(__sun) && defined(__i386__)
+# define PLAT_x86_solaris 1
+#elif defined(__sun) && defined(__x86_64__)
+# define PLAT_amd64_solaris 1
+#else
+/* If we're not compiling for our target platform, don't generate
+ any inline asms. */
+# undef CONFIG_VALGRIND
+#endif
+
+
+/* ------------------------------------------------------------------ */
+/* ARCHITECTURE SPECIFICS for SPECIAL INSTRUCTIONS. There is nothing */
+/* in here of use to end-users -- skip to the next section. */
+/* ------------------------------------------------------------------ */
+
+/*
+ * VALGRIND_DO_CLIENT_REQUEST(): a statement that invokes a Valgrind client
+ * request. Accepts both pointers and integers as arguments.
+ *
+ * VALGRIND_DO_CLIENT_REQUEST_STMT(): a statement that invokes a Valgrind
+ * client request that does not return a value.
+
+ * VALGRIND_DO_CLIENT_REQUEST_EXPR(): a C expression that invokes a Valgrind
+ * client request and whose value equals the client request result. Accepts
+ * both pointers and integers as arguments. Note that such calls are not
+ * necessarily pure functions -- they may have side effects.
+ */
+
+#define VALGRIND_DO_CLIENT_REQUEST(_zzq_rlval, _zzq_default, \
+ _zzq_request, _zzq_arg1, _zzq_arg2, \
+ _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ do { (_zzq_rlval) = VALGRIND_DO_CLIENT_REQUEST_EXPR((_zzq_default), \
+ (_zzq_request), (_zzq_arg1), (_zzq_arg2), \
+ (_zzq_arg3), (_zzq_arg4), (_zzq_arg5)); } while (0)
+
+#define VALGRIND_DO_CLIENT_REQUEST_STMT(_zzq_request, _zzq_arg1, \
+ _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ do { (void) VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ (_zzq_request), (_zzq_arg1), (_zzq_arg2), \
+ (_zzq_arg3), (_zzq_arg4), (_zzq_arg5)); } while (0)
+
+#if !IS_ENABLED(CONFIG_VALGRIND)
+
+/* Define NVALGRIND to completely remove the Valgrind magic sequence
+ from the compiled code (analogous to NDEBUG's effects on
+ assert()) */
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ (_zzq_default)
+
+#else /* ! CONFIG_VALGRIND */
+
+/* The following defines the magic code sequences which the JITter
+ spots and handles magically. Don't look too closely at them as
+ they will rot your brain.
+
+ The assembly code sequences for all architectures is in this one
+ file. This is because this file must be stand-alone, and we don't
+ want to have multiple files.
+
+ For VALGRIND_DO_CLIENT_REQUEST, we must ensure that the default
+ value gets put in the return slot, so that everything works when
+ this is executed not under Valgrind. Args are passed in a memory
+ block, and so there's no intrinsic limit to the number that could
+ be passed, but it's currently five.
+
+ The macro args are:
+ _zzq_rlval result lvalue
+ _zzq_default default value (result returned when running on real CPU)
+ _zzq_request request code
+ _zzq_arg1..5 request params
+
+ The other two macros are used to support function wrapping, and are
+ a lot simpler. VALGRIND_GET_NR_CONTEXT returns the value of the
+ guest's NRADDR pseudo-register and whatever other information is
+ needed to safely run the call original from the wrapper: on
+ ppc64-linux, the R2 value at the divert point is also needed. This
+ information is abstracted into a user-visible type, OrigFn.
+
+ VALGRIND_CALL_NOREDIR_* behaves the same as the following on the
+ guest, but guarantees that the branch instruction will not be
+ redirected: x86: call *%eax, amd64: call *%rax, ppc32/ppc64:
+ branch-and-link-to-r11. VALGRIND_CALL_NOREDIR is just text, not a
+ complete inline asm, since it needs to be combined with more magic
+ inline asm stuff to be useful.
+*/
+
+/* ----------------- x86-{linux,darwin,solaris} ---------------- */
+
+#if defined(PLAT_x86_linux) || defined(PLAT_x86_darwin) \
+ || (defined(PLAT_x86_win32) && defined(__GNUC__)) \
+ || defined(PLAT_x86_solaris)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "roll $3, %%edi ; roll $13, %%edi\n\t" \
+ "roll $29, %%edi ; roll $19, %%edi\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({volatile unsigned int _zzq_args[6]; \
+ volatile unsigned int _zzq_result; \
+ _zzq_args[0] = (unsigned int)(_zzq_request); \
+ _zzq_args[1] = (unsigned int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned int)(_zzq_arg5); \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %EDX = client_request ( %EAX ) */ \
+ "xchgl %%ebx,%%ebx" \
+ : "=d" (_zzq_result) \
+ : "a" (&_zzq_args[0]), "0" (_zzq_default) \
+ : "cc", "memory" \
+ ); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %EAX = guest_NRADDR */ \
+ "xchgl %%ecx,%%ecx" \
+ : "=a" (__addr) \
+ : \
+ : "cc", "memory" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_EAX \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* call-noredir *%EAX */ \
+ "xchgl %%edx,%%edx\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "xchgl %%edi,%%edi\n\t" \
+ : : : "cc", "memory" \
+ ); \
+ } while (0)
+
+#endif /* PLAT_x86_linux || PLAT_x86_darwin || (PLAT_x86_win32 && __GNUC__)
+ || PLAT_x86_solaris */
+
+/* ------------------------- x86-Win32 ------------------------- */
+
+#if defined(PLAT_x86_win32) && !defined(__GNUC__)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#if defined(_MSC_VER)
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ __asm rol edi, 3 __asm rol edi, 13 \
+ __asm rol edi, 29 __asm rol edi, 19
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ valgrind_do_client_request_expr((uintptr_t)(_zzq_default), \
+ (uintptr_t)(_zzq_request), (uintptr_t)(_zzq_arg1), \
+ (uintptr_t)(_zzq_arg2), (uintptr_t)(_zzq_arg3), \
+ (uintptr_t)(_zzq_arg4), (uintptr_t)(_zzq_arg5))
+
+static __inline uintptr_t
+valgrind_do_client_request_expr(uintptr_t _zzq_default, uintptr_t _zzq_request,
+ uintptr_t _zzq_arg1, uintptr_t _zzq_arg2,
+ uintptr_t _zzq_arg3, uintptr_t _zzq_arg4,
+ uintptr_t _zzq_arg5)
+{
+ volatile uintptr_t _zzq_args[6];
+ volatile unsigned int _zzq_result;
+ _zzq_args[0] = (uintptr_t)(_zzq_request);
+ _zzq_args[1] = (uintptr_t)(_zzq_arg1);
+ _zzq_args[2] = (uintptr_t)(_zzq_arg2);
+ _zzq_args[3] = (uintptr_t)(_zzq_arg3);
+ _zzq_args[4] = (uintptr_t)(_zzq_arg4);
+ _zzq_args[5] = (uintptr_t)(_zzq_arg5);
+ __asm { __asm lea eax, _zzq_args __asm mov edx, _zzq_default
+ __SPECIAL_INSTRUCTION_PREAMBLE
+ /* %EDX = client_request ( %EAX ) */
+ __asm xchg ebx,ebx
+ __asm mov _zzq_result, edx
+ }
+ return _zzq_result;
+}
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned int __addr; \
+ __asm { __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %EAX = guest_NRADDR */ \
+ __asm xchg ecx,ecx \
+ __asm mov __addr, eax \
+ } \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_EAX ERROR
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm { __SPECIAL_INSTRUCTION_PREAMBLE \
+ __asm xchg edi,edi \
+ } \
+ } while (0)
+
+#else
+#error Unsupported compiler.
+#endif
+
+#endif /* PLAT_x86_win32 */
+
+/* ----------------- amd64-{linux,darwin,solaris} --------------- */
+
+#if defined(PLAT_amd64_linux) || defined(PLAT_amd64_darwin) \
+ || defined(PLAT_amd64_solaris) \
+ || (defined(PLAT_amd64_win64) && defined(__GNUC__))
+
+typedef
+ struct {
+ unsigned long int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "rolq $3, %%rdi ; rolq $13, %%rdi\n\t" \
+ "rolq $61, %%rdi ; rolq $51, %%rdi\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({ volatile unsigned long int _zzq_args[6]; \
+ volatile unsigned long int _zzq_result; \
+ _zzq_args[0] = (unsigned long int)(_zzq_request); \
+ _zzq_args[1] = (unsigned long int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned long int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned long int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned long int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned long int)(_zzq_arg5); \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %RDX = client_request ( %RAX ) */ \
+ "xchgq %%rbx,%%rbx" \
+ : "=d" (_zzq_result) \
+ : "a" (&_zzq_args[0]), "0" (_zzq_default) \
+ : "cc", "memory" \
+ ); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %RAX = guest_NRADDR */ \
+ "xchgq %%rcx,%%rcx" \
+ : "=a" (__addr) \
+ : \
+ : "cc", "memory" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_RAX \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* call-noredir *%RAX */ \
+ "xchgq %%rdx,%%rdx\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "xchgq %%rdi,%%rdi\n\t" \
+ : : : "cc", "memory" \
+ ); \
+ } while (0)
+
+#endif /* PLAT_amd64_linux || PLAT_amd64_darwin || PLAT_amd64_solaris */
+
+/* ------------------------- amd64-Win64 ------------------------- */
+
+#if defined(PLAT_amd64_win64) && !defined(__GNUC__)
+
+#error Unsupported compiler.
+
+#endif /* PLAT_amd64_win64 */
+
+/* ------------------------ ppc32-linux ------------------------ */
+
+#if defined(PLAT_ppc32_linux)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "rlwinm 0,0,3,0,31 ; rlwinm 0,0,13,0,31\n\t" \
+ "rlwinm 0,0,29,0,31 ; rlwinm 0,0,19,0,31\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ \
+ __extension__ \
+ ({ unsigned int _zzq_args[6]; \
+ unsigned int _zzq_result; \
+ unsigned int* _zzq_ptr; \
+ _zzq_args[0] = (unsigned int)(_zzq_request); \
+ _zzq_args[1] = (unsigned int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned int)(_zzq_arg5); \
+ _zzq_ptr = _zzq_args; \
+ __asm__ volatile("mr 3,%1\n\t" /*default*/ \
+ "mr 4,%2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = client_request ( %R4 ) */ \
+ "or 1,1,1\n\t" \
+ "mr %0,3" /*result*/ \
+ : "=b" (_zzq_result) \
+ : "b" (_zzq_default), "b" (_zzq_ptr) \
+ : "cc", "memory", "r3", "r4"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ unsigned int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = guest_NRADDR */ \
+ "or 2,2,2\n\t" \
+ "mr %0,3" \
+ : "=b" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* branch-and-link-to-noredir *%R11 */ \
+ "or 3,3,3\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "or 5,5,5\n\t" \
+ ); \
+ } while (0)
+
+#endif /* PLAT_ppc32_linux */
+
+/* ------------------------ ppc64-linux ------------------------ */
+
+#if defined(PLAT_ppc64be_linux)
+
+typedef
+ struct {
+ unsigned long int nraddr; /* where's the code? */
+ unsigned long int r2; /* what tocptr do we need? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "rotldi 0,0,3 ; rotldi 0,0,13\n\t" \
+ "rotldi 0,0,61 ; rotldi 0,0,51\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ \
+ __extension__ \
+ ({ unsigned long int _zzq_args[6]; \
+ unsigned long int _zzq_result; \
+ unsigned long int* _zzq_ptr; \
+ _zzq_args[0] = (unsigned long int)(_zzq_request); \
+ _zzq_args[1] = (unsigned long int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned long int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned long int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned long int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned long int)(_zzq_arg5); \
+ _zzq_ptr = _zzq_args; \
+ __asm__ volatile("mr 3,%1\n\t" /*default*/ \
+ "mr 4,%2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = client_request ( %R4 ) */ \
+ "or 1,1,1\n\t" \
+ "mr %0,3" /*result*/ \
+ : "=b" (_zzq_result) \
+ : "b" (_zzq_default), "b" (_zzq_ptr) \
+ : "cc", "memory", "r3", "r4"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ unsigned long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = guest_NRADDR */ \
+ "or 2,2,2\n\t" \
+ "mr %0,3" \
+ : "=b" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = guest_NRADDR_GPR2 */ \
+ "or 4,4,4\n\t" \
+ "mr %0,3" \
+ : "=b" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->r2 = __addr; \
+ }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* branch-and-link-to-noredir *%R11 */ \
+ "or 3,3,3\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "or 5,5,5\n\t" \
+ ); \
+ } while (0)
+
+#endif /* PLAT_ppc64be_linux */
+
+#if defined(PLAT_ppc64le_linux)
+
+typedef
+ struct {
+ unsigned long int nraddr; /* where's the code? */
+ unsigned long int r2; /* what tocptr do we need? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "rotldi 0,0,3 ; rotldi 0,0,13\n\t" \
+ "rotldi 0,0,61 ; rotldi 0,0,51\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ \
+ __extension__ \
+ ({ unsigned long int _zzq_args[6]; \
+ unsigned long int _zzq_result; \
+ unsigned long int* _zzq_ptr; \
+ _zzq_args[0] = (unsigned long int)(_zzq_request); \
+ _zzq_args[1] = (unsigned long int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned long int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned long int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned long int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned long int)(_zzq_arg5); \
+ _zzq_ptr = _zzq_args; \
+ __asm__ volatile("mr 3,%1\n\t" /*default*/ \
+ "mr 4,%2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = client_request ( %R4 ) */ \
+ "or 1,1,1\n\t" \
+ "mr %0,3" /*result*/ \
+ : "=b" (_zzq_result) \
+ : "b" (_zzq_default), "b" (_zzq_ptr) \
+ : "cc", "memory", "r3", "r4"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ unsigned long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = guest_NRADDR */ \
+ "or 2,2,2\n\t" \
+ "mr %0,3" \
+ : "=b" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = guest_NRADDR_GPR2 */ \
+ "or 4,4,4\n\t" \
+ "mr %0,3" \
+ : "=b" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->r2 = __addr; \
+ }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* branch-and-link-to-noredir *%R12 */ \
+ "or 3,3,3\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "or 5,5,5\n\t" \
+ ); \
+ } while (0)
+
+#endif /* PLAT_ppc64le_linux */
+
+/* ------------------------- arm-linux ------------------------- */
+
+#if defined(PLAT_arm_linux)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "mov r12, r12, ror #3 ; mov r12, r12, ror #13 \n\t" \
+ "mov r12, r12, ror #29 ; mov r12, r12, ror #19 \n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ \
+ __extension__ \
+ ({volatile unsigned int _zzq_args[6]; \
+ volatile unsigned int _zzq_result; \
+ _zzq_args[0] = (unsigned int)(_zzq_request); \
+ _zzq_args[1] = (unsigned int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned int)(_zzq_arg5); \
+ __asm__ volatile("mov r3, %1\n\t" /*default*/ \
+ "mov r4, %2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* R3 = client_request ( R4 ) */ \
+ "orr r10, r10, r10\n\t" \
+ "mov %0, r3" /*result*/ \
+ : "=r" (_zzq_result) \
+ : "r" (_zzq_default), "r" (&_zzq_args[0]) \
+ : "cc","memory", "r3", "r4"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ unsigned int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* R3 = guest_NRADDR */ \
+ "orr r11, r11, r11\n\t" \
+ "mov %0, r3" \
+ : "=r" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* branch-and-link-to-noredir *%R4 */ \
+ "orr r12, r12, r12\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "orr r9, r9, r9\n\t" \
+ : : : "cc", "memory" \
+ ); \
+ } while (0)
+
+#endif /* PLAT_arm_linux */
+
+/* ------------------------ arm64-linux ------------------------- */
+
+#if defined(PLAT_arm64_linux)
+
+typedef
+ struct {
+ unsigned long int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "ror x12, x12, #3 ; ror x12, x12, #13 \n\t" \
+ "ror x12, x12, #51 ; ror x12, x12, #61 \n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ \
+ __extension__ \
+ ({volatile unsigned long int _zzq_args[6]; \
+ volatile unsigned long int _zzq_result; \
+ _zzq_args[0] = (unsigned long int)(_zzq_request); \
+ _zzq_args[1] = (unsigned long int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned long int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned long int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned long int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned long int)(_zzq_arg5); \
+ __asm__ volatile("mov x3, %1\n\t" /*default*/ \
+ "mov x4, %2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* X3 = client_request ( X4 ) */ \
+ "orr x10, x10, x10\n\t" \
+ "mov %0, x3" /*result*/ \
+ : "=r" (_zzq_result) \
+ : "r" ((unsigned long int)(_zzq_default)), \
+ "r" (&_zzq_args[0]) \
+ : "cc","memory", "x3", "x4"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ unsigned long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* X3 = guest_NRADDR */ \
+ "orr x11, x11, x11\n\t" \
+ "mov %0, x3" \
+ : "=r" (__addr) \
+ : \
+ : "cc", "memory", "x3" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* branch-and-link-to-noredir X8 */ \
+ "orr x12, x12, x12\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "orr x9, x9, x9\n\t" \
+ : : : "cc", "memory" \
+ ); \
+ } while (0)
+
+#endif /* PLAT_arm64_linux */
+
+/* ------------------------ s390x-linux ------------------------ */
+
+#if defined(PLAT_s390x_linux)
+
+typedef
+ struct {
+ unsigned long int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+/* __SPECIAL_INSTRUCTION_PREAMBLE will be used to identify Valgrind specific
+ * code. This detection is implemented in platform specific toIR.c
+ * (e.g. VEX/priv/guest_s390_decoder.c).
+ */
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "lr 15,15\n\t" \
+ "lr 1,1\n\t" \
+ "lr 2,2\n\t" \
+ "lr 3,3\n\t"
+
+#define __CLIENT_REQUEST_CODE "lr 2,2\n\t"
+#define __GET_NR_CONTEXT_CODE "lr 3,3\n\t"
+#define __CALL_NO_REDIR_CODE "lr 4,4\n\t"
+#define __VEX_INJECT_IR_CODE "lr 5,5\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({volatile unsigned long int _zzq_args[6]; \
+ volatile unsigned long int _zzq_result; \
+ _zzq_args[0] = (unsigned long int)(_zzq_request); \
+ _zzq_args[1] = (unsigned long int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned long int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned long int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned long int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned long int)(_zzq_arg5); \
+ __asm__ volatile(/* r2 = args */ \
+ "lgr 2,%1\n\t" \
+ /* r3 = default */ \
+ "lgr 3,%2\n\t" \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ __CLIENT_REQUEST_CODE \
+ /* results = r3 */ \
+ "lgr %0, 3\n\t" \
+ : "=d" (_zzq_result) \
+ : "a" (&_zzq_args[0]), "0" (_zzq_default) \
+ : "cc", "2", "3", "memory" \
+ ); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ __GET_NR_CONTEXT_CODE \
+ "lgr %0, 3\n\t" \
+ : "=a" (__addr) \
+ : \
+ : "cc", "3", "memory" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_R1 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ __CALL_NO_REDIR_CODE
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ __VEX_INJECT_IR_CODE); \
+ } while (0)
+
+#endif /* PLAT_s390x_linux */
+
+/* ------------------------- mips32-linux ---------------- */
+
+#if defined(PLAT_mips32_linux)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+/* .word 0x342
+ * .word 0x742
+ * .word 0xC2
+ * .word 0x4C2*/
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "srl $0, $0, 13\n\t" \
+ "srl $0, $0, 29\n\t" \
+ "srl $0, $0, 3\n\t" \
+ "srl $0, $0, 19\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({ volatile unsigned int _zzq_args[6]; \
+ volatile unsigned int _zzq_result; \
+ _zzq_args[0] = (unsigned int)(_zzq_request); \
+ _zzq_args[1] = (unsigned int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned int)(_zzq_arg5); \
+ __asm__ volatile("move $11, %1\n\t" /*default*/ \
+ "move $12, %2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* T3 = client_request ( T4 ) */ \
+ "or $13, $13, $13\n\t" \
+ "move %0, $11\n\t" /*result*/ \
+ : "=r" (_zzq_result) \
+ : "r" (_zzq_default), "r" (&_zzq_args[0]) \
+ : "$11", "$12", "memory"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %t9 = guest_NRADDR */ \
+ "or $14, $14, $14\n\t" \
+ "move %0, $11" /*result*/ \
+ : "=r" (__addr) \
+ : \
+ : "$11" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_T9 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* call-noredir *%t9 */ \
+ "or $15, $15, $15\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "or $11, $11, $11\n\t" \
+ ); \
+ } while (0)
+
+
+#endif /* PLAT_mips32_linux */
+
+/* ------------------------- mips64-linux ---------------- */
+
+#if defined(PLAT_mips64_linux)
+
+typedef
+ struct {
+ unsigned long nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+/* dsll $0,$0, 3
+ * dsll $0,$0, 13
+ * dsll $0,$0, 29
+ * dsll $0,$0, 19*/
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "dsll $0,$0, 3 ; dsll $0,$0,13\n\t" \
+ "dsll $0,$0,29 ; dsll $0,$0,19\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({ volatile unsigned long int _zzq_args[6]; \
+ volatile unsigned long int _zzq_result; \
+ _zzq_args[0] = (unsigned long int)(_zzq_request); \
+ _zzq_args[1] = (unsigned long int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned long int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned long int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned long int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned long int)(_zzq_arg5); \
+ __asm__ volatile("move $11, %1\n\t" /*default*/ \
+ "move $12, %2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* $11 = client_request ( $12 ) */ \
+ "or $13, $13, $13\n\t" \
+ "move %0, $11\n\t" /*result*/ \
+ : "=r" (_zzq_result) \
+ : "r" (_zzq_default), "r" (&_zzq_args[0]) \
+ : "$11", "$12", "memory"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* $11 = guest_NRADDR */ \
+ "or $14, $14, $14\n\t" \
+ "move %0, $11" /*result*/ \
+ : "=r" (__addr) \
+ : \
+ : "$11"); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_T9 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* call-noredir $25 */ \
+ "or $15, $15, $15\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "or $11, $11, $11\n\t" \
+ ); \
+ } while (0)
+
+#endif /* PLAT_mips64_linux */
+
+#if defined(PLAT_nanomips_linux)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+/*
+ 8000 c04d srl zero, zero, 13
+ 8000 c05d srl zero, zero, 29
+ 8000 c043 srl zero, zero, 3
+ 8000 c053 srl zero, zero, 19
+*/
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE "srl[32] $zero, $zero, 13 \n\t" \
+ "srl[32] $zero, $zero, 29 \n\t" \
+ "srl[32] $zero, $zero, 3 \n\t" \
+ "srl[32] $zero, $zero, 19 \n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({ volatile unsigned int _zzq_args[6]; \
+ volatile unsigned int _zzq_result; \
+ _zzq_args[0] = (unsigned int)(_zzq_request); \
+ _zzq_args[1] = (unsigned int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned int)(_zzq_arg5); \
+ __asm__ volatile("move $a7, %1\n\t" /* default */ \
+ "move $t0, %2\n\t" /* ptr */ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* $a7 = client_request( $t0 ) */ \
+ "or[32] $t0, $t0, $t0\n\t" \
+ "move %0, $a7\n\t" /* result */ \
+ : "=r" (_zzq_result) \
+ : "r" (_zzq_default), "r" (&_zzq_args[0]) \
+ : "$a7", "$t0", "memory"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* $a7 = guest_NRADDR */ \
+ "or[32] $t1, $t1, $t1\n\t" \
+ "move %0, $a7" /*result*/ \
+ : "=r" (__addr) \
+ : \
+ : "$a7"); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_T9 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* call-noredir $25 */ \
+ "or[32] $t2, $t2, $t2\n\t"
+
+#define VALGRIND_VEX_INJECT_IR() \
+ do { \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ "or[32] $t3, $t3, $t3\n\t" \
+ ); \
+ } while (0)
+
+#endif
+/* Insert assembly code for other platforms here... */
+
+#endif /* CONFIG_VALGRIND */
+
+
+/* ------------------------------------------------------------------ */
+/* PLATFORM SPECIFICS for FUNCTION WRAPPING. This is all very */
+/* ugly. It's the least-worst tradeoff I can think of. */
+/* ------------------------------------------------------------------ */
+
+/* This section defines magic (a.k.a appalling-hack) macros for doing
+ guaranteed-no-redirection macros, so as to get from function
+ wrappers to the functions they are wrapping. The whole point is to
+ construct standard call sequences, but to do the call itself with a
+ special no-redirect call pseudo-instruction that the JIT
+ understands and handles specially. This section is long and
+ repetitious, and I can't see a way to make it shorter.
+
+ The naming scheme is as follows:
+
+ CALL_FN_{W,v}_{v,W,WW,WWW,WWWW,5W,6W,7W,etc}
+
+ 'W' stands for "word" and 'v' for "void". Hence there are
+ different macros for calling arity 0, 1, 2, 3, 4, etc, functions,
+ and for each, the possibility of returning a word-typed result, or
+ no result.
+*/
+
+/* Use these to write the name of your wrapper. NOTE: duplicates
+ VG_WRAP_FUNCTION_Z{U,Z} in pub_tool_redir.h. NOTE also: inserts
+ the default behaviour equivalance class tag "0000" into the name.
+ See pub_tool_redir.h for details -- normally you don't need to
+ think about this, though. */
+
+/* Use an extra level of macroisation so as to ensure the soname/fnname
+ args are fully macro-expanded before pasting them together. */
+#define VG_CONCAT4(_aa,_bb,_cc,_dd) _aa##_bb##_cc##_dd
+
+#define I_WRAP_SONAME_FNNAME_ZU(soname,fnname) \
+ VG_CONCAT4(_vgw00000ZU_,soname,_,fnname)
+
+#define I_WRAP_SONAME_FNNAME_ZZ(soname,fnname) \
+ VG_CONCAT4(_vgw00000ZZ_,soname,_,fnname)
+
+/* Use this macro from within a wrapper function to collect the
+ context (address and possibly other info) of the original function.
+ Once you have that you can then use it in one of the CALL_FN_
+ macros. The type of the argument _lval is OrigFn. */
+#define VALGRIND_GET_ORIG_FN(_lval) VALGRIND_GET_NR_CONTEXT(_lval)
+
+/* Also provide end-user facilities for function replacement, rather
+ than wrapping. A replacement function differs from a wrapper in
+ that it has no way to get hold of the original function being
+ called, and hence no way to call onwards to it. In a replacement
+ function, VALGRIND_GET_ORIG_FN always returns zero. */
+
+#define I_REPLACE_SONAME_FNNAME_ZU(soname,fnname) \
+ VG_CONCAT4(_vgr00000ZU_,soname,_,fnname)
+
+#define I_REPLACE_SONAME_FNNAME_ZZ(soname,fnname) \
+ VG_CONCAT4(_vgr00000ZZ_,soname,_,fnname)
+
+/* Derivatives of the main macros below, for calling functions
+ returning void. */
+
+#define CALL_FN_v_v(fnptr) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_v(_junk,fnptr); } while (0)
+
+#define CALL_FN_v_W(fnptr, arg1) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_W(_junk,fnptr,arg1); } while (0)
+
+#define CALL_FN_v_WW(fnptr, arg1,arg2) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_WW(_junk,fnptr,arg1,arg2); } while (0)
+
+#define CALL_FN_v_WWW(fnptr, arg1,arg2,arg3) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_WWW(_junk,fnptr,arg1,arg2,arg3); } while (0)
+
+#define CALL_FN_v_WWWW(fnptr, arg1,arg2,arg3,arg4) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_WWWW(_junk,fnptr,arg1,arg2,arg3,arg4); } while (0)
+
+#define CALL_FN_v_5W(fnptr, arg1,arg2,arg3,arg4,arg5) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_5W(_junk,fnptr,arg1,arg2,arg3,arg4,arg5); } while (0)
+
+#define CALL_FN_v_6W(fnptr, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_6W(_junk,fnptr,arg1,arg2,arg3,arg4,arg5,arg6); } while (0)
+
+#define CALL_FN_v_7W(fnptr, arg1,arg2,arg3,arg4,arg5,arg6,arg7) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_7W(_junk,fnptr,arg1,arg2,arg3,arg4,arg5,arg6,arg7); } while (0)
+
+/* ----------------- x86-{linux,darwin,solaris} ---------------- */
+
+#if defined(PLAT_x86_linux) || defined(PLAT_x86_darwin) \
+ || defined(PLAT_x86_solaris)
+
+/* These regs are trashed by the hidden call. No need to mention eax
+ as gcc can already see that, plus causes gcc to bomb. */
+#define __CALLER_SAVED_REGS /*"eax"*/ "ecx", "edx"
+
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+#define VALGRIND_ALIGN_STACK \
+ "movl %%esp,%%edi\n\t" \
+ "andl $0xfffffff0,%%esp\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "movl %%edi,%%esp\n\t"
+
+/* These CALL_FN_ macros assume that on x86-linux, sizeof(unsigned
+ long) == 4. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "subl $12, %%esp\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "subl $8, %%esp\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "subl $4, %%esp\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "subl $12, %%esp\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "subl $8, %%esp\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "subl $4, %%esp\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "subl $12, %%esp\n\t" \
+ "pushl 36(%%eax)\n\t" \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "subl $8, %%esp\n\t" \
+ "pushl 40(%%eax)\n\t" \
+ "pushl 36(%%eax)\n\t" \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "subl $4, %%esp\n\t" \
+ "pushl 44(%%eax)\n\t" \
+ "pushl 40(%%eax)\n\t" \
+ "pushl 36(%%eax)\n\t" \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "pushl 48(%%eax)\n\t" \
+ "pushl 44(%%eax)\n\t" \
+ "pushl 40(%%eax)\n\t" \
+ "pushl 36(%%eax)\n\t" \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_x86_linux || PLAT_x86_darwin || PLAT_x86_solaris */
+
+/* ---------------- amd64-{linux,darwin,solaris} --------------- */
+
+#if defined(PLAT_amd64_linux) || defined(PLAT_amd64_darwin) \
+ || defined(PLAT_amd64_solaris)
+
+/* ARGREGS: rdi rsi rdx rcx r8 r9 (the rest on stack in R-to-L order) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS /*"rax",*/ "rcx", "rdx", "rsi", \
+ "rdi", "r8", "r9", "r10", "r11"
+
+/* This is all pretty complex. It's so as to make stack unwinding
+ work reliably. See bug 243270. The basic problem is the sub and
+ add of 128 of %rsp in all of the following macros. If gcc believes
+ the CFA is in %rsp, then unwinding may fail, because what's at the
+ CFA is not what gcc "expected" when it constructs the CFIs for the
+ places where the macros are instantiated.
+
+ But we can't just add a CFI annotation to increase the CFA offset
+ by 128, to match the sub of 128 from %rsp, because we don't know
+ whether gcc has chosen %rsp as the CFA at that point, or whether it
+ has chosen some other register (eg, %rbp). In the latter case,
+ adding a CFI annotation to change the CFA offset is simply wrong.
+
+ So the solution is to get hold of the CFA using
+ __builtin_dwarf_cfa(), put it in a known register, and add a
+ CFI annotation to say what the register is. We choose %rbp for
+ this (perhaps perversely), because:
+
+ (1) %rbp is already subject to unwinding. If a new register was
+ chosen then the unwinder would have to unwind it in all stack
+ traces, which is expensive, and
+
+ (2) %rbp is already subject to precise exception updates in the
+ JIT. If a new register was chosen, we'd have to have precise
+ exceptions for it too, which reduces performance of the
+ generated code.
+
+ However .. one extra complication. We can't just whack the result
+ of __builtin_dwarf_cfa() into %rbp and then add %rbp to the
+ list of trashed registers at the end of the inline assembly
+ fragments; gcc won't allow %rbp to appear in that list. Hence
+ instead we need to stash %rbp in %r15 for the duration of the asm,
+ and say that %r15 is trashed instead. gcc seems happy to go with
+ that.
+
+ Oh .. and this all needs to be conditionalised so that it is
+ unchanged from before this commit, when compiled with older gccs
+ that don't support __builtin_dwarf_cfa. Furthermore, since
+ this header file is freestanding, it has to be independent of
+ config.h, and so the following conditionalisation cannot depend on
+ configure time checks.
+
+ Although it's not clear from
+ 'defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)',
+ this expression excludes Darwin.
+ .cfi directives in Darwin assembly appear to be completely
+ different and I haven't investigated how they work.
+
+ For even more entertainment value, note we have to use the
+ completely undocumented __builtin_dwarf_cfa(), which appears to
+ really compute the CFA, whereas __builtin_frame_address(0) claims
+ to but actually doesn't. See
+ https://bugs.kde.org/show_bug.cgi?id=243270#c47
+*/
+#if defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)
+# define __FRAME_POINTER \
+ ,"r"(__builtin_dwarf_cfa())
+# define VALGRIND_CFI_PROLOGUE \
+ "movq %%rbp, %%r15\n\t" \
+ "movq %2, %%rbp\n\t" \
+ ".cfi_remember_state\n\t" \
+ ".cfi_def_cfa rbp, 0\n\t"
+# define VALGRIND_CFI_EPILOGUE \
+ "movq %%r15, %%rbp\n\t" \
+ ".cfi_restore_state\n\t"
+#else
+# define __FRAME_POINTER
+# define VALGRIND_CFI_PROLOGUE
+# define VALGRIND_CFI_EPILOGUE
+#endif
+
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+#define VALGRIND_ALIGN_STACK \
+ "movq %%rsp,%%r14\n\t" \
+ "andq $0xfffffffffffffff0,%%rsp\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "movq %%r14,%%rsp\n\t"
+
+/* These CALL_FN_ macros assume that on amd64-linux, sizeof(unsigned
+ long) == 8. */
+
+/* NB 9 Sept 07. There is a nasty kludge here in all these CALL_FN_
+ macros. In order not to trash the stack redzone, we need to drop
+ %rsp by 128 before the hidden call, and restore afterwards. The
+ nastyness is that it is only by luck that the stack still appears
+ to be unwindable during the hidden call - since then the behaviour
+ of any routine using this macro does not match what the CFI data
+ says. Sigh.
+
+ Why is this important? Imagine that a wrapper has a stack
+ allocated local, and passes to the hidden call, a pointer to it.
+ Because gcc does not know about the hidden call, it may allocate
+ that local in the redzone. Unfortunately the hidden call may then
+ trash it before it comes to use it. So we must step clear of the
+ redzone, for the duration of the hidden call, to make it safe.
+
+ Probably the same problem afflicts the other redzone-style ABIs too
+ (ppc64-linux); but for those, the stack is
+ self describing (none of this CFI nonsense) so at least messing
+ with the stack pointer doesn't give a danger of non-unwindable
+ stack. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $136,%%rsp\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $136,%%rsp\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "pushq 80(%%rax)\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $136,%%rsp\n\t" \
+ "pushq 88(%%rax)\n\t" \
+ "pushq 80(%%rax)\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "pushq 96(%%rax)\n\t" \
+ "pushq 88(%%rax)\n\t" \
+ "pushq 80(%%rax)\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_amd64_linux || PLAT_amd64_darwin || PLAT_amd64_solaris */
+
+/* ------------------------ ppc32-linux ------------------------ */
+
+#if defined(PLAT_ppc32_linux)
+
+/* This is useful for finding out about the on-stack stuff:
+
+ extern int f9 ( int,int,int,int,int,int,int,int,int );
+ extern int f10 ( int,int,int,int,int,int,int,int,int,int );
+ extern int f11 ( int,int,int,int,int,int,int,int,int,int,int );
+ extern int f12 ( int,int,int,int,int,int,int,int,int,int,int,int );
+
+ int g9 ( void ) {
+ return f9(11,22,33,44,55,66,77,88,99);
+ }
+ int g10 ( void ) {
+ return f10(11,22,33,44,55,66,77,88,99,110);
+ }
+ int g11 ( void ) {
+ return f11(11,22,33,44,55,66,77,88,99,110,121);
+ }
+ int g12 ( void ) {
+ return f12(11,22,33,44,55,66,77,88,99,110,121,132);
+ }
+*/
+
+/* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS \
+ "lr", "ctr", "xer", \
+ "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
+ "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+ "r11", "r12", "r13"
+
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+#define VALGRIND_ALIGN_STACK \
+ "mr 28,1\n\t" \
+ "rlwinm 1,1,0,0,27\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "mr 1,28\n\t"
+
+/* These CALL_FN_ macros assume that on ppc32-linux,
+ sizeof(unsigned long) == 4. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "addi 1,1,-16\n\t" \
+ /* arg9 */ \
+ "lwz 3,36(11)\n\t" \
+ "stw 3,8(1)\n\t" \
+ /* args1-8 */ \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "addi 1,1,-16\n\t" \
+ /* arg10 */ \
+ "lwz 3,40(11)\n\t" \
+ "stw 3,12(1)\n\t" \
+ /* arg9 */ \
+ "lwz 3,36(11)\n\t" \
+ "stw 3,8(1)\n\t" \
+ /* args1-8 */ \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ _argvec[11] = (unsigned long)arg11; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "addi 1,1,-32\n\t" \
+ /* arg11 */ \
+ "lwz 3,44(11)\n\t" \
+ "stw 3,16(1)\n\t" \
+ /* arg10 */ \
+ "lwz 3,40(11)\n\t" \
+ "stw 3,12(1)\n\t" \
+ /* arg9 */ \
+ "lwz 3,36(11)\n\t" \
+ "stw 3,8(1)\n\t" \
+ /* args1-8 */ \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ _argvec[11] = (unsigned long)arg11; \
+ _argvec[12] = (unsigned long)arg12; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "addi 1,1,-32\n\t" \
+ /* arg12 */ \
+ "lwz 3,48(11)\n\t" \
+ "stw 3,20(1)\n\t" \
+ /* arg11 */ \
+ "lwz 3,44(11)\n\t" \
+ "stw 3,16(1)\n\t" \
+ /* arg10 */ \
+ "lwz 3,40(11)\n\t" \
+ "stw 3,12(1)\n\t" \
+ /* arg9 */ \
+ "lwz 3,36(11)\n\t" \
+ "stw 3,8(1)\n\t" \
+ /* args1-8 */ \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_ppc32_linux */
+
+/* ------------------------ ppc64-linux ------------------------ */
+
+#if defined(PLAT_ppc64be_linux)
+
+/* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS \
+ "lr", "ctr", "xer", \
+ "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
+ "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+ "r11", "r12", "r13"
+
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+#define VALGRIND_ALIGN_STACK \
+ "mr 28,1\n\t" \
+ "rldicr 1,1,0,59\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "mr 1,28\n\t"
+
+/* These CALL_FN_ macros assume that on ppc64-linux, sizeof(unsigned
+ long) == 8. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+0]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+1]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+2]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+3]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+4]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+5]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+6]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+7]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+8]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+9]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-128\n\t" /* expand stack frame */ \
+ /* arg9 */ \
+ "ld 3,72(11)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+10]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ _argvec[2+10] = (unsigned long)arg10; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-128\n\t" /* expand stack frame */ \
+ /* arg10 */ \
+ "ld 3,80(11)\n\t" \
+ "std 3,120(1)\n\t" \
+ /* arg9 */ \
+ "ld 3,72(11)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+11]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ _argvec[2+10] = (unsigned long)arg10; \
+ _argvec[2+11] = (unsigned long)arg11; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-144\n\t" /* expand stack frame */ \
+ /* arg11 */ \
+ "ld 3,88(11)\n\t" \
+ "std 3,128(1)\n\t" \
+ /* arg10 */ \
+ "ld 3,80(11)\n\t" \
+ "std 3,120(1)\n\t" \
+ /* arg9 */ \
+ "ld 3,72(11)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+12]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ _argvec[2+10] = (unsigned long)arg10; \
+ _argvec[2+11] = (unsigned long)arg11; \
+ _argvec[2+12] = (unsigned long)arg12; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-144\n\t" /* expand stack frame */ \
+ /* arg12 */ \
+ "ld 3,96(11)\n\t" \
+ "std 3,136(1)\n\t" \
+ /* arg11 */ \
+ "ld 3,88(11)\n\t" \
+ "std 3,128(1)\n\t" \
+ /* arg10 */ \
+ "ld 3,80(11)\n\t" \
+ "std 3,120(1)\n\t" \
+ /* arg9 */ \
+ "ld 3,72(11)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_ppc64be_linux */
+
+/* ------------------------- ppc64le-linux ----------------------- */
+#if defined(PLAT_ppc64le_linux)
+
+/* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS \
+ "lr", "ctr", "xer", \
+ "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
+ "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+ "r11", "r12", "r13"
+
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+#define VALGRIND_ALIGN_STACK \
+ "mr 28,1\n\t" \
+ "rldicr 1,1,0,59\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "mr 1,28\n\t"
+
+/* These CALL_FN_ macros assume that on ppc64-linux, sizeof(unsigned
+ long) == 8. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+0]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+1]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+2]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+3]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+4]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+5]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+6]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+7]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+8]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+9]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-128\n\t" /* expand stack frame */ \
+ /* arg9 */ \
+ "ld 3,72(12)\n\t" \
+ "std 3,96(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+10]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ _argvec[2+10] = (unsigned long)arg10; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-128\n\t" /* expand stack frame */ \
+ /* arg10 */ \
+ "ld 3,80(12)\n\t" \
+ "std 3,104(1)\n\t" \
+ /* arg9 */ \
+ "ld 3,72(12)\n\t" \
+ "std 3,96(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+11]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ _argvec[2+10] = (unsigned long)arg10; \
+ _argvec[2+11] = (unsigned long)arg11; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-144\n\t" /* expand stack frame */ \
+ /* arg11 */ \
+ "ld 3,88(12)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* arg10 */ \
+ "ld 3,80(12)\n\t" \
+ "std 3,104(1)\n\t" \
+ /* arg9 */ \
+ "ld 3,72(12)\n\t" \
+ "std 3,96(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+12]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ _argvec[2+10] = (unsigned long)arg10; \
+ _argvec[2+11] = (unsigned long)arg11; \
+ _argvec[2+12] = (unsigned long)arg12; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "mr 12,%1\n\t" \
+ "std 2,-16(12)\n\t" /* save tocptr */ \
+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-144\n\t" /* expand stack frame */ \
+ /* arg12 */ \
+ "ld 3,96(12)\n\t" \
+ "std 3,120(1)\n\t" \
+ /* arg11 */ \
+ "ld 3,88(12)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* arg10 */ \
+ "ld 3,80(12)\n\t" \
+ "std 3,104(1)\n\t" \
+ /* arg9 */ \
+ "ld 3,72(12)\n\t" \
+ "std 3,96(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
+ "ld 12, 0(12)\n\t" /* target->r12 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
+ "mr 12,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(12)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_ppc64le_linux */
+
+/* ------------------------- arm-linux ------------------------- */
+
+#if defined(PLAT_arm_linux)
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS "r0", "r1", "r2", "r3","r4", "r12", "r14"
+
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+/* This is a bit tricky. We store the original stack pointer in r10
+ as it is callee-saves. gcc doesn't allow the use of r11 for some
+ reason. Also, we can't directly "bic" the stack pointer in thumb
+ mode since r13 isn't an allowed register number in that context.
+ So use r4 as a temporary, since that is about to get trashed
+ anyway, just after each use of this macro. Side effect is we need
+ to be very careful about any future changes, since
+ VALGRIND_ALIGN_STACK simply assumes r4 is usable. */
+#define VALGRIND_ALIGN_STACK \
+ "mov r10, sp\n\t" \
+ "mov r4, sp\n\t" \
+ "bic r4, r4, #7\n\t" \
+ "mov sp, r4\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "mov sp, r10\n\t"
+
+/* These CALL_FN_ macros assume that on arm-linux, sizeof(unsigned
+ long) == 4. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #4 \n\t" \
+ "ldr r0, [%1, #20] \n\t" \
+ "push {r0} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "push {r0, r1} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #4 \n\t" \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "push {r0, r1, r2} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "push {r0, r1, r2, r3} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #4 \n\t" \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "ldr r4, [%1, #36] \n\t" \
+ "push {r0, r1, r2, r3, r4} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr r0, [%1, #40] \n\t" \
+ "push {r0} \n\t" \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "ldr r4, [%1, #36] \n\t" \
+ "push {r0, r1, r2, r3, r4} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #4 \n\t" \
+ "ldr r0, [%1, #40] \n\t" \
+ "ldr r1, [%1, #44] \n\t" \
+ "push {r0, r1} \n\t" \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "ldr r4, [%1, #36] \n\t" \
+ "push {r0, r1, r2, r3, r4} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr r0, [%1, #40] \n\t" \
+ "ldr r1, [%1, #44] \n\t" \
+ "ldr r2, [%1, #48] \n\t" \
+ "push {r0, r1, r2} \n\t" \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "ldr r4, [%1, #36] \n\t" \
+ "push {r0, r1, r2, r3, r4} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_arm_linux */
+
+/* ------------------------ arm64-linux ------------------------ */
+
+#if defined(PLAT_arm64_linux)
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS \
+ "x0", "x1", "x2", "x3","x4", "x5", "x6", "x7", "x8", "x9", \
+ "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", \
+ "x18", "x19", "x20", "x30", \
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", \
+ "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", \
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", \
+ "v26", "v27", "v28", "v29", "v30", "v31"
+
+/* x21 is callee-saved, so we can use it to save and restore SP around
+ the hidden call. */
+#define VALGRIND_ALIGN_STACK \
+ "mov x21, sp\n\t" \
+ "bic sp, x21, #15\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "mov sp, x21\n\t"
+
+/* These CALL_FN_ macros assume that on arm64-linux,
+ sizeof(unsigned long) == 8. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x3, [%1, #32] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x3, [%1, #32] \n\t" \
+ "ldr x4, [%1, #40] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x3, [%1, #32] \n\t" \
+ "ldr x4, [%1, #40] \n\t" \
+ "ldr x5, [%1, #48] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x3, [%1, #32] \n\t" \
+ "ldr x4, [%1, #40] \n\t" \
+ "ldr x5, [%1, #48] \n\t" \
+ "ldr x6, [%1, #56] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x3, [%1, #32] \n\t" \
+ "ldr x4, [%1, #40] \n\t" \
+ "ldr x5, [%1, #48] \n\t" \
+ "ldr x6, [%1, #56] \n\t" \
+ "ldr x7, [%1, #64] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #0x20 \n\t" \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x3, [%1, #32] \n\t" \
+ "ldr x4, [%1, #40] \n\t" \
+ "ldr x5, [%1, #48] \n\t" \
+ "ldr x6, [%1, #56] \n\t" \
+ "ldr x7, [%1, #64] \n\t" \
+ "ldr x8, [%1, #72] \n\t" \
+ "str x8, [sp, #0] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #0x20 \n\t" \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x3, [%1, #32] \n\t" \
+ "ldr x4, [%1, #40] \n\t" \
+ "ldr x5, [%1, #48] \n\t" \
+ "ldr x6, [%1, #56] \n\t" \
+ "ldr x7, [%1, #64] \n\t" \
+ "ldr x8, [%1, #72] \n\t" \
+ "str x8, [sp, #0] \n\t" \
+ "ldr x8, [%1, #80] \n\t" \
+ "str x8, [sp, #8] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #0x30 \n\t" \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x3, [%1, #32] \n\t" \
+ "ldr x4, [%1, #40] \n\t" \
+ "ldr x5, [%1, #48] \n\t" \
+ "ldr x6, [%1, #56] \n\t" \
+ "ldr x7, [%1, #64] \n\t" \
+ "ldr x8, [%1, #72] \n\t" \
+ "str x8, [sp, #0] \n\t" \
+ "ldr x8, [%1, #80] \n\t" \
+ "str x8, [sp, #8] \n\t" \
+ "ldr x8, [%1, #88] \n\t" \
+ "str x8, [sp, #16] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11, \
+ arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #0x30 \n\t" \
+ "ldr x0, [%1, #8] \n\t" \
+ "ldr x1, [%1, #16] \n\t" \
+ "ldr x2, [%1, #24] \n\t" \
+ "ldr x3, [%1, #32] \n\t" \
+ "ldr x4, [%1, #40] \n\t" \
+ "ldr x5, [%1, #48] \n\t" \
+ "ldr x6, [%1, #56] \n\t" \
+ "ldr x7, [%1, #64] \n\t" \
+ "ldr x8, [%1, #72] \n\t" \
+ "str x8, [sp, #0] \n\t" \
+ "ldr x8, [%1, #80] \n\t" \
+ "str x8, [sp, #8] \n\t" \
+ "ldr x8, [%1, #88] \n\t" \
+ "str x8, [sp, #16] \n\t" \
+ "ldr x8, [%1, #96] \n\t" \
+ "str x8, [sp, #24] \n\t" \
+ "ldr x8, [%1] \n\t" /* target->x8 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \
+ VALGRIND_RESTORE_STACK \
+ "mov %0, x0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_arm64_linux */
+
+/* ------------------------- s390x-linux ------------------------- */
+
+#if defined(PLAT_s390x_linux)
+
+/* Similar workaround as amd64 (see above), but we use r11 as frame
+ pointer and save the old r11 in r7. r11 might be used for
+ argvec, therefore we copy argvec in r1 since r1 is clobbered
+ after the call anyway. */
+#if defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)
+# define __FRAME_POINTER \
+ ,"d"(__builtin_dwarf_cfa())
+# define VALGRIND_CFI_PROLOGUE \
+ ".cfi_remember_state\n\t" \
+ "lgr 1,%1\n\t" /* copy the argvec pointer in r1 */ \
+ "lgr 7,11\n\t" \
+ "lgr 11,%2\n\t" \
+ ".cfi_def_cfa r11, 0\n\t"
+# define VALGRIND_CFI_EPILOGUE \
+ "lgr 11, 7\n\t" \
+ ".cfi_restore_state\n\t"
+#else
+# define __FRAME_POINTER
+# define VALGRIND_CFI_PROLOGUE \
+ "lgr 1,%1\n\t"
+# define VALGRIND_CFI_EPILOGUE
+#endif
+
+/* Nb: On s390 the stack pointer is properly aligned *at all times*
+ according to the s390 GCC maintainer. (The ABI specification is not
+ precise in this regard.) Therefore, VALGRIND_ALIGN_STACK and
+ VALGRIND_RESTORE_STACK are not defined here. */
+
+/* These regs are trashed by the hidden call. Note that we overwrite
+ r14 in s390_irgen_noredir (VEX/priv/guest_s390_irgen.c) to give the
+ function a proper return address. All others are ABI defined call
+ clobbers. */
+#if defined(__VX__) || defined(__S390_VX__)
+#define __CALLER_SAVED_REGS "0", "1", "2", "3", "4", "5", "14", \
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
+#else
+#define __CALLER_SAVED_REGS "0", "1", "2", "3", "4", "5", "14", \
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7"
+#endif
+
+/* Nb: Although r11 is modified in the asm snippets below (inside
+ VALGRIND_CFI_PROLOGUE) it is not listed in the clobber section, for
+ two reasons:
+ (1) r11 is restored in VALGRIND_CFI_EPILOGUE, so effectively it is not
+ modified
+ (2) GCC will complain that r11 cannot appear inside a clobber section,
+ when compiled with -O -fno-omit-frame-pointer
+ */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 1, 0(1)\n\t" /* target->r1 */ \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "d" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+/* The call abi has the arguments in r2-r6 and stack */
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1, arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1, arg2, arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1, arg2, arg3, arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1, arg2, arg3, arg4, arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-168\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,168\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-176\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,176\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-184\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,184\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8, arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-192\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "mvc 184(8,15), 72(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,192\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8, arg9, arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-200\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "mvc 184(8,15), 72(1)\n\t" \
+ "mvc 192(8,15), 80(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,200\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8, arg9, arg10, arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ _argvec[11] = (unsigned long)arg11; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-208\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "mvc 184(8,15), 72(1)\n\t" \
+ "mvc 192(8,15), 80(1)\n\t" \
+ "mvc 200(8,15), 88(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,208\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8, arg9, arg10, arg11, arg12)\
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ _argvec[11] = (unsigned long)arg11; \
+ _argvec[12] = (unsigned long)arg12; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-216\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "mvc 184(8,15), 72(1)\n\t" \
+ "mvc 192(8,15), 80(1)\n\t" \
+ "mvc 200(8,15), 88(1)\n\t" \
+ "mvc 208(8,15), 96(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "aghi 15,216\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ "lgr %0, 2\n\t" \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+
+#endif /* PLAT_s390x_linux */
+
+/* ------------------------- mips32-linux ----------------------- */
+
+#if defined(PLAT_mips32_linux)
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS "$2", "$3", "$4", "$5", "$6", \
+"$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+"$25", "$31"
+
+/* These CALL_FN_ macros assume that on mips-linux, sizeof(unsigned
+ long) == 4. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16\n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $4, 4(%1) \n\t" /* arg1*/ \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $7, 16(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "lw $4, 20(%1) \n\t" \
+ "subu $29, $29, 24\n\t" \
+ "sw $4, 16($29) \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $7, 16(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 24 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "lw $4, 20(%1) \n\t" \
+ "subu $29, $29, 32\n\t" \
+ "sw $4, 16($29) \n\t" \
+ "lw $4, 24(%1) \n\t" \
+ "nop\n\t" \
+ "sw $4, 20($29) \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $7, 16(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 32 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "lw $4, 20(%1) \n\t" \
+ "subu $29, $29, 32\n\t" \
+ "sw $4, 16($29) \n\t" \
+ "lw $4, 24(%1) \n\t" \
+ "sw $4, 20($29) \n\t" \
+ "lw $4, 28(%1) \n\t" \
+ "sw $4, 24($29) \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $7, 16(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 32 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "lw $4, 20(%1) \n\t" \
+ "subu $29, $29, 40\n\t" \
+ "sw $4, 16($29) \n\t" \
+ "lw $4, 24(%1) \n\t" \
+ "sw $4, 20($29) \n\t" \
+ "lw $4, 28(%1) \n\t" \
+ "sw $4, 24($29) \n\t" \
+ "lw $4, 32(%1) \n\t" \
+ "sw $4, 28($29) \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $7, 16(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 40 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "lw $4, 20(%1) \n\t" \
+ "subu $29, $29, 40\n\t" \
+ "sw $4, 16($29) \n\t" \
+ "lw $4, 24(%1) \n\t" \
+ "sw $4, 20($29) \n\t" \
+ "lw $4, 28(%1) \n\t" \
+ "sw $4, 24($29) \n\t" \
+ "lw $4, 32(%1) \n\t" \
+ "sw $4, 28($29) \n\t" \
+ "lw $4, 36(%1) \n\t" \
+ "sw $4, 32($29) \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $7, 16(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 40 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "lw $4, 20(%1) \n\t" \
+ "subu $29, $29, 48\n\t" \
+ "sw $4, 16($29) \n\t" \
+ "lw $4, 24(%1) \n\t" \
+ "sw $4, 20($29) \n\t" \
+ "lw $4, 28(%1) \n\t" \
+ "sw $4, 24($29) \n\t" \
+ "lw $4, 32(%1) \n\t" \
+ "sw $4, 28($29) \n\t" \
+ "lw $4, 36(%1) \n\t" \
+ "sw $4, 32($29) \n\t" \
+ "lw $4, 40(%1) \n\t" \
+ "sw $4, 36($29) \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $7, 16(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 48 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "lw $4, 20(%1) \n\t" \
+ "subu $29, $29, 48\n\t" \
+ "sw $4, 16($29) \n\t" \
+ "lw $4, 24(%1) \n\t" \
+ "sw $4, 20($29) \n\t" \
+ "lw $4, 28(%1) \n\t" \
+ "sw $4, 24($29) \n\t" \
+ "lw $4, 32(%1) \n\t" \
+ "sw $4, 28($29) \n\t" \
+ "lw $4, 36(%1) \n\t" \
+ "sw $4, 32($29) \n\t" \
+ "lw $4, 40(%1) \n\t" \
+ "sw $4, 36($29) \n\t" \
+ "lw $4, 44(%1) \n\t" \
+ "sw $4, 40($29) \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $7, 16(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 48 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $28, 0($29) \n\t" \
+ "sw $31, 4($29) \n\t" \
+ "lw $4, 20(%1) \n\t" \
+ "subu $29, $29, 56\n\t" \
+ "sw $4, 16($29) \n\t" \
+ "lw $4, 24(%1) \n\t" \
+ "sw $4, 20($29) \n\t" \
+ "lw $4, 28(%1) \n\t" \
+ "sw $4, 24($29) \n\t" \
+ "lw $4, 32(%1) \n\t" \
+ "sw $4, 28($29) \n\t" \
+ "lw $4, 36(%1) \n\t" \
+ "sw $4, 32($29) \n\t" \
+ "lw $4, 40(%1) \n\t" \
+ "sw $4, 36($29) \n\t" \
+ "lw $4, 44(%1) \n\t" \
+ "sw $4, 40($29) \n\t" \
+ "lw $4, 48(%1) \n\t" \
+ "sw $4, 44($29) \n\t" \
+ "lw $4, 4(%1) \n\t" \
+ "lw $5, 8(%1) \n\t" \
+ "lw $6, 12(%1) \n\t" \
+ "lw $7, 16(%1) \n\t" \
+ "lw $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 56 \n\t" \
+ "lw $28, 0($29) \n\t" \
+ "lw $31, 4($29) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_mips32_linux */
+
+/* ------------------------- nanomips-linux -------------------- */
+
+#if defined(PLAT_nanomips_linux)
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS "$t4", "$t5", "$a0", "$a1", "$a2", \
+"$a3", "$a4", "$a5", "$a6", "$a7", "$t0", "$t1", "$t2", "$t3", \
+"$t8","$t9", "$at"
+
+/* These CALL_FN_ macros assume that on mips-linux, sizeof(unsigned
+ long) == 4. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ "lw $t9, 0(%1)\n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ "lw $t9, 0(%1)\n\t" \
+ "lw $a0, 4(%1)\n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ "lw $t9, 0(%1)\n\t" \
+ "lw $a0, 4(%1)\n\t" \
+ "lw $a1, 8(%1)\n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ "lw $t9, 0(%1)\n\t" \
+ "lw $a0, 4(%1)\n\t" \
+ "lw $a1, 8(%1)\n\t" \
+ "lw $a2,12(%1)\n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ "lw $t9, 0(%1)\n\t" \
+ "lw $a0, 4(%1)\n\t" \
+ "lw $a1, 8(%1)\n\t" \
+ "lw $a2,12(%1)\n\t" \
+ "lw $a3,16(%1)\n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ "lw $t9, 0(%1)\n\t" \
+ "lw $a0, 4(%1)\n\t" \
+ "lw $a1, 8(%1)\n\t" \
+ "lw $a2,12(%1)\n\t" \
+ "lw $a3,16(%1)\n\t" \
+ "lw $a4,20(%1)\n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ "lw $t9, 0(%1)\n\t" \
+ "lw $a0, 4(%1)\n\t" \
+ "lw $a1, 8(%1)\n\t" \
+ "lw $a2,12(%1)\n\t" \
+ "lw $a3,16(%1)\n\t" \
+ "lw $a4,20(%1)\n\t" \
+ "lw $a5,24(%1)\n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ "lw $t9, 0(%1)\n\t" \
+ "lw $a0, 4(%1)\n\t" \
+ "lw $a1, 8(%1)\n\t" \
+ "lw $a2,12(%1)\n\t" \
+ "lw $a3,16(%1)\n\t" \
+ "lw $a4,20(%1)\n\t" \
+ "lw $a5,24(%1)\n\t" \
+ "lw $a6,28(%1)\n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ "lw $t9, 0(%1)\n\t" \
+ "lw $a0, 4(%1)\n\t" \
+ "lw $a1, 8(%1)\n\t" \
+ "lw $a2,12(%1)\n\t" \
+ "lw $a3,16(%1)\n\t" \
+ "lw $a4,20(%1)\n\t" \
+ "lw $a5,24(%1)\n\t" \
+ "lw $a6,28(%1)\n\t" \
+ "lw $a7,32(%1)\n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ "addiu $sp, $sp, -16 \n\t" \
+ "lw $t9,36(%1) \n\t" \
+ "sw $t9, 0($sp) \n\t" \
+ "lw $t9, 0(%1) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2,12(%1) \n\t" \
+ "lw $a3,16(%1) \n\t" \
+ "lw $a4,20(%1) \n\t" \
+ "lw $a5,24(%1) \n\t" \
+ "lw $a6,28(%1) \n\t" \
+ "lw $a7,32(%1) \n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0 \n\t" \
+ "addiu $sp, $sp, 16 \n\t" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ "addiu $sp, $sp, -16 \n\t" \
+ "lw $t9,36(%1) \n\t" \
+ "sw $t9, 0($sp) \n\t" \
+ "lw $t9,40(%1) \n\t" \
+ "sw $t9, 4($sp) \n\t" \
+ "lw $t9, 0(%1) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2,12(%1) \n\t" \
+ "lw $a3,16(%1) \n\t" \
+ "lw $a4,20(%1) \n\t" \
+ "lw $a5,24(%1) \n\t" \
+ "lw $a6,28(%1) \n\t" \
+ "lw $a7,32(%1) \n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0 \n\t" \
+ "addiu $sp, $sp, 16 \n\t" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ "addiu $sp, $sp, -16 \n\t" \
+ "lw $t9,36(%1) \n\t" \
+ "sw $t9, 0($sp) \n\t" \
+ "lw $t9,40(%1) \n\t" \
+ "sw $t9, 4($sp) \n\t" \
+ "lw $t9,44(%1) \n\t" \
+ "sw $t9, 8($sp) \n\t" \
+ "lw $t9, 0(%1) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2,12(%1) \n\t" \
+ "lw $a3,16(%1) \n\t" \
+ "lw $a4,20(%1) \n\t" \
+ "lw $a5,24(%1) \n\t" \
+ "lw $a6,28(%1) \n\t" \
+ "lw $a7,32(%1) \n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0 \n\t" \
+ "addiu $sp, $sp, 16 \n\t" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ "addiu $sp, $sp, -16 \n\t" \
+ "lw $t9,36(%1) \n\t" \
+ "sw $t9, 0($sp) \n\t" \
+ "lw $t9,40(%1) \n\t" \
+ "sw $t9, 4($sp) \n\t" \
+ "lw $t9,44(%1) \n\t" \
+ "sw $t9, 8($sp) \n\t" \
+ "lw $t9,48(%1) \n\t" \
+ "sw $t9,12($sp) \n\t" \
+ "lw $t9, 0(%1) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2,12(%1) \n\t" \
+ "lw $a3,16(%1) \n\t" \
+ "lw $a4,20(%1) \n\t" \
+ "lw $a5,24(%1) \n\t" \
+ "lw $a6,28(%1) \n\t" \
+ "lw $a7,32(%1) \n\t" \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $a0 \n\t" \
+ "addiu $sp, $sp, 16 \n\t" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_nanomips_linux */
+
+/* ------------------------- mips64-linux ------------------------- */
+
+#if defined(PLAT_mips64_linux)
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS "$2", "$3", "$4", "$5", "$6", \
+"$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+"$25", "$31"
+
+/* These CALL_FN_ macros assume that on mips64-linux,
+ sizeof(long long) == 8. */
+
+#define MIPS64_LONG2REG_CAST(x) ((long long)(long)x)
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[1]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ __asm__ volatile( \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[2]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ __asm__ volatile( \
+ "ld $4, 8(%1)\n\t" /* arg1*/ \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[3]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = _orig.nraddr; \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ __asm__ volatile( \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[4]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = _orig.nraddr; \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ __asm__ volatile( \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[5]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ _argvec[4] = MIPS64_LONG2REG_CAST(arg4); \
+ __asm__ volatile( \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $7, 32(%1)\n\t" \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[6]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ _argvec[4] = MIPS64_LONG2REG_CAST(arg4); \
+ _argvec[5] = MIPS64_LONG2REG_CAST(arg5); \
+ __asm__ volatile( \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $7, 32(%1)\n\t" \
+ "ld $8, 40(%1)\n\t" \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[7]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ _argvec[4] = MIPS64_LONG2REG_CAST(arg4); \
+ _argvec[5] = MIPS64_LONG2REG_CAST(arg5); \
+ _argvec[6] = MIPS64_LONG2REG_CAST(arg6); \
+ __asm__ volatile( \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $7, 32(%1)\n\t" \
+ "ld $8, 40(%1)\n\t" \
+ "ld $9, 48(%1)\n\t" \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[8]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ _argvec[4] = MIPS64_LONG2REG_CAST(arg4); \
+ _argvec[5] = MIPS64_LONG2REG_CAST(arg5); \
+ _argvec[6] = MIPS64_LONG2REG_CAST(arg6); \
+ _argvec[7] = MIPS64_LONG2REG_CAST(arg7); \
+ __asm__ volatile( \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $7, 32(%1)\n\t" \
+ "ld $8, 40(%1)\n\t" \
+ "ld $9, 48(%1)\n\t" \
+ "ld $10, 56(%1)\n\t" \
+ "ld $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[9]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ _argvec[4] = MIPS64_LONG2REG_CAST(arg4); \
+ _argvec[5] = MIPS64_LONG2REG_CAST(arg5); \
+ _argvec[6] = MIPS64_LONG2REG_CAST(arg6); \
+ _argvec[7] = MIPS64_LONG2REG_CAST(arg7); \
+ _argvec[8] = MIPS64_LONG2REG_CAST(arg8); \
+ __asm__ volatile( \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $7, 32(%1)\n\t" \
+ "ld $8, 40(%1)\n\t" \
+ "ld $9, 48(%1)\n\t" \
+ "ld $10, 56(%1)\n\t" \
+ "ld $11, 64(%1)\n\t" \
+ "ld $25, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[10]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ _argvec[4] = MIPS64_LONG2REG_CAST(arg4); \
+ _argvec[5] = MIPS64_LONG2REG_CAST(arg5); \
+ _argvec[6] = MIPS64_LONG2REG_CAST(arg6); \
+ _argvec[7] = MIPS64_LONG2REG_CAST(arg7); \
+ _argvec[8] = MIPS64_LONG2REG_CAST(arg8); \
+ _argvec[9] = MIPS64_LONG2REG_CAST(arg9); \
+ __asm__ volatile( \
+ "dsubu $29, $29, 8\n\t" \
+ "ld $4, 72(%1)\n\t" \
+ "sd $4, 0($29)\n\t" \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $7, 32(%1)\n\t" \
+ "ld $8, 40(%1)\n\t" \
+ "ld $9, 48(%1)\n\t" \
+ "ld $10, 56(%1)\n\t" \
+ "ld $11, 64(%1)\n\t" \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "daddu $29, $29, 8\n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[11]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ _argvec[4] = MIPS64_LONG2REG_CAST(arg4); \
+ _argvec[5] = MIPS64_LONG2REG_CAST(arg5); \
+ _argvec[6] = MIPS64_LONG2REG_CAST(arg6); \
+ _argvec[7] = MIPS64_LONG2REG_CAST(arg7); \
+ _argvec[8] = MIPS64_LONG2REG_CAST(arg8); \
+ _argvec[9] = MIPS64_LONG2REG_CAST(arg9); \
+ _argvec[10] = MIPS64_LONG2REG_CAST(arg10); \
+ __asm__ volatile( \
+ "dsubu $29, $29, 16\n\t" \
+ "ld $4, 72(%1)\n\t" \
+ "sd $4, 0($29)\n\t" \
+ "ld $4, 80(%1)\n\t" \
+ "sd $4, 8($29)\n\t" \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $7, 32(%1)\n\t" \
+ "ld $8, 40(%1)\n\t" \
+ "ld $9, 48(%1)\n\t" \
+ "ld $10, 56(%1)\n\t" \
+ "ld $11, 64(%1)\n\t" \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "daddu $29, $29, 16\n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[12]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ _argvec[4] = MIPS64_LONG2REG_CAST(arg4); \
+ _argvec[5] = MIPS64_LONG2REG_CAST(arg5); \
+ _argvec[6] = MIPS64_LONG2REG_CAST(arg6); \
+ _argvec[7] = MIPS64_LONG2REG_CAST(arg7); \
+ _argvec[8] = MIPS64_LONG2REG_CAST(arg8); \
+ _argvec[9] = MIPS64_LONG2REG_CAST(arg9); \
+ _argvec[10] = MIPS64_LONG2REG_CAST(arg10); \
+ _argvec[11] = MIPS64_LONG2REG_CAST(arg11); \
+ __asm__ volatile( \
+ "dsubu $29, $29, 24\n\t" \
+ "ld $4, 72(%1)\n\t" \
+ "sd $4, 0($29)\n\t" \
+ "ld $4, 80(%1)\n\t" \
+ "sd $4, 8($29)\n\t" \
+ "ld $4, 88(%1)\n\t" \
+ "sd $4, 16($29)\n\t" \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $7, 32(%1)\n\t" \
+ "ld $8, 40(%1)\n\t" \
+ "ld $9, 48(%1)\n\t" \
+ "ld $10, 56(%1)\n\t" \
+ "ld $11, 64(%1)\n\t" \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "daddu $29, $29, 24\n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long long _argvec[13]; \
+ volatile unsigned long long _res; \
+ _argvec[0] = MIPS64_LONG2REG_CAST(_orig.nraddr); \
+ _argvec[1] = MIPS64_LONG2REG_CAST(arg1); \
+ _argvec[2] = MIPS64_LONG2REG_CAST(arg2); \
+ _argvec[3] = MIPS64_LONG2REG_CAST(arg3); \
+ _argvec[4] = MIPS64_LONG2REG_CAST(arg4); \
+ _argvec[5] = MIPS64_LONG2REG_CAST(arg5); \
+ _argvec[6] = MIPS64_LONG2REG_CAST(arg6); \
+ _argvec[7] = MIPS64_LONG2REG_CAST(arg7); \
+ _argvec[8] = MIPS64_LONG2REG_CAST(arg8); \
+ _argvec[9] = MIPS64_LONG2REG_CAST(arg9); \
+ _argvec[10] = MIPS64_LONG2REG_CAST(arg10); \
+ _argvec[11] = MIPS64_LONG2REG_CAST(arg11); \
+ _argvec[12] = MIPS64_LONG2REG_CAST(arg12); \
+ __asm__ volatile( \
+ "dsubu $29, $29, 32\n\t" \
+ "ld $4, 72(%1)\n\t" \
+ "sd $4, 0($29)\n\t" \
+ "ld $4, 80(%1)\n\t" \
+ "sd $4, 8($29)\n\t" \
+ "ld $4, 88(%1)\n\t" \
+ "sd $4, 16($29)\n\t" \
+ "ld $4, 96(%1)\n\t" \
+ "sd $4, 24($29)\n\t" \
+ "ld $4, 8(%1)\n\t" \
+ "ld $5, 16(%1)\n\t" \
+ "ld $6, 24(%1)\n\t" \
+ "ld $7, 32(%1)\n\t" \
+ "ld $8, 40(%1)\n\t" \
+ "ld $9, 48(%1)\n\t" \
+ "ld $10, 56(%1)\n\t" \
+ "ld $11, 64(%1)\n\t" \
+ "ld $25, 0(%1)\n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "daddu $29, $29, 32\n\t" \
+ "move %0, $2\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) (long)_res; \
+ } while (0)
+
+#endif /* PLAT_mips64_linux */
+
+/* ------------------------------------------------------------------ */
+/* ARCHITECTURE INDEPENDENT MACROS for CLIENT REQUESTS. */
+/* */
+/* ------------------------------------------------------------------ */
+
+/* Some request codes. There are many more of these, but most are not
+ exposed to end-user view. These are the public ones, all of the
+ form 0x1000 + small_number.
+
+ Core ones are in the range 0x00000000--0x0000ffff. The non-public
+ ones start at 0x2000.
+*/
+
+/* These macros are used by tools -- they must be public, but don't
+ embed them into other programs. */
+#define VG_USERREQ_TOOL_BASE(a,b) \
+ ((unsigned int)(((a)&0xff) << 24 | ((b)&0xff) << 16))
+#define VG_IS_TOOL_USERREQ(a, b, v) \
+ (VG_USERREQ_TOOL_BASE(a,b) == ((v) & 0xffff0000))
+
+/* !! ABIWARNING !! ABIWARNING !! ABIWARNING !! ABIWARNING !!
+ This enum comprises an ABI exported by Valgrind to programs
+ which use client requests. DO NOT CHANGE THE NUMERIC VALUES OF THESE
+ ENTRIES, NOR DELETE ANY -- add new ones at the end of the most
+ relevant group. */
+typedef
+ enum { VG_USERREQ__RUNNING_ON_VALGRIND = 0x1001,
+ VG_USERREQ__DISCARD_TRANSLATIONS = 0x1002,
+
+ /* These allow any function to be called from the simulated
+ CPU but run on the real CPU. Nb: the first arg passed to
+ the function is always the ThreadId of the running
+ thread! So CLIENT_CALL0 actually requires a 1 arg
+ function, etc. */
+ VG_USERREQ__CLIENT_CALL0 = 0x1101,
+ VG_USERREQ__CLIENT_CALL1 = 0x1102,
+ VG_USERREQ__CLIENT_CALL2 = 0x1103,
+ VG_USERREQ__CLIENT_CALL3 = 0x1104,
+
+ /* Can be useful in regression testing suites -- eg. can
+ send Valgrind's output to /dev/null and still count
+ errors. */
+ VG_USERREQ__COUNT_ERRORS = 0x1201,
+
+ /* Allows the client program and/or gdbserver to execute a monitor
+ command. */
+ VG_USERREQ__GDB_MONITOR_COMMAND = 0x1202,
+
+ /* Allows the client program to change a dynamic command line
+ option. */
+ VG_USERREQ__CLO_CHANGE = 0x1203,
+
+ /* These are useful and can be interpreted by any tool that
+ tracks malloc() et al, by using vg_replace_malloc.c. */
+ VG_USERREQ__MALLOCLIKE_BLOCK = 0x1301,
+ VG_USERREQ__RESIZEINPLACE_BLOCK = 0x130b,
+ VG_USERREQ__FREELIKE_BLOCK = 0x1302,
+ /* Memory pool support. */
+ VG_USERREQ__CREATE_MEMPOOL = 0x1303,
+ VG_USERREQ__DESTROY_MEMPOOL = 0x1304,
+ VG_USERREQ__MEMPOOL_ALLOC = 0x1305,
+ VG_USERREQ__MEMPOOL_FREE = 0x1306,
+ VG_USERREQ__MEMPOOL_TRIM = 0x1307,
+ VG_USERREQ__MOVE_MEMPOOL = 0x1308,
+ VG_USERREQ__MEMPOOL_CHANGE = 0x1309,
+ VG_USERREQ__MEMPOOL_EXISTS = 0x130a,
+
+ /* Allow printfs to valgrind log. */
+ /* The first two pass the va_list argument by value, which
+ assumes it is the same size as or smaller than a UWord,
+ which generally isn't the case. Hence are deprecated.
+ The second two pass the vargs by reference and so are
+ immune to this problem. */
+ /* both :: char* fmt, va_list vargs (DEPRECATED) */
+ VG_USERREQ__PRINTF = 0x1401,
+ VG_USERREQ__PRINTF_BACKTRACE = 0x1402,
+ /* both :: char* fmt, va_list* vargs */
+ VG_USERREQ__PRINTF_VALIST_BY_REF = 0x1403,
+ VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF = 0x1404,
+
+ /* Stack support. */
+ VG_USERREQ__STACK_REGISTER = 0x1501,
+ VG_USERREQ__STACK_DEREGISTER = 0x1502,
+ VG_USERREQ__STACK_CHANGE = 0x1503,
+
+ /* Wine support */
+ VG_USERREQ__LOAD_PDB_DEBUGINFO = 0x1601,
+
+ /* Querying of debug info. */
+ VG_USERREQ__MAP_IP_TO_SRCLOC = 0x1701,
+
+ /* Disable/enable error reporting level. Takes a single
+ Word arg which is the delta to this thread's error
+ disablement indicator. Hence 1 disables or further
+ disables errors, and -1 moves back towards enablement.
+ Other values are not allowed. */
+ VG_USERREQ__CHANGE_ERR_DISABLEMENT = 0x1801,
+
+ /* Some requests used for Valgrind internal, such as
+ self-test or self-hosting. */
+ /* Initialise IR injection */
+ VG_USERREQ__VEX_INIT_FOR_IRI = 0x1901,
+ /* Used by Inner Valgrind to inform Outer Valgrind where to
+ find the list of inner guest threads */
+ VG_USERREQ__INNER_THREADS = 0x1902
+ } Vg_ClientRequest;
+
+#if !defined(__GNUC__)
+# define __extension__ /* */
+#endif
+
+
+/* Returns the number of Valgrinds this code is running under. That
+ is, 0 if running natively, 1 if running under Valgrind, 2 if
+ running under Valgrind which is running under another Valgrind,
+ etc. */
+#define RUNNING_ON_VALGRIND \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* if not */, \
+ VG_USERREQ__RUNNING_ON_VALGRIND, \
+ 0, 0, 0, 0, 0) \
+
+
+/* Discard translation of code in the range [_qzz_addr .. _qzz_addr +
+ _qzz_len - 1]. Useful if you are debugging a JITter or some such,
+ since it provides a way to make sure valgrind will retranslate the
+ invalidated area. Returns no value. */
+#define VALGRIND_DISCARD_TRANSLATIONS(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DISCARD_TRANSLATIONS, \
+ _qzz_addr, _qzz_len, 0, 0, 0)
+
+#define VALGRIND_INNER_THREADS(_qzz_addr) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__INNER_THREADS, \
+ _qzz_addr, 0, 0, 0, 0)
+
+
+/* These requests are for getting Valgrind itself to print something.
+ Possibly with a backtrace. This is a really ugly hack. The return value
+ is the number of characters printed, excluding the "**<pid>** " part at the
+ start and the backtrace (if present). */
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER) && !defined(_MSC_VER)
+/* Modern GCC will optimize the static routine out if unused,
+ and unused attribute will shut down warnings about it. */
+static int VALGRIND_PRINTF(const char *format, ...)
+ __attribute__((format(__printf__, 1, 2), __unused__));
+#endif
+static int
+#if defined(_MSC_VER)
+__inline
+#endif
+VALGRIND_PRINTF(const char *format, ...)
+{
+#if !IS_ENABLED(CONFIG_VALGRIND)
+ (void)format;
+ return 0;
+#else /* CONFIG_VALGRIND */
+#if defined(_MSC_VER) || defined(__MINGW64__)
+ uintptr_t _qzz_res;
+#else
+ unsigned long _qzz_res;
+#endif
+ va_list vargs;
+ va_start(vargs, format);
+#if defined(_MSC_VER) || defined(__MINGW64__)
+ _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+ VG_USERREQ__PRINTF_VALIST_BY_REF,
+ (uintptr_t)format,
+ (uintptr_t)&vargs,
+ 0, 0, 0);
+#else
+ _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+ VG_USERREQ__PRINTF_VALIST_BY_REF,
+ (unsigned long)format,
+ (unsigned long)&vargs,
+ 0, 0, 0);
+#endif
+ va_end(vargs);
+ return (int)_qzz_res;
+#endif /* CONFIG_VALGRIND */
+}
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER) && !defined(_MSC_VER)
+static int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+ __attribute__((format(__printf__, 1, 2), __unused__));
+#endif
+static int
+#if defined(_MSC_VER)
+__inline
+#endif
+VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+{
+#if !IS_ENABLED(CONFIG_VALGRIND)
+ (void)format;
+ return 0;
+#else /* CONFIG_VALGRIND */
+#if defined(_MSC_VER) || defined(__MINGW64__)
+ uintptr_t _qzz_res;
+#else
+ unsigned long _qzz_res;
+#endif
+ va_list vargs;
+ va_start(vargs, format);
+#if defined(_MSC_VER) || defined(__MINGW64__)
+ _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+ VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF,
+ (uintptr_t)format,
+ (uintptr_t)&vargs,
+ 0, 0, 0);
+#else
+ _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+ VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF,
+ (unsigned long)format,
+ (unsigned long)&vargs,
+ 0, 0, 0);
+#endif
+ va_end(vargs);
+ return (int)_qzz_res;
+#endif /* CONFIG_VALGRIND */
+}
+
+
+/* These requests allow control to move from the simulated CPU to the
+ real CPU, calling an arbitrary function.
+
+ Note that the current ThreadId is inserted as the first argument.
+ So this call:
+
+ VALGRIND_NON_SIMD_CALL2(f, arg1, arg2)
+
+ requires f to have this signature:
+
+ Word f(Word tid, Word arg1, Word arg2)
+
+ where "Word" is a word-sized type.
+
+ Note that these client requests are not entirely reliable. For example,
+ if you call a function with them that subsequently calls printf(),
+ there's a high chance Valgrind will crash. Generally, your prospects of
+ these working are made higher if the called function does not refer to
+ any global variables, and does not refer to any libc or other functions
+ (printf et al). Any kind of entanglement with libc or dynamic linking is
+ likely to have a bad outcome, for tricky reasons which we've grappled
+ with a lot in the past.
+*/
+#define VALGRIND_NON_SIMD_CALL0(_qyy_fn) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__CLIENT_CALL0, \
+ _qyy_fn, \
+ 0, 0, 0, 0)
+
+#define VALGRIND_NON_SIMD_CALL1(_qyy_fn, _qyy_arg1) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__CLIENT_CALL1, \
+ _qyy_fn, \
+ _qyy_arg1, 0, 0, 0)
+
+#define VALGRIND_NON_SIMD_CALL2(_qyy_fn, _qyy_arg1, _qyy_arg2) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__CLIENT_CALL2, \
+ _qyy_fn, \
+ _qyy_arg1, _qyy_arg2, 0, 0)
+
+#define VALGRIND_NON_SIMD_CALL3(_qyy_fn, _qyy_arg1, _qyy_arg2, _qyy_arg3) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__CLIENT_CALL3, \
+ _qyy_fn, \
+ _qyy_arg1, _qyy_arg2, \
+ _qyy_arg3, 0)
+
+
+/* Counts the number of errors that have been recorded by a tool. Nb:
+ the tool must record the errors with VG_(maybe_record_error)() or
+ VG_(unique_error)() for them to be counted. */
+#define VALGRIND_COUNT_ERRORS \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ 0 /* default return */, \
+ VG_USERREQ__COUNT_ERRORS, \
+ 0, 0, 0, 0, 0)
+
+/* Several Valgrind tools (Memcheck, Massif, Helgrind, DRD) rely on knowing
+ when heap blocks are allocated in order to give accurate results. This
+ happens automatically for the standard allocator functions such as
+ malloc(), calloc(), realloc(), memalign(), new, new[], free(), delete,
+ delete[], etc.
+
+ But if your program uses a custom allocator, this doesn't automatically
+ happen, and Valgrind will not do as well. For example, if you allocate
+ superblocks with mmap() and then allocates chunks of the superblocks, all
+ Valgrind's observations will be at the mmap() level and it won't know that
+ the chunks should be considered separate entities. In Memcheck's case,
+ that means you probably won't get heap block overrun detection (because
+ there won't be redzones marked as unaddressable) and you definitely won't
+ get any leak detection.
+
+ The following client requests allow a custom allocator to be annotated so
+ that it can be handled accurately by Valgrind.
+
+ VALGRIND_MALLOCLIKE_BLOCK marks a region of memory as having been allocated
+ by a malloc()-like function. For Memcheck (an illustrative case), this
+ does two things:
+
+ - It records that the block has been allocated. This means any addresses
+ within the block mentioned in error messages will be
+ identified as belonging to the block. It also means that if the block
+ isn't freed it will be detected by the leak checker.
+
+ - It marks the block as being addressable and undefined (if 'is_zeroed' is
+ not set), or addressable and defined (if 'is_zeroed' is set). This
+ controls how accesses to the block by the program are handled.
+
+ 'addr' is the start of the usable block (ie. after any
+ redzone), 'sizeB' is its size. 'rzB' is the redzone size if the allocator
+ can apply redzones -- these are blocks of padding at the start and end of
+ each block. Adding redzones is recommended as it makes it much more likely
+ Valgrind will spot block overruns. `is_zeroed' indicates if the memory is
+ zeroed (or filled with another predictable value), as is the case for
+ calloc().
+
+ VALGRIND_MALLOCLIKE_BLOCK should be put immediately after the point where a
+ heap block -- that will be used by the client program -- is allocated.
+ It's best to put it at the outermost level of the allocator if possible;
+ for example, if you have a function my_alloc() which calls
+ internal_alloc(), and the client request is put inside internal_alloc(),
+ stack traces relating to the heap block will contain entries for both
+ my_alloc() and internal_alloc(), which is probably not what you want.
+
+ For Memcheck users: if you use VALGRIND_MALLOCLIKE_BLOCK to carve out
+ custom blocks from within a heap block, B, that has been allocated with
+ malloc/calloc/new/etc, then block B will be *ignored* during leak-checking
+ -- the custom blocks will take precedence.
+
+ VALGRIND_FREELIKE_BLOCK is the partner to VALGRIND_MALLOCLIKE_BLOCK. For
+ Memcheck, it does two things:
+
+ - It records that the block has been deallocated. This assumes that the
+ block was annotated as having been allocated via
+ VALGRIND_MALLOCLIKE_BLOCK. Otherwise, an error will be issued.
+
+ - It marks the block as being unaddressable.
+
+ VALGRIND_FREELIKE_BLOCK should be put immediately after the point where a
+ heap block is deallocated.
+
+ VALGRIND_RESIZEINPLACE_BLOCK informs a tool about reallocation. For
+ Memcheck, it does four things:
+
+ - It records that the size of a block has been changed. This assumes that
+ the block was annotated as having been allocated via
+ VALGRIND_MALLOCLIKE_BLOCK. Otherwise, an error will be issued.
+
+ - If the block shrunk, it marks the freed memory as being unaddressable.
+
+ - If the block grew, it marks the new area as undefined and defines a red
+ zone past the end of the new block.
+
+ - The V-bits of the overlap between the old and the new block are preserved.
+
+ VALGRIND_RESIZEINPLACE_BLOCK should be put after allocation of the new block
+ and before deallocation of the old block.
+
+ In many cases, these three client requests will not be enough to get your
+ allocator working well with Memcheck. More specifically, if your allocator
+ writes to freed blocks in any way then a VALGRIND_MAKE_MEM_UNDEFINED call
+ will be necessary to mark the memory as addressable just before the zeroing
+ occurs, otherwise you'll get a lot of invalid write errors. For example,
+ you'll need to do this if your allocator recycles freed blocks, but it
+ zeroes them before handing them back out (via VALGRIND_MALLOCLIKE_BLOCK).
+ Alternatively, if your allocator reuses freed blocks for allocator-internal
+ data structures, VALGRIND_MAKE_MEM_UNDEFINED calls will also be necessary.
+
+ Really, what's happening is a blurring of the lines between the client
+ program and the allocator... after VALGRIND_FREELIKE_BLOCK is called, the
+ memory should be considered unaddressable to the client program, but the
+ allocator knows more than the rest of the client program and so may be able
+ to safely access it. Extra client requests are necessary for Valgrind to
+ understand the distinction between the allocator and the rest of the
+ program.
+
+ Ignored if addr == 0.
+*/
+#define VALGRIND_MALLOCLIKE_BLOCK(addr, sizeB, rzB, is_zeroed) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MALLOCLIKE_BLOCK, \
+ addr, sizeB, rzB, is_zeroed, 0)
+
+/* See the comment for VALGRIND_MALLOCLIKE_BLOCK for details.
+ Ignored if addr == 0.
+*/
+#define VALGRIND_RESIZEINPLACE_BLOCK(addr, oldSizeB, newSizeB, rzB) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__RESIZEINPLACE_BLOCK, \
+ addr, oldSizeB, newSizeB, rzB, 0)
+
+/* See the comment for VALGRIND_MALLOCLIKE_BLOCK for details.
+ Ignored if addr == 0.
+*/
+#define VALGRIND_FREELIKE_BLOCK(addr, rzB) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__FREELIKE_BLOCK, \
+ addr, rzB, 0, 0, 0)
+
+/* Create a memory pool. */
+#define VALGRIND_CREATE_MEMPOOL(pool, rzB, is_zeroed) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CREATE_MEMPOOL, \
+ pool, rzB, is_zeroed, 0, 0)
+
+/* Create a memory pool with some flags specifying extended behaviour.
+ When flags is zero, the behaviour is identical to VALGRIND_CREATE_MEMPOOL.
+
+ The flag VALGRIND_MEMPOOL_METAPOOL specifies that the pieces of memory
+ associated with the pool using VALGRIND_MEMPOOL_ALLOC will be used
+ by the application as superblocks to dole out MALLOC_LIKE blocks using
+ VALGRIND_MALLOCLIKE_BLOCK. In other words, a meta pool is a "2 levels"
+ pool : first level is the blocks described by VALGRIND_MEMPOOL_ALLOC.
+ The second level blocks are described using VALGRIND_MALLOCLIKE_BLOCK.
+ Note that the association between the pool and the second level blocks
+ is implicit : second level blocks will be located inside first level
+ blocks. It is necessary to use the VALGRIND_MEMPOOL_METAPOOL flag
+ for such 2 levels pools, as otherwise valgrind will detect overlapping
+ memory blocks, and will abort execution (e.g. during leak search).
+
+ Such a meta pool can also be marked as an 'auto free' pool using the flag
+ VALGRIND_MEMPOOL_AUTO_FREE, which must be OR-ed together with the
+ VALGRIND_MEMPOOL_METAPOOL. For an 'auto free' pool, VALGRIND_MEMPOOL_FREE
+ will automatically free the second level blocks that are contained
+ inside the first level block freed with VALGRIND_MEMPOOL_FREE.
+ In other words, calling VALGRIND_MEMPOOL_FREE will cause implicit calls
+ to VALGRIND_FREELIKE_BLOCK for all the second level blocks included
+ in the first level block.
+ Note: it is an error to use the VALGRIND_MEMPOOL_AUTO_FREE flag
+ without the VALGRIND_MEMPOOL_METAPOOL flag.
+*/
+#define VALGRIND_MEMPOOL_AUTO_FREE 1
+#define VALGRIND_MEMPOOL_METAPOOL 2
+#define VALGRIND_CREATE_MEMPOOL_EXT(pool, rzB, is_zeroed, flags) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CREATE_MEMPOOL, \
+ pool, rzB, is_zeroed, flags, 0)
+
+/* Destroy a memory pool. */
+#define VALGRIND_DESTROY_MEMPOOL(pool) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DESTROY_MEMPOOL, \
+ pool, 0, 0, 0, 0)
+
+/* Associate a piece of memory with a memory pool. */
+#define VALGRIND_MEMPOOL_ALLOC(pool, addr, size) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_ALLOC, \
+ pool, addr, size, 0, 0)
+
+/* Disassociate a piece of memory from a memory pool. */
+#define VALGRIND_MEMPOOL_FREE(pool, addr) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_FREE, \
+ pool, addr, 0, 0, 0)
+
+/* Disassociate any pieces outside a particular range. */
+#define VALGRIND_MEMPOOL_TRIM(pool, addr, size) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_TRIM, \
+ pool, addr, size, 0, 0)
+
+/* Resize and/or move a piece associated with a memory pool. */
+#define VALGRIND_MOVE_MEMPOOL(poolA, poolB) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MOVE_MEMPOOL, \
+ poolA, poolB, 0, 0, 0)
+
+/* Resize and/or move a piece associated with a memory pool. */
+#define VALGRIND_MEMPOOL_CHANGE(pool, addrA, addrB, size) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_CHANGE, \
+ pool, addrA, addrB, size, 0)
+
+/* Return 1 if a mempool exists, else 0. */
+#define VALGRIND_MEMPOOL_EXISTS(pool) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__MEMPOOL_EXISTS, \
+ pool, 0, 0, 0, 0)
+
+/* Mark a piece of memory as being a stack. Returns a stack id.
+ start is the lowest addressable stack byte, end is the highest
+ addressable stack byte. */
+#define VALGRIND_STACK_REGISTER(start, end) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__STACK_REGISTER, \
+ start, end, 0, 0, 0)
+
+/* Unmark the piece of memory associated with a stack id as being a
+ stack. */
+#define VALGRIND_STACK_DEREGISTER(id) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__STACK_DEREGISTER, \
+ id, 0, 0, 0, 0)
+
+/* Change the start and end address of the stack id.
+ start is the new lowest addressable stack byte, end is the new highest
+ addressable stack byte. */
+#define VALGRIND_STACK_CHANGE(id, start, end) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__STACK_CHANGE, \
+ id, start, end, 0, 0)
+
+/* Load PDB debug info for Wine PE image_map. */
+#define VALGRIND_LOAD_PDB_DEBUGINFO(fd, ptr, total_size, delta) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__LOAD_PDB_DEBUGINFO, \
+ fd, ptr, total_size, delta, 0)
+
+/* Map a code address to a source file name and line number. buf64
+ must point to a 64-byte buffer in the caller's address space. The
+ result will be dumped in there and is guaranteed to be zero
+ terminated. If no info is found, the first byte is set to zero. */
+#define VALGRIND_MAP_IP_TO_SRCLOC(addr, buf64) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__MAP_IP_TO_SRCLOC, \
+ addr, buf64, 0, 0, 0)
+
+/* Disable error reporting for this thread. Behaves in a stack like
+ way, so you can safely call this multiple times provided that
+ VALGRIND_ENABLE_ERROR_REPORTING is called the same number of times
+ to re-enable reporting. The first call of this macro disables
+ reporting. Subsequent calls have no effect except to increase the
+ number of VALGRIND_ENABLE_ERROR_REPORTING calls needed to re-enable
+ reporting. Child threads do not inherit this setting from their
+ parents -- they are always created with reporting enabled. */
+#define VALGRIND_DISABLE_ERROR_REPORTING \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CHANGE_ERR_DISABLEMENT, \
+ 1, 0, 0, 0, 0)
+
+/* Re-enable error reporting, as per comments on
+ VALGRIND_DISABLE_ERROR_REPORTING. */
+#define VALGRIND_ENABLE_ERROR_REPORTING \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CHANGE_ERR_DISABLEMENT, \
+ -1, 0, 0, 0, 0)
+
+/* Execute a monitor command from the client program.
+ If a connection is opened with GDB, the output will be sent
+ according to the output mode set for vgdb.
+ If no connection is opened, output will go to the log output.
+ Returns 1 if command not recognised, 0 otherwise. */
+#define VALGRIND_MONITOR_COMMAND(command) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__GDB_MONITOR_COMMAND, \
+ command, 0, 0, 0, 0)
+
+
+/* Change the value of a dynamic command line option.
+ Note that unknown or not dynamically changeable options
+ will cause a warning message to be output. */
+#define VALGRIND_CLO_CHANGE(option) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CLO_CHANGE, \
+ option, 0, 0, 0, 0)
+
+
+#undef PLAT_x86_darwin
+#undef PLAT_amd64_darwin
+#undef PLAT_x86_win32
+#undef PLAT_amd64_win64
+#undef PLAT_x86_linux
+#undef PLAT_amd64_linux
+#undef PLAT_ppc32_linux
+#undef PLAT_ppc64be_linux
+#undef PLAT_ppc64le_linux
+#undef PLAT_arm_linux
+#undef PLAT_s390x_linux
+#undef PLAT_mips32_linux
+#undef PLAT_mips64_linux
+#undef PLAT_nanomips_linux
+#undef PLAT_x86_solaris
+#undef PLAT_amd64_solaris
+
+#endif /* __VALGRIND_H */
SD_CONFIG_FIXED = 4, /* To set fixed config registers */
};
+enum pm_gem_config_type {
+ GEM_CONFIG_SGMII_MODE = 1, /* To set GEM_SGMII_MODE in GEM_CLK_CTRL */
+ GEM_CONFIG_FIXED = 2, /* To set fixed config registers */
+};
+
#define PM_SIP_SVC 0xc2000000
#define ZYNQMP_PM_VERSION_MAJOR 1
int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload);
int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
+int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
+ u32 value);
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
/* Type of Config Object */
/* not currently allocated and new size is larger. Alloc and
* copy in data. The new space is not inited.
*/
- ptr = memdup(abuf->data, new_size);
+ ptr = malloc(new_size);
if (!ptr)
return false;
+ if (abuf->size)
+ memcpy(ptr, abuf->data, abuf->size);
abuf->data = ptr;
abuf->size = new_size;
abuf->alloced = true;
menuconfig ASYMMETRIC_KEY_TYPE
bool "Asymmetric (public-key cryptographic) key Support"
+ depends on FIT_SIGNATURE
help
This option provides support for a key type that holds the data for
the asymmetric keys used for public key cryptographic operations such
return -ENOPKG;
if (!strcmp(sinfo->sig->hash_algo, "sha256"))
sig->digest_size = SHA256_SUM_LEN;
+ else if (!strcmp(sinfo->sig->hash_algo, "sha384"))
+ sig->digest_size = SHA384_SUM_LEN;
+ else if (!strcmp(sinfo->sig->hash_algo, "sha512"))
+ sig->digest_size = SHA512_SUM_LEN;
else if (!strcmp(sinfo->sig->hash_algo, "sha1"))
sig->digest_size = SHA1_SUM_LEN;
else
return -ENOPKG;
if (!strcmp(sig->hash_algo, "sha256"))
sig->digest_size = SHA256_SUM_LEN;
+ else if (!strcmp(sig->hash_algo, "sha384"))
+ sig->digest_size = SHA384_SUM_LEN;
+ else if (!strcmp(sig->hash_algo, "sha512"))
+ sig->digest_size = SHA512_SUM_LEN;
else if (!strcmp(sig->hash_algo, "sha1"))
sig->digest_size = SHA1_SUM_LEN;
else
variable related operations to that. The application will verify,
authenticate and store the variables on an RPMB.
+config EFI_VARIABLE_NO_STORE
+ bool "Don't persist non-volatile UEFI variables"
+ help
+ If you choose this option, non-volatile variables cannot be persisted.
+ You could still provide non-volatile variables via
+ EFI_VARIABLES_PRESEED.
+
endchoice
config EFI_VARIABLES_PRESEED
bool "Initial values for UEFI variables"
- depends on EFI_VARIABLE_FILE_STORE
+ depends on !EFI_MM_COMM_TEE
help
Include a file with the initial values for non-volatile UEFI variables
into the U-Boot binary. If this configuration option is set, changes
config EFI_CAPSULE_ON_DISK
bool "Enable capsule-on-disk support"
+ depends on SYSRESET
select EFI_HAVE_CAPSULE_SUPPORT
help
Select this option if you want to use capsule-on-disk feature,
CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI)
CFLAGS_dtbdump.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_dtbdump.o := $(CFLAGS_NON_EFI)
-CFLAGS_initrddump_exit.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_initrddump.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_initrddump.o := $(CFLAGS_NON_EFI)
ifneq ($(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
#include <malloc.h>
#include <mapmem.h>
#include <sort.h>
+#include <sysreset.h>
#include <asm/global_data.h>
#include <crypto/pkcs7.h>
return EFI_EXIT(ret);
}
+/**
+ * efi_load_capsule_drivers - initialize capsule drivers
+ *
+ * Generic FMP drivers backed by DFU
+ *
+ * Return: status code
+ */
+efi_status_t __weak efi_load_capsule_drivers(void)
+{
+ __maybe_unused efi_handle_t handle;
+ efi_status_t ret = EFI_SUCCESS;
+
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_FIT)) {
+ handle = NULL;
+ ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
+ &handle, &efi_guid_firmware_management_protocol,
+ &efi_fmp_fit, NULL));
+ }
+
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) {
+ handle = NULL;
+ ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
+ &handle,
+ &efi_guid_firmware_management_protocol,
+ &efi_fmp_raw, NULL));
+ }
+
+ return ret;
+}
+
#ifdef CONFIG_EFI_CAPSULE_ON_DISK
/**
* get_dp_device - retrieve a device path from boot variable
bootdev_root = NULL;
}
-/**
- * efi_load_capsule_drivers - initialize capsule drivers
- *
- * Generic FMP drivers backed by DFU
- *
- * Return: status code
- */
-efi_status_t __weak efi_load_capsule_drivers(void)
-{
- __maybe_unused efi_handle_t handle;
- efi_status_t ret = EFI_SUCCESS;
-
- if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_FIT)) {
- handle = NULL;
- ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
- &handle, &efi_guid_firmware_management_protocol,
- &efi_fmp_fit, NULL));
- }
-
- if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) {
- handle = NULL;
- ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
- &handle,
- &efi_guid_firmware_management_protocol,
- &efi_fmp_raw, NULL));
- }
-
- return ret;
-}
-
/**
* check_run_capsules() - check whether capsule update should run
*
* UEFI spec requires to reset system after complete processing capsule
* update on the storage.
*/
- log_info("Reboot after firmware update");
+ log_info("Reboot after firmware update.\n");
/* Cold reset is required for loading the new firmware. */
- do_reset(NULL, 0, 0, NULL);
+ sysreset_walk_halt(SYSRESET_COLD);
hang();
/* not reach here */
{
void *fdt_blob = NULL;
+ if (IS_ENABLED(CONFIG_SANDBOX))
+ return NULL;
+
#ifdef CONFIG_SPL_BUILD
/* FDT is at end of BSS unless it is in a different memory region */
- if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
+ if (CONFIG_IS_ENABLED(SEPARATE_BSS))
fdt_blob = (ulong *)&_image_binary_end;
else
fdt_blob = (ulong *)&__bss_end;
static void *SzAlloc(void *p, size_t size) { return malloc(size); }
static void SzFree(void *p, void *address) { free(address); }
-int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
- unsigned char *inStream, SizeT length)
+int lzmaBuffToBuffDecompress(unsigned char *outStream, SizeT *uncompressedSize,
+ const unsigned char *inStream, SizeT length)
{
int res = SZ_ERROR_DATA;
int i;
#include <lzma/LzmaTypes.h>
-extern int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
- unsigned char *inStream, SizeT length);
+/**
+ * lzmaBuffToBuffDecompress() - Decompress LZMA data
+ *
+ * @outStream: output buffer
+ * @uncompressedSize: On entry, the mnaximum uncompressed size of the data;
+ * on exit, the actual uncompressed size after processing
+ * @inStream: Compressed bytes to decompress
+ * @length: Sizeof @inStream
+ * @return 0 if OK, SZ_ERROR_DATA if the data is in a format that cannot be
+ * decompressed; SZ_ERROR_OUTPUT_EOF if *uncompressedSize is too small;
+ * see also other SZ_ERROR... values
+ */
+int lzmaBuffToBuffDecompress(unsigned char *outStream, SizeT *uncompressedSize,
+ const unsigned char *inStream, SizeT length);
+
#endif
}
int padding_pkcs_15_verify(struct image_sign_info *info,
- uint8_t *msg, int msg_len,
+ const uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len)
{
struct checksum_algo *checksum = info->checksum;
* Return: 0 if the octet string was correctly generated, others on error
*/
static int mask_generation_function1(struct checksum_algo *checksum,
- uint8_t *seed, int seed_len,
+ const uint8_t *seed, int seed_len,
uint8_t *output, int output_len)
{
struct image_region region[2];
}
static int compute_hash_prime(struct checksum_algo *checksum,
- uint8_t *pad, int pad_len,
- uint8_t *hash, int hash_len,
- uint8_t *salt, int salt_len,
+ const uint8_t *pad, int pad_len,
+ const uint8_t *hash, int hash_len,
+ const uint8_t *salt, int salt_len,
uint8_t *hprime)
{
struct image_region region[3];
/*
* padding_pss_verify() - verify the pss padding of a signature
*
- * Only works with a rsa_pss_saltlen:-2 (default value) right now
- * saltlen:-1 "set the salt length to the digest length" is currently
- * not supported.
+ * Works with any salt length
+ *
+ * msg is a concatenation of : masked_db + h + 0xbc
+ * Once unmasked, db is a concatenation of : [0x00]* + 0x01 + salt
+ * Length of 0-padding at begin of db depends on salt length.
*
* @info: Specifies key and FIT information
* @msg: byte array of message, len equal to msg_len
* @hash_len: Length of the hash
*/
int padding_pss_verify(struct image_sign_info *info,
- uint8_t *msg, int msg_len,
+ const uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len)
{
- uint8_t *masked_db = NULL;
- int masked_db_len = msg_len - hash_len - 1;
- uint8_t *h = NULL, *hprime = NULL;
- int h_len = hash_len;
+ const uint8_t *masked_db = NULL;
uint8_t *db_mask = NULL;
- int db_mask_len = masked_db_len;
- uint8_t *db = NULL, *salt = NULL;
- int db_len = masked_db_len, salt_len = msg_len - hash_len - 2;
+ uint8_t *db = NULL;
+ int db_len = msg_len - hash_len - 1;
+ const uint8_t *h = NULL;
+ uint8_t *hprime = NULL;
+ int h_len = hash_len;
+ uint8_t *db_nopad = NULL, *salt = NULL;
+ int db_padlen, salt_len;
uint8_t pad_zero[8] = { 0 };
int ret, i, leftmost_bits = 1;
uint8_t leftmost_mask;
struct checksum_algo *checksum = info->checksum;
/* first, allocate everything */
- masked_db = malloc(masked_db_len);
- h = malloc(h_len);
- db_mask = malloc(db_mask_len);
+ db_mask = malloc(db_len);
db = malloc(db_len);
- salt = malloc(salt_len);
hprime = malloc(hash_len);
- if (!masked_db || !h || !db_mask || !db || !salt || !hprime) {
+ if (!db_mask || !db || !hprime) {
printf("%s: can't allocate some buffer\n", __func__);
ret = -ENOMEM;
goto out;
}
/* step 5 */
- memcpy(masked_db, msg, masked_db_len);
- memcpy(h, msg + masked_db_len, h_len);
+ masked_db = &msg[0];
+ h = &msg[db_len];
/* step 6 */
leftmost_mask = (0xff >> (8 - leftmost_bits)) << (8 - leftmost_bits);
}
/* step 7 */
- mask_generation_function1(checksum, h, h_len, db_mask, db_mask_len);
+ mask_generation_function1(checksum, h, h_len, db_mask, db_len);
/* step 8 */
for (i = 0; i < db_len; i++)
db[0] &= 0xff >> leftmost_bits;
/* step 10 */
- if (db[0] != 0x01) {
+ db_padlen = 0;
+ while (db[db_padlen] == 0x00 && db_padlen < (db_len - 1))
+ db_padlen++;
+ db_nopad = &db[db_padlen];
+ if (db_nopad[0] != 0x01) {
printf("%s: invalid pss padding ", __func__);
- printf("(leftmost byte of db isn't 0x01)\n");
+ printf("(leftmost byte of db after 0-padding isn't 0x01)\n");
ret = EINVAL;
goto out;
}
/* step 11 */
- memcpy(salt, &db[1], salt_len);
+ salt_len = db_len - db_padlen - 1;
+ salt = &db_nopad[1];
/* step 12 & 13 */
compute_hash_prime(checksum, pad_zero, 8,
- (uint8_t *)hash, hash_len,
+ hash, hash_len,
salt, salt_len, hprime);
/* step 14 */
out:
free(hprime);
- free(salt);
free(db);
free(db_mask);
- free(h);
- free(masked_db);
return ret;
}
# Modified for U-Boot
dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \
+ $(UBOOTINCLUDE) \
-I$(srctree)/arch/$(ARCH)/dts \
-I$(srctree)/arch/$(ARCH)/dts/include \
- -Iinclude \
-I$(srctree)/include \
- -I$(srctree)/arch/$(ARCH)/include \
- -include $(srctree)/include/linux/kconfig.h \
-D__ASSEMBLY__ \
-undef -D__DTS__
$(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mkimage)
-MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \
+MKIMAGEFLAGS_sunxi-spl.bin = \
+ -A $(ARCH) \
+ -T $(CONFIG_SPL_IMAGE_TYPE) \
+ -a $(CONFIG_SPL_TEXT_BASE) \
-n $(CONFIG_DEFAULT_DEVICE_TREE)
OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE)
CONFIG_ARM_GIC_BASE_ADDRESS
CONFIG_AUTO_ZRELADDR
CONFIG_BOARDDIR
-CONFIG_BOARD_SIZE_LIMIT
-CONFIG_BOOTROM_ERR_REG
CONFIG_BOOTSCRIPT_ADDR
CONFIG_BOOTSCRIPT_COPY_RAM
CONFIG_BOOTSCRIPT_HDR_ADDR
CONFIG_BS_HDR_SIZE
CONFIG_BS_SIZE
CONFIG_CHAIN_BOOT_CMD
-CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
-CONFIG_CI_UDC_HAS_HOSTPC
-CONFIG_CM922T_XA10
-CONFIG_CMDLINE_PS_SUPPORT
-CONFIG_CM_INIT
-CONFIG_CM_MULTIPLE_SSRAM
-CONFIG_CM_REMAP
-CONFIG_CM_SPD_DETECT
-CONFIG_CM_TCRAM
-CONFIG_COMMON_BOOT
-CONFIG_CONS_SCIF0
-CONFIG_CONS_SCIF1
-CONFIG_CONS_SCIF2
-CONFIG_CONS_SCIF4
-CONFIG_CQSPI_REF_CLK
-CONFIG_CUSTOMER_BOARD_SUPPORT
-CONFIG_DCACHE
-CONFIG_DEBUG
-CONFIG_DEBUG_LED
CONFIG_DEFAULT
-CONFIG_DEFAULT_IMMR
-CONFIG_DESIGNWARE_ETH
CONFIG_DFU_ALT
CONFIG_DFU_ALT_BOOT_EMMC
CONFIG_DFU_ALT_BOOT_SD
CONFIG_DFU_ALT_SYSTEM
CONFIG_DFU_ENV_SETTINGS
-CONFIG_DIMM_SLOTS_PER_CTLR
-CONFIG_DISCOVER_PHY
CONFIG_DM9000_BASE
CONFIG_DM9000_BYTE_SWAPPED
CONFIG_DM9000_DEBUG
CONFIG_DM9000_NO_SROM
CONFIG_DM9000_USE_16BIT
-CONFIG_DMA_COHERENT
-CONFIG_DMA_COHERENT_SIZE
-CONFIG_DP_DDR_CTRL
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
-CONFIG_DP_DDR_NUM_CTRLS
-CONFIG_DRIVER_DM9000
CONFIG_DSP_CLUSTER_START
CONFIG_DWC_AHSATA_BASE_ADDR
CONFIG_DWC_AHSATA_PORT_ID
CONFIG_FSL_PMIC_CLK
CONFIG_FSL_PMIC_CS
CONFIG_FSL_PMIC_MODE
-CONFIG_FSL_QIXIS
CONFIG_FSL_SATA_V2
CONFIG_FSL_SDHC_V2_3
CONFIG_FSL_SERDES
CONFIG_GATEWAYIP
CONFIG_GLOBAL_TIMER
CONFIG_GMII
-CONFIG_GREEN_LED
CONFIG_G_DNL_THOR_PRODUCT_NUM
CONFIG_G_DNL_THOR_VENDOR_NUM
CONFIG_G_DNL_UMS_PRODUCT_NUM
CONFIG_I2C_MVTWSI_BASE0
CONFIG_I2C_MVTWSI_BASE1
CONFIG_I2C_RTC_ADDR
-CONFIG_ICACHE
CONFIG_ICS307_REFCLK_HZ
CONFIG_IDE_PREINIT
CONFIG_IMX
CONFIG_IRAM_STACK
CONFIG_IRAM_TOP
CONFIG_IRDA_BASE
-CONFIG_JRSTARTR_JR0
CONFIG_KEY_REVOCATION
CONFIG_KIRKWOOD_EGIGA_INIT
CONFIG_KIRKWOOD_PCIE_INIT
CONFIG_POWER_SPI
CONFIG_POWER_TPS62362
CONFIG_POWER_TPS65090_EC
-CONFIG_POWER_TPS65217
CONFIG_POWER_TPS65218
CONFIG_POWER_TPS65910
CONFIG_PPC_CLUSTER_START
CONFIG_PXA_STD_I2C
CONFIG_PXA_VGA
CONFIG_QBMAN_CLK_DIV
-CONFIG_QIXIS_I2C_ACCESS
CONFIG_RAMBOOT_NAND
CONFIG_RAMBOOT_SPIFLASH
CONFIG_RAMBOOT_TEXT_BASE
-CONFIG_RAMDISKFILE
CONFIG_RAMDISK_ADDR
-CONFIG_RAMDISK_BOOT
CONFIG_RD_LVL
-CONFIG_RED_LED
CONFIG_RESERVED_01_BASE
CONFIG_RESERVED_02_BASE
CONFIG_RESERVED_03_BASE
CONFIG_SH_ETHER_USE_PORT
CONFIG_SH_GPIO_PFC
CONFIG_SH_QSPI_BASE
-CONFIG_SH_SCIF_CLK_FREQ
CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
CONFIG_SKIP_TRUNOFF_WATCHDOG
CONFIG_SLIC
CONFIG_SYS_DPAA_FMAN
CONFIG_SYS_DPAA_PME
CONFIG_SYS_DPAA_RMAN
-CONFIG_SYS_DP_DDR_BASE
-CONFIG_SYS_DP_DDR_BASE_PHY
CONFIG_SYS_DRAM_BASE
CONFIG_SYS_DRAM_SIZE
CONFIG_SYS_DRAM_TEST
CONFIG_UBOOT_SECTOR_START
CONFIG_UEC_ETH
CONFIG_UEC_ETH2
-CONFIG_UPDATEB
CONFIG_USART_BASE
CONFIG_USART_ID
CONFIG_USBD_HS
if (do_output) {
printf("%s", "#define CONFIG_EXTRA_ENV_TEXT \"")
- # Print out all the variables
+ # Print out all the variables by alphabetic order, if using
+ # gawk. This allows test_env_test.py to work on both awk (where
+ # this next line does nothing)
+ PROCINFO["sorted_in"] = "@ind_str_asc"
for (var in vars) {
env = vars[var]
print var "=" vars[var] "\\0"
${OBJCOPY} --dump-section .rodata.default_environment=${ENV_OBJ_FILE_COPY} \
${env_obj_file_path}
-# Replace default '\0' with '\n' and sort entries
-tr '\0' '\n' < ${ENV_OBJ_FILE_COPY} | sort --field-separator== -k1,1 --stable
+# Replace default '\0' with '\n' , remove blank lines and sort entries
+tr '\0' '\n' < ${ENV_OBJ_FILE_COPY} | sed -e '/^\s*$/d' | sort --field-separator== -k1,1 --stable
rm ${ENV_OBJ_FILE_COPY}
--- /dev/null
+{
+ dlmalloc
+ Memcheck:Addr1
+ src:dlmalloc.c
+}
+{
+ dlmalloc
+ Memcheck:Addr4
+ src:dlmalloc.c
+}
+{
+ dlmalloc
+ Memcheck:Addr8
+ src:dlmalloc.c
+}
+{
+ dlmalloc
+ Memcheck:Addr1
+ fun:*
+ src:dlmalloc.c
+}
+{
+ dlmalloc
+ Memcheck:Addr4
+ fun:*
+ src:dlmalloc.c
+}
+{
+ dlmalloc
+ Memcheck:Addr8
+ fun:*
+ src:dlmalloc.c
+}
+{
+ dlmalloc
+ Memcheck:Value4
+ src:dlmalloc.c
+}
+{
+ dlmalloc
+ Memcheck:Value8
+ src:dlmalloc.c
+}
+{
+ dlmalloc
+ Memcheck:Cond
+ src:dlmalloc.c
+}
+{
+ dlmalloc
+ Memcheck:Free
+ src:dlmalloc.c
+}
/* Test that 'pinmux status <pinname>' displays the selected pin. */
console_record_reset();
run_command("pinmux status a5", 0);
- ut_assert_nextlinen("a5 : gpio input .");
+ ut_assert_nextlinen("a5 : gpio output .");
ut_assert_console_end();
console_record_reset();
return 0;
}
DM_TEST(dm_test_blk_iter, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test finding fixed/removable block devices */
+static int dm_test_blk_flags(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ /* Iterate through devices without probing them */
+ ut_assertok(blk_find_first(BLKF_BOTH, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc2.blk", dev->name);
+
+ ut_assertok(blk_find_next(BLKF_BOTH, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc1.blk", dev->name);
+
+ ut_assertok(blk_find_next(BLKF_BOTH, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc0.blk", dev->name);
+
+ ut_asserteq(-ENODEV, blk_find_next(BLKF_BOTH, &dev));
+ ut_assertnull(dev);
+
+ /* All devices are removable until probed */
+ ut_asserteq(-ENODEV, blk_find_first(BLKF_FIXED, &dev));
+
+ ut_assertok(blk_find_first(BLKF_REMOVABLE, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc2.blk", dev->name);
+
+ /* Now probe them and iterate again */
+ ut_assertok(blk_first_device_err(BLKF_BOTH, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc2.blk", dev->name);
+
+ ut_assertok(blk_next_device_err(BLKF_BOTH, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc1.blk", dev->name);
+
+ ut_assertok(blk_next_device_err(BLKF_BOTH, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc0.blk", dev->name);
+
+ ut_asserteq(-ENODEV, blk_next_device_err(BLKF_BOTH, &dev));
+
+ /* Look only for fixed devices */
+ ut_assertok(blk_first_device_err(BLKF_FIXED, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc2.blk", dev->name);
+
+ ut_asserteq(-ENODEV, blk_next_device_err(BLKF_FIXED, &dev));
+
+ /* Look only for removable devices */
+ ut_assertok(blk_first_device_err(BLKF_REMOVABLE, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc1.blk", dev->name);
+
+ ut_assertok(blk_next_device_err(BLKF_REMOVABLE, &dev));
+ ut_assertnonnull(dev);
+ ut_asserteq_str("mmc0.blk", dev->name);
+
+ ut_asserteq(-ENODEV, blk_next_device_err(BLKF_REMOVABLE, &dev));
+
+ return 0;
+}
+DM_TEST(dm_test_blk_flags, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test blk_foreach() and friend */
+static int dm_test_blk_foreach(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ int found;
+
+ /* Test blk_foreach() - use the 3rd bytes of the name (0/1/2) */
+ found = 0;
+ blk_foreach(BLKF_BOTH, dev)
+ found |= 1 << dectoul(&dev->name[3], NULL);
+ ut_asserteq(7, found);
+
+ /* All devices are removable until probed */
+ found = 0;
+ blk_foreach(BLKF_FIXED, dev)
+ found |= 1 << dectoul(&dev->name[3], NULL);
+ ut_asserteq(0, found);
+
+ found = 0;
+ blk_foreach(BLKF_REMOVABLE, dev)
+ found |= 1 << dectoul(&dev->name[3], NULL);
+ ut_asserteq(7, found);
+
+ /* Now try again with the probing functions */
+ found = 0;
+ blk_foreach_probe(BLKF_BOTH, dev)
+ found |= 1 << dectoul(&dev->name[3], NULL);
+ ut_asserteq(7, found);
+ ut_asserteq(3, blk_count_devices(BLKF_BOTH));
+
+ found = 0;
+ blk_foreach_probe(BLKF_FIXED, dev)
+ found |= 1 << dectoul(&dev->name[3], NULL);
+ ut_asserteq(4, found);
+ ut_asserteq(1, blk_count_devices(BLKF_FIXED));
+
+ found = 0;
+ blk_foreach_probe(BLKF_REMOVABLE, dev)
+ found |= 1 << dectoul(&dev->name[3], NULL);
+ ut_asserteq(3, found);
+ ut_asserteq(2, blk_count_devices(BLKF_REMOVABLE));
+
+ return 0;
+}
+DM_TEST(dm_test_blk_foreach, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
#include <log.h>
#include <serial.h>
#include <dm.h>
+#include <asm/serial.h>
#include <dm/test.h>
#include <test/test.h>
#include <test/ut.h>
+static const char test_message[] =
+ "This is a test message\n"
+ "consisting of multiple lines\n";
+
static int dm_test_serial(struct unit_test_state *uts)
{
+ int i;
struct serial_device_info info_serial = {0};
struct udevice *dev_serial;
+ size_t start, putc_written;
+
uint value_serial;
ut_assertok(uclass_get_device_by_name(UCLASS_SERIAL, "serial",
SERIAL_8_BITS,
SERIAL_TWO_STOP)));
+ /* Verify that putc and puts print the same number of characters */
+ sandbox_serial_endisable(false);
+ start = sandbox_serial_written();
+ for (i = 0; i < sizeof(test_message) - 1; i++)
+ serial_putc(test_message[i]);
+ putc_written = sandbox_serial_written();
+ serial_puts(test_message);
+ sandbox_serial_endisable(true);
+ ut_asserteq(putc_written - start,
+ sandbox_serial_written() - putc_written);
+
return 0;
}
}
LIB_TEST(lib_test_abuf_realloc, 0);
+/* Test abuf_realloc() on an non-allocated buffer of zero size */
+static int lib_test_abuf_realloc_size(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+
+ start = ut_check_free();
+
+ abuf_init(&buf);
+
+ /* Allocate some space */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+
+ /* Free it */
+ ut_asserteq(true, abuf_realloc(&buf, 0));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_realloc_size, 0);
+
/* Test handling of buffers that are too large */
static int lib_test_abuf_large(struct unit_test_state *uts)
{
"""
import os
-import pytest
import shutil
-from subprocess import call, check_call
+from subprocess import check_call
+import pytest
@pytest.fixture(scope='session')
def efi_bootmgr_data(u_boot_config):
tests
Args:
- u_boot_config: U-boot configuration.
+ u_boot_config -- U-boot configuration.
Return:
A path to disk image to be used for testing
shutil.copyfile(u_boot_config.build_dir + '/lib/efi_loader/initrddump.efi',
mnt_point + '/initrddump.efi')
- check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat {} {}'
- .format(mnt_point, image_path), shell=True)
-
- print(image_path)
+ check_call(f'virt-make-fs --partition=gpt --size=+1M --type=vfat {mnt_point} {image_path}',
+ shell=True)
- yield image_path
+ return image_path
# SPDX-License-Identifier: GPL-2.0+
+""" Unit test for UEFI bootmanager
+"""
import pytest
@pytest.mark.buildconfigspec('cmd_efidebug')
@pytest.mark.buildconfigspec('cmd_bootefi_bootmgr')
def test_efi_bootmgr(u_boot_console, efi_bootmgr_data):
- u_boot_console.run_command(cmd = 'host bind 0 {}'.format(efi_bootmgr_data))
+ """ Unit test for UEFI bootmanager
+ The efidebug command is used to set up UEFI load options.
+ The bootefi bootmgr loads initrddump.efi as a payload.
+ The crc32 of the loaded initrd.img is checked
+
+ Args:
+ u_boot_console -- U-Boot console
+ efi_bootmgr_data -- Path to the disk image used for testing.
+ """
+ u_boot_console.run_command(cmd = f'host bind 0 {efi_bootmgr_data}')
u_boot_console.run_command(cmd = 'efidebug boot add ' \
'-b 0001 label-1 host 0:1 initrddump.efi ' \
"""Compute the path of a given (temporary) file.
Args:
- file_name: The name of a file within U-Boot build dir.
+ file_name -- The name of a file within U-Boot build dir.
Return:
The computed file path.
"""
build dir and, optionally, compresses the file using gzip.
Args:
- fname: The target file name within U-Boot build dir.
- comp: Flag to enable gzip compression.
+ fname -- The target file name within U-Boot build dir.
+ comp -- Flag to enable gzip compression.
Return:
The path of the created file.
"""
Creates a DTS file and compiles it to a DTB.
Args:
- fdt_type: The type of the FDT, i.e. internal, user.
- comp: Flag to enable gzip compression.
+ fdt_type -- The type of the FDT, i.e. internal, user.
+ comp -- Flag to enable gzip compression.
Return:
The path of the created file.
"""
# Generate a test FDT file.
dts = make_fpath('test-efi-fit-%s.dts' % fdt_type)
- with open(dts, 'w') as file:
+ with open(dts, 'w', encoding='ascii') as file:
file.write(FDT_DATA % fdt_params)
# Build the test FDT.
Runs 'mkimage' to create a FIT image within U-Boot build dir.
Args:
- comp: Enable gzip compression for the EFI binary and FDT blob.
+ comp -- Enable gzip compression for the EFI binary and FDT blob.
Return:
The path of the created file.
"""
# Generate a test ITS file.
its_path = make_fpath('test-efi-fit-helloworld.its')
- with open(its_path, 'w') as file:
+ with open(its_path, 'w', encoding='ascii') as file:
file.write(ITS_DATA % its_params)
# Build the test ITS.
"""Load the FIT image using the 'host load' command and return its address.
Args:
- fit: Dictionary describing the FIT image to load, see env__efi_fit_test_file
- in the comment at the beginning of this file.
+ fit -- Dictionary describing the FIT image to load, see
+ env__efi_fit_test_file in the comment at the beginning of
+ this file.
Return:
The address where the file has been loaded.
"""
CRC32 are validated.
Args:
- fit: Dictionary describing the FIT image to load, see env__efi_fit_tftp_file
- in the comment at the beginning of this file.
+ fit -- Dictionary describing the FIT image to load, see env__efi_fit_tftp_file
+ in the comment at the beginning of this file.
Return:
The address where the file has been loaded.
"""
Eventually the 'Hello, world' message is expected in the U-Boot console.
Args:
- enable_fdt: Flag to enable using the FDT blob inside FIT image.
- enable_comp: Flag to enable GZIP compression on EFI and FDT
- generated content.
+ enable_fdt -- Flag to enable using the FDT blob inside FIT image.
+ enable_comp -- Flag to enable GZIP compression on EFI and FDT
+ generated content.
"""
with cons.log.section('FDT=%s;COMP=%s' % (enable_fdt, enable_comp)):
# two vars
check_script('''fred=123
-ernie=456''', 'fred=123\\0ernie=456\\0')
+mary=456''', 'fred=123\\0mary=456\\0')
# blank lines
check_script('''fred=123
-ernie=456
+mary=456
-''', 'fred=123\\0ernie=456\\0')
+''', 'fred=123\\0mary=456\\0')
# append
check_script('''fred=123
-ernie=456
-fred+= 456''', 'fred=123 456\\0ernie=456\\0')
+mary=456
+fred+= 456''', 'fred=123 456\\0mary=456\\0')
# append from empty
check_script('''fred=
-ernie=456
-fred+= 456''', 'fred= 456\\0ernie=456\\0')
+mary=456
+fred+= 456''', 'fred= 456\\0mary=456\\0')
# variable with + in it
- check_script('fred+ernie=123', 'fred+ernie=123\\0')
+ check_script('fred+mary=123', 'fred+mary=123\\0')
# ignores variables that are empty
check_script('''fred=
fred+=
-ernie=456''', 'ernie=456\\0')
+mary=456''', 'mary=456\\0')
# single-character env name
- check_script('''f=123
+ check_script('''m=123
e=456
-f+= 456''', 'e=456\\0f=123 456\\0')
+m+= 456''', 'e=456\\0m=123 456\\0')
# contains quotes
check_script('''fred="my var"
-ernie=another"''', 'fred=\\"my var\\"\\0ernie=another\\"\\0')
+mary=another"''', 'fred=\\"my var\\"\\0mary=another\\"\\0')
# variable name ending in +
check_script('''fred\\+=my var
# variable name containing +
check_script('''fred+jane=both
fred+jane+=again
-ernie=456''', 'fred+jane=bothagain\\0ernie=456\\0')
+mary=456''', 'fred+jane=bothagain\\0mary=456\\0')
# multi-line vars - new vars always start at column 1
check_script('''fred=first
after blank
confusing=oops
-ernie=another"''', 'fred=first second third with tab after blank confusing=oops\\0ernie=another\\"\\0')
+mary=another"''', 'fred=first second third with tab after blank confusing=oops\\0mary=another\\"\\0')
# real-world example
check_script('''ubifs_boot=
-# SPDX-License-Identifier: GPL-2.0+
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2021 Adarsh Babu Kalepalli <opensource.kab@gmail.com>
+# Copyright (c) 2020 Alex Kiernan <alex.kiernan@gmail.com>
import pytest
+import time
+import u_boot_utils
+
+"""
+ test_gpio_input is intended to test the fix 4dbc107f4683.
+ 4dbc107f4683:"cmd: gpio: Correct do_gpio() return value"
+"""
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpio')
assert(expected_response in response)
response = u_boot_console.run_command('gpio input 200; echo rc:$?')
assert(expected_response in response)
+
+
+"""
+Generic Tests for 'gpio' command on sandbox and real hardware.
+The below sequence of tests rely on env__gpio_dev_config for configuration values of gpio pins.
+
+ Configuration data for gpio command.
+ The set,clear,toggle ,input and status options of 'gpio' command are verified.
+ For sake of verification,A LED/buzzer could be connected to GPIO pins configured as O/P.
+ Logic level '1'/'0' can be applied onto GPIO pins configured as I/P
+
+
+env__gpio_dev_config = {
+ #the number of 'gpio_str_x' strings should equal to
+ #'gpio_str_count' value
+ 'gpio_str_count':4 ,
+ 'gpio_str_1': '0',
+ 'gpio_str_2': '31',
+ 'gpio_str_3': '63',
+ 'gpio_str_4': '127',
+ 'gpio_op_pin': '64',
+ 'gpio_ip_pin_set':'65',
+ 'gpio_ip_pin_clear':'66',
+ 'gpio_clear_value': 'value is 0',
+ 'gpio_set_value': 'value is 1',
+}
+"""
+
+
+@pytest.mark.buildconfigspec('cmd_gpio')
+def test_gpio_status_all_generic(u_boot_console):
+ """Test the 'gpio status' command.
+
+ Displays all gpio pins available on the Board.
+ To verify if the status of pins is displayed or not,
+ the user can configure (gpio_str_count) and verify existence of certain
+ pins.The details of these can be configured in 'gpio_str_n'.
+ of boardenv_* (example above).User can configure any
+ number of such pins and mention that count in 'gpio_str_count'.
+ """
+
+ f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ if not f:
+ pytest.skip("gpio not configured")
+
+ gpio_str_count = f['gpio_str_count']
+
+ #Display all the GPIO ports
+ cmd = 'gpio status -a'
+ response = u_boot_console.run_command(cmd)
+
+ for str_value in range(1,gpio_str_count + 1):
+ assert f["gpio_str_%d" %(str_value)] in response
+
+
+@pytest.mark.buildconfigspec('cmd_gpio')
+def test_gpio_set_generic(u_boot_console):
+ """Test the 'gpio set' command.
+
+ A specific gpio pin configured by user as output
+ (mentioned in gpio_op_pin) is verified for
+ 'set' option
+
+ """
+
+ f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ if not f:
+ pytest.skip("gpio not configured")
+
+ gpio_pin_adr = f['gpio_op_pin'];
+ gpio_set_value = f['gpio_set_value'];
+
+
+ cmd = 'gpio set ' + gpio_pin_adr
+ response = u_boot_console.run_command(cmd)
+ good_response = gpio_set_value
+ assert good_response in response
+
+
+
+@pytest.mark.buildconfigspec('cmd_gpio')
+def test_gpio_clear_generic(u_boot_console):
+ """Test the 'gpio clear' command.
+
+ A specific gpio pin configured by user as output
+ (mentioned in gpio_op_pin) is verified for
+ 'clear' option
+ """
+
+ f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ if not f:
+ pytest.skip("gpio not configured")
+
+ gpio_pin_adr = f['gpio_op_pin'];
+ gpio_clear_value = f['gpio_clear_value'];
+
+
+ cmd = 'gpio clear ' + gpio_pin_adr
+ response = u_boot_console.run_command(cmd)
+ good_response = gpio_clear_value
+ assert good_response in response
+
+
+@pytest.mark.buildconfigspec('cmd_gpio')
+def test_gpio_toggle_generic(u_boot_console):
+ """Test the 'gpio toggle' command.
+
+ A specific gpio pin configured by user as output
+ (mentioned in gpio_op_pin) is verified for
+ 'toggle' option
+ """
+
+
+ f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ if not f:
+ pytest.skip("gpio not configured")
+
+ gpio_pin_adr = f['gpio_op_pin'];
+ gpio_set_value = f['gpio_set_value'];
+ gpio_clear_value = f['gpio_clear_value'];
+
+ cmd = 'gpio set ' + gpio_pin_adr
+ response = u_boot_console.run_command(cmd)
+ good_response = gpio_set_value
+ assert good_response in response
+
+ cmd = 'gpio toggle ' + gpio_pin_adr
+ response = u_boot_console.run_command(cmd)
+ good_response = gpio_clear_value
+ assert good_response in response
+
+
+@pytest.mark.buildconfigspec('cmd_gpio')
+def test_gpio_input_generic(u_boot_console):
+ """Test the 'gpio input' command.
+
+ Specific gpio pins configured by user as input
+ (mentioned in gpio_ip_pin_set and gpio_ip_pin_clear)
+ is verified for logic '1' and logic '0' states
+ """
+
+ f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ if not f:
+ pytest.skip("gpio not configured")
+
+ gpio_pin_adr = f['gpio_ip_pin_clear'];
+ gpio_clear_value = f['gpio_clear_value'];
+
+
+ cmd = 'gpio input ' + gpio_pin_adr
+ response = u_boot_console.run_command(cmd)
+ good_response = gpio_clear_value
+ assert good_response in response
+
+
+ gpio_pin_adr = f['gpio_ip_pin_set'];
+ gpio_set_value = f['gpio_set_value'];
+
+
+ cmd = 'gpio input ' + gpio_pin_adr
+ response = u_boot_console.run_command(cmd)
+ good_response = gpio_set_value
+ assert good_response in response
AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/aes/, \
aes-encrypt.o aes-decrypt.o)
-# Cryptographic helpers that depend on openssl/libcrypto
-LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/, \
- fdt-libcrypto.o)
+# Cryptographic helpers and image types that depend on openssl/libcrypto
+LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := \
+ lib/fdt-libcrypto.o \
+ sunxi_toc0.o
ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o
Returns:
str: Tool output
"""
- args = ['gbb_utility'
+ args = ['gbb_utility',
'-s',
f'--hwid={hwid}',
f'--rootkey={rootkey}',
'--keyblock', keyblock,
'--signprivate', signprivate,
'--version', version,
- '--fw', firmware,
+ '--fv', firmware,
'--kernelkey', kernelkey,
'--flags', flags
]
vblock=output_fname,
keyblock=prefix + self.keyblock,
signprivate=prefix + self.signprivate,
- version=f'{self.version,}',
+ version=f'{self.version:d}',
firmware=input_fname,
kernelkey=prefix + self.kernelkey,
flags=f'{self.preamble_flags}')
int pflag;
int vflag;
int xflag;
+ int Aflag;
int skipcpy;
int os;
int arch;
show_valid_options(IH_ARCH);
usage("Invalid architecture");
}
+ params.Aflag = 1;
break;
case 'b':
if (add_content(IH_TYPE_FLATDT, optarg)) {
usage("Missing output filename");
}
+static void verify_image(const struct image_type_params *tparams)
+{
+ struct stat sbuf;
+ void *ptr;
+ int ifd;
+
+ ifd = open(params.imagefile, O_RDONLY | O_BINARY);
+ if (ifd < 0) {
+ fprintf(stderr, "%s: Can't open %s: %s\n",
+ params.cmdname, params.imagefile,
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ if (fstat(ifd, &sbuf) < 0) {
+ fprintf(stderr, "%s: Can't stat %s: %s\n",
+ params.cmdname, params.imagefile, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ params.file_size = sbuf.st_size;
+
+ ptr = mmap(0, params.file_size, PROT_READ, MAP_SHARED, ifd, 0);
+ if (ptr == MAP_FAILED) {
+ fprintf(stderr, "%s: Can't map %s: %s\n",
+ params.cmdname, params.imagefile, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ if (tparams->verify_header((unsigned char *)ptr, params.file_size, ¶ms) != 0) {
+ fprintf(stderr, "%s: Failed to verify header of %s\n",
+ params.cmdname, params.imagefile);
+ exit(EXIT_FAILURE);
+ }
+
+ (void)munmap(ptr, params.file_size);
+ (void)close(ifd);
+}
+
int main(int argc, char **argv)
{
int ifd = -1;
exit (EXIT_FAILURE);
}
+ if (tparams->verify_header)
+ verify_image(tparams);
+
exit (EXIT_SUCCESS);
}
return (ulong)(uintptr_t)ptr;
}
+#define ARCH_DMA_MINALIGN 1
+#define DEFINE_ALIGN_BUFFER(type, name, size, alugn) type name[size]
+
#define MKIMAGE_TMPFILE_SUFFIX ".tmp"
#define MKIMAGE_MAX_TMPFILE_LEN 256
#define MKIMAGE_DEFAULT_DTC_OPTIONS "-I dts -O dtb -p 500"
struct spl_info *img_spl_info, *spl_info;
int ret;
+ /* spl_hdr is abandon on header_v2 */
+ if ((*(uint32_t *)buf) == RK_MAGIC_V2)
+ return 0;
+
ret = rkcommon_parse_header(buf, &header0, &img_spl_info);
/* If this is the (unimplemented) RC4 case, then rewrite the result */
#define PAD_SIZE 8192
#define PAD_SIZE_MIN 512
+static int egon_get_arch(struct image_tool_params *params)
+{
+ if (params->Aflag)
+ return params->arch;
+
+ /* For compatibility, assume ARM when no architecture specified */
+ return IH_ARCH_ARM;
+}
+
static int egon_check_params(struct image_tool_params *params)
{
- /* We just need a binary image file. */
+ /*
+ * Check whether the architecture is supported.
+ */
+ switch (egon_get_arch(params)) {
+ case IH_ARCH_ARM:
+ case IH_ARCH_RISCV:
+ break;
+ default:
+ return EXIT_FAILURE;
+ }
+
+ /* We need a binary image file. */
return !params->dflag;
}
const struct boot_file_head *header = (void *)ptr;
uint32_t length;
- /* First 4 bytes must be an ARM branch instruction. */
- if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 0xea000000)
- return EXIT_FAILURE;
+ /*
+ * First 4 bytes must be a branch instruction of the corresponding
+ * architecture.
+ */
+ switch (egon_get_arch(params)) {
+ case IH_ARCH_ARM:
+ if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 0xea000000)
+ return EXIT_FAILURE;
+ break;
+ case IH_ARCH_RISCV:
+ if ((le32_to_cpu(header->b_instruction) & 0x00000fff) != 0x0000006f)
+ return EXIT_FAILURE;
+ break;
+ default:
+ return EXIT_FAILURE; /* Unknown architecture */
+ }
if (memcmp(header->magic, BOOT0_MAGIC, sizeof(header->magic)))
return EXIT_FAILURE;
uint32_t checksum = 0, value;
int i;
- /* Generate an ARM branch instruction to jump over the header. */
- value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2);
- header->b_instruction = cpu_to_le32(value);
+ /*
+ * Different architectures need different first instruction to
+ * branch to the body.
+ */
+ switch (egon_get_arch(params)) {
+ case IH_ARCH_ARM:
+ /* Generate an ARM branch instruction to jump over the header. */
+ value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2);
+ header->b_instruction = cpu_to_le32(value);
+ break;
+ case IH_ARCH_RISCV:
+ /*
+ * Generate a RISC-V JAL instruction with rd=x0
+ * (pseudo instruction J, jump without side effects).
+ *
+ * The following weird bit operation maps imm[20]
+ * to inst[31], imm[10:1] to inst[30:21],
+ * imm[11] to inst[20], imm[19:12] to inst[19:12],
+ * and imm[0] is dropped (because 1-byte RISC-V instruction
+ * is not allowed).
+ */
+ value = 0x0000006f |
+ ((sizeof(struct boot_file_head) & 0x00100000) << 11) |
+ ((sizeof(struct boot_file_head) & 0x000007fe) << 20) |
+ ((sizeof(struct boot_file_head) & 0x00000800) << 9) |
+ ((sizeof(struct boot_file_head) & 0x000ff000) << 0);
+ header->b_instruction = cpu_to_le32(value);
+ break;
+ }
memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));
header->check_sum = cpu_to_le32(BROM_STAMP_VALUE);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Arm Ltd.
+ * (C) Copyright 2020-2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <openssl/asn1t.h>
+#include <openssl/pem.h>
+#include <openssl/rsa.h>
+
+#include <image.h>
+#include <sunxi_image.h>
+
+#include "imagetool.h"
+#include "mkimage.h"
+
+/*
+ * NAND requires 8K padding. For other devices, BROM requires only
+ * 512B padding, but let's use the larger padding to cover everything.
+ */
+#define PAD_SIZE 8192
+
+#define pr_fmt(fmt) "mkimage (TOC0): %s: " fmt
+#define pr_err(fmt, args...) fprintf(stderr, pr_fmt(fmt), "error", ##args)
+#define pr_warn(fmt, args...) fprintf(stderr, pr_fmt(fmt), "warning", ##args)
+#define pr_info(fmt, args...) fprintf(stderr, pr_fmt(fmt), "info", ##args)
+
+struct __packed toc0_key_item {
+ __le32 vendor_id;
+ __le32 key0_n_len;
+ __le32 key0_e_len;
+ __le32 key1_n_len;
+ __le32 key1_e_len;
+ __le32 sig_len;
+ uint8_t key0[512];
+ uint8_t key1[512];
+ uint8_t reserved[32];
+ uint8_t sig[256];
+};
+
+/*
+ * This looks somewhat like an X.509 certificate, but it is not valid BER.
+ *
+ * Some differences:
+ * - Some X.509 certificate fields are missing or rearranged.
+ * - Some sequences have the wrong tag.
+ * - Zero-length sequences are accepted.
+ * - Large strings and integers must be an even number of bytes long.
+ * - Positive integers are not zero-extended to maintain their sign.
+ *
+ * See https://linux-sunxi.org/TOC0 for more information.
+ */
+struct __packed toc0_small_tag {
+ uint8_t tag;
+ uint8_t length;
+};
+
+typedef struct toc0_small_tag toc0_small_int;
+typedef struct toc0_small_tag toc0_small_oct;
+typedef struct toc0_small_tag toc0_small_seq;
+typedef struct toc0_small_tag toc0_small_exp;
+
+#define TOC0_SMALL_INT(len) { 0x02, (len) }
+#define TOC0_SMALL_SEQ(len) { 0x30, (len) }
+#define TOC0_SMALL_EXP(tag, len) { 0xa0 | (tag), len }
+
+struct __packed toc0_large_tag {
+ uint8_t tag;
+ uint8_t prefix;
+ uint8_t length_hi;
+ uint8_t length_lo;
+};
+
+typedef struct toc0_large_tag toc0_large_int;
+typedef struct toc0_large_tag toc0_large_bit;
+typedef struct toc0_large_tag toc0_large_seq;
+
+#define TOC0_LARGE_INT(len) { 0x02, 0x82, (len) >> 8, (len) & 0xff }
+#define TOC0_LARGE_BIT(len) { 0x03, 0x82, (len) >> 8, (len) & 0xff }
+#define TOC0_LARGE_SEQ(len) { 0x30, 0x82, (len) >> 8, (len) & 0xff }
+
+struct __packed toc0_cert_item {
+ toc0_large_seq tag_totalSequence;
+ struct __packed toc0_totalSequence {
+ toc0_large_seq tag_mainSequence;
+ struct __packed toc0_mainSequence {
+ toc0_small_exp tag_explicit0;
+ struct __packed toc0_explicit0 {
+ toc0_small_int tag_version;
+ uint8_t version;
+ } explicit0;
+ toc0_small_int tag_serialNumber;
+ uint8_t serialNumber;
+ toc0_small_seq tag_signature;
+ toc0_small_seq tag_issuer;
+ toc0_small_seq tag_validity;
+ toc0_small_seq tag_subject;
+ toc0_large_seq tag_subjectPublicKeyInfo;
+ struct __packed toc0_subjectPublicKeyInfo {
+ toc0_small_seq tag_algorithm;
+ toc0_large_seq tag_publicKey;
+ struct __packed toc0_publicKey {
+ toc0_large_int tag_n;
+ uint8_t n[256];
+ toc0_small_int tag_e;
+ uint8_t e[3];
+ } publicKey;
+ } subjectPublicKeyInfo;
+ toc0_small_exp tag_explicit3;
+ struct __packed toc0_explicit3 {
+ toc0_small_seq tag_extension;
+ struct __packed toc0_extension {
+ toc0_small_int tag_digest;
+ uint8_t digest[32];
+ } extension;
+ } explicit3;
+ } mainSequence;
+ toc0_large_bit tag_sigSequence;
+ struct __packed toc0_sigSequence {
+ toc0_small_seq tag_algorithm;
+ toc0_large_bit tag_signature;
+ uint8_t signature[256];
+ } sigSequence;
+ } totalSequence;
+};
+
+#define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER))
+
+static const struct toc0_cert_item cert_item_template = {
+ TOC0_LARGE_SEQ(sizeof(struct toc0_totalSequence)),
+ {
+ TOC0_LARGE_SEQ(sizeof(struct toc0_mainSequence)),
+ {
+ TOC0_SMALL_EXP(0, sizeof(struct toc0_explicit0)),
+ {
+ TOC0_SMALL_INT(sizeof_field(struct toc0_explicit0, version)),
+ 0,
+ },
+ TOC0_SMALL_INT(sizeof_field(struct toc0_mainSequence, serialNumber)),
+ 0,
+ TOC0_SMALL_SEQ(0),
+ TOC0_SMALL_SEQ(0),
+ TOC0_SMALL_SEQ(0),
+ TOC0_SMALL_SEQ(0),
+ TOC0_LARGE_SEQ(sizeof(struct toc0_subjectPublicKeyInfo)),
+ {
+ TOC0_SMALL_SEQ(0),
+ TOC0_LARGE_SEQ(sizeof(struct toc0_publicKey)),
+ {
+ TOC0_LARGE_INT(sizeof_field(struct toc0_publicKey, n)),
+ {},
+ TOC0_SMALL_INT(sizeof_field(struct toc0_publicKey, e)),
+ {},
+ },
+ },
+ TOC0_SMALL_EXP(3, sizeof(struct toc0_explicit3)),
+ {
+ TOC0_SMALL_SEQ(sizeof(struct toc0_extension)),
+ {
+ TOC0_SMALL_INT(sizeof_field(struct toc0_extension, digest)),
+ {},
+ },
+ },
+ },
+ TOC0_LARGE_BIT(sizeof(struct toc0_sigSequence)),
+ {
+ TOC0_SMALL_SEQ(0),
+ TOC0_LARGE_BIT(sizeof_field(struct toc0_sigSequence, signature)),
+ {},
+ },
+ },
+};
+
+#define TOC0_DEFAULT_NUM_ITEMS 3
+#define TOC0_DEFAULT_HEADER_LEN \
+ ALIGN( \
+ sizeof(struct toc0_main_info) + \
+ sizeof(struct toc0_item_info) * TOC0_DEFAULT_NUM_ITEMS + \
+ sizeof(struct toc0_cert_item) + \
+ sizeof(struct toc0_key_item), \
+ 32)
+
+static char *fw_key_file = "fw_key.pem";
+static char *key_item_file = "key_item.bin";
+static char *root_key_file = "root_key.pem";
+
+/*
+ * Create a key item in @buf, containing the public keys @root_key and @fw_key,
+ * and signed by the RSA key @root_key.
+ */
+static int toc0_create_key_item(uint8_t *buf, uint32_t *len,
+ RSA *root_key, RSA *fw_key)
+{
+ struct toc0_key_item *key_item = (void *)buf;
+ uint8_t digest[SHA256_DIGEST_LENGTH];
+ int ret = EXIT_FAILURE;
+ unsigned int sig_len;
+ int n_len, e_len;
+
+ /* Store key 0. */
+ n_len = BN_bn2bin(RSA_get0_n(root_key), key_item->key0);
+ e_len = BN_bn2bin(RSA_get0_e(root_key), key_item->key0 + n_len);
+ if (n_len + e_len > sizeof(key_item->key0)) {
+ pr_err("Root key is too big for key item\n");
+ goto err;
+ }
+ key_item->key0_n_len = cpu_to_le32(n_len);
+ key_item->key0_e_len = cpu_to_le32(e_len);
+
+ /* Store key 1. */
+ n_len = BN_bn2bin(RSA_get0_n(fw_key), key_item->key1);
+ e_len = BN_bn2bin(RSA_get0_e(fw_key), key_item->key1 + n_len);
+ if (n_len + e_len > sizeof(key_item->key1)) {
+ pr_err("Firmware key is too big for key item\n");
+ goto err;
+ }
+ key_item->key1_n_len = cpu_to_le32(n_len);
+ key_item->key1_e_len = cpu_to_le32(e_len);
+
+ /* Sign the key item. */
+ key_item->sig_len = cpu_to_le32(RSA_size(root_key));
+ SHA256(buf, key_item->sig - buf, digest);
+ if (!RSA_sign(NID_sha256, digest, sizeof(digest),
+ key_item->sig, &sig_len, root_key)) {
+ pr_err("Failed to sign key item\n");
+ goto err;
+ }
+ if (sig_len != sizeof(key_item->sig)) {
+ pr_err("Bad key item signature length\n");
+ goto err;
+ }
+
+ *len = sizeof(*key_item);
+ ret = EXIT_SUCCESS;
+
+err:
+ return ret;
+}
+
+/*
+ * Verify the key item in @buf, containing two public keys @key0 and @key1,
+ * and signed by the RSA key @key0. If @root_key is provided, only signatures
+ * by that key will be accepted. @key1 is returned in @key.
+ */
+static int toc0_verify_key_item(const uint8_t *buf, uint32_t len,
+ RSA *root_key, RSA **fw_key)
+{
+ struct toc0_key_item *key_item = (void *)buf;
+ uint8_t digest[SHA256_DIGEST_LENGTH];
+ int ret = EXIT_FAILURE;
+ int n_len, e_len;
+ RSA *key0 = NULL;
+ RSA *key1 = NULL;
+ BIGNUM *n, *e;
+
+ if (len < sizeof(*key_item))
+ goto err;
+
+ /* Load key 0. */
+ n_len = le32_to_cpu(key_item->key0_n_len);
+ e_len = le32_to_cpu(key_item->key0_e_len);
+ if (n_len + e_len > sizeof(key_item->key0)) {
+ pr_err("Bad root key size in key item\n");
+ goto err;
+ }
+ n = BN_bin2bn(key_item->key0, n_len, NULL);
+ e = BN_bin2bn(key_item->key0 + n_len, e_len, NULL);
+ key0 = RSA_new();
+ if (!key0)
+ goto err;
+ if (!RSA_set0_key(key0, n, e, NULL))
+ goto err;
+
+ /* If a root key was provided, compare it to key 0. */
+ if (root_key && (BN_cmp(n, RSA_get0_n(root_key)) ||
+ BN_cmp(e, RSA_get0_e(root_key)))) {
+ pr_err("Wrong root key in key item\n");
+ goto err;
+ }
+
+ /* Verify the key item signature. */
+ SHA256(buf, key_item->sig - buf, digest);
+ if (!RSA_verify(NID_sha256, digest, sizeof(digest),
+ key_item->sig, le32_to_cpu(key_item->sig_len), key0)) {
+ pr_err("Bad key item signature\n");
+ goto err;
+ }
+
+ if (fw_key) {
+ /* Load key 1. */
+ n_len = le32_to_cpu(key_item->key1_n_len);
+ e_len = le32_to_cpu(key_item->key1_e_len);
+ if (n_len + e_len > sizeof(key_item->key1)) {
+ pr_err("Bad firmware key size in key item\n");
+ goto err;
+ }
+ n = BN_bin2bn(key_item->key1, n_len, NULL);
+ e = BN_bin2bn(key_item->key1 + n_len, e_len, NULL);
+ key1 = RSA_new();
+ if (!key1)
+ goto err;
+ if (!RSA_set0_key(key1, n, e, NULL))
+ goto err;
+
+ if (*fw_key) {
+ /* If a FW key was provided, compare it to key 1. */
+ if (BN_cmp(n, RSA_get0_n(*fw_key)) ||
+ BN_cmp(e, RSA_get0_e(*fw_key))) {
+ pr_err("Wrong firmware key in key item\n");
+ goto err;
+ }
+ } else {
+ /* Otherwise, send key1 back to the caller. */
+ *fw_key = key1;
+ key1 = NULL;
+ }
+ }
+
+ ret = EXIT_SUCCESS;
+
+err:
+ RSA_free(key0);
+ RSA_free(key1);
+
+ return ret;
+}
+
+/*
+ * Create a certificate in @buf, describing the firmware with SHA256 digest
+ * @digest, and signed by the RSA key @fw_key.
+ */
+static int toc0_create_cert_item(uint8_t *buf, uint32_t *len, RSA *fw_key,
+ uint8_t digest[static SHA256_DIGEST_LENGTH])
+{
+ struct toc0_cert_item *cert_item = (void *)buf;
+ uint8_t cert_digest[SHA256_DIGEST_LENGTH];
+ struct toc0_totalSequence *totalSequence;
+ struct toc0_sigSequence *sigSequence;
+ struct toc0_extension *extension;
+ struct toc0_publicKey *publicKey;
+ int ret = EXIT_FAILURE;
+ unsigned int sig_len;
+
+ memcpy(cert_item, &cert_item_template, sizeof(*cert_item));
+ *len = sizeof(*cert_item);
+
+ /*
+ * Fill in the public key.
+ *
+ * Only 2048-bit RSA keys are supported. Since this uses a fixed-size
+ * structure, it may fail for non-standard exponents.
+ */
+ totalSequence = &cert_item->totalSequence;
+ publicKey = &totalSequence->mainSequence.subjectPublicKeyInfo.publicKey;
+ if (BN_bn2binpad(RSA_get0_n(fw_key), publicKey->n, sizeof(publicKey->n)) < 0 ||
+ BN_bn2binpad(RSA_get0_e(fw_key), publicKey->e, sizeof(publicKey->e)) < 0) {
+ pr_err("Firmware key is too big for certificate\n");
+ goto err;
+ }
+
+ /* Fill in the firmware digest. */
+ extension = &totalSequence->mainSequence.explicit3.extension;
+ memcpy(&extension->digest, digest, SHA256_DIGEST_LENGTH);
+
+ /*
+ * Sign the certificate.
+ *
+ * In older SBROM versions (and by default in newer versions),
+ * the last 4 bytes of the certificate are not signed.
+ *
+ * (The buffer passed to SHA256 starts at tag_mainSequence, but
+ * the buffer size does not include the length of that tag.)
+ */
+ SHA256((uint8_t *)totalSequence, sizeof(struct toc0_mainSequence), cert_digest);
+ sigSequence = &totalSequence->sigSequence;
+ if (!RSA_sign(NID_sha256, cert_digest, SHA256_DIGEST_LENGTH,
+ sigSequence->signature, &sig_len, fw_key)) {
+ pr_err("Failed to sign certificate\n");
+ goto err;
+ }
+ if (sig_len != sizeof(sigSequence->signature)) {
+ pr_err("Bad certificate signature length\n");
+ goto err;
+ }
+
+ ret = EXIT_SUCCESS;
+
+err:
+ return ret;
+}
+
+/*
+ * Verify the certificate in @buf, describing the firmware with SHA256 digest
+ * @digest, and signed by the RSA key contained within. If @fw_key is provided,
+ * only that key will be accepted.
+ *
+ * This function is only expected to work with images created by mkimage.
+ */
+static int toc0_verify_cert_item(const uint8_t *buf, uint32_t len, RSA *fw_key,
+ uint8_t digest[static SHA256_DIGEST_LENGTH])
+{
+ const struct toc0_cert_item *cert_item = (const void *)buf;
+ uint8_t cert_digest[SHA256_DIGEST_LENGTH];
+ const struct toc0_totalSequence *totalSequence;
+ const struct toc0_sigSequence *sigSequence;
+ const struct toc0_extension *extension;
+ const struct toc0_publicKey *publicKey;
+ int ret = EXIT_FAILURE;
+ RSA *key = NULL;
+ BIGNUM *n, *e;
+
+ /* Extract the public key from the certificate. */
+ totalSequence = &cert_item->totalSequence;
+ publicKey = &totalSequence->mainSequence.subjectPublicKeyInfo.publicKey;
+ n = BN_bin2bn(publicKey->n, sizeof(publicKey->n), NULL);
+ e = BN_bin2bn(publicKey->e, sizeof(publicKey->e), NULL);
+ key = RSA_new();
+ if (!key)
+ goto err;
+ if (!RSA_set0_key(key, n, e, NULL))
+ goto err;
+
+ /* If a key was provided, compare it to the embedded key. */
+ if (fw_key && (BN_cmp(RSA_get0_n(key), RSA_get0_n(fw_key)) ||
+ BN_cmp(RSA_get0_e(key), RSA_get0_e(fw_key)))) {
+ pr_err("Wrong firmware key in certificate\n");
+ goto err;
+ }
+
+ /* If a digest was provided, compare it to the embedded digest. */
+ extension = &totalSequence->mainSequence.explicit3.extension;
+ if (digest && memcmp(&extension->digest, digest, SHA256_DIGEST_LENGTH)) {
+ pr_err("Wrong firmware digest in certificate\n");
+ goto err;
+ }
+
+ /* Verify the certificate's signature. See the comment above. */
+ SHA256((uint8_t *)totalSequence, sizeof(struct toc0_mainSequence), cert_digest);
+ sigSequence = &totalSequence->sigSequence;
+ if (!RSA_verify(NID_sha256, cert_digest, SHA256_DIGEST_LENGTH,
+ sigSequence->signature,
+ sizeof(sigSequence->signature), key)) {
+ pr_err("Bad certificate signature\n");
+ goto err;
+ }
+
+ ret = EXIT_SUCCESS;
+
+err:
+ RSA_free(key);
+
+ return ret;
+}
+
+/*
+ * Always create a TOC0 containing 3 items. The extra item will be ignored on
+ * SoCs which do not support it.
+ */
+static int toc0_create(uint8_t *buf, uint32_t len, RSA *root_key, RSA *fw_key,
+ uint8_t *key_item, uint32_t key_item_len,
+ uint8_t *fw_item, uint32_t fw_item_len, uint32_t fw_addr)
+{
+ struct toc0_main_info *main_info = (void *)buf;
+ struct toc0_item_info *item_info = (void *)(main_info + 1);
+ uint8_t digest[SHA256_DIGEST_LENGTH];
+ uint32_t *buf32 = (void *)buf;
+ RSA *orig_fw_key = fw_key;
+ int ret = EXIT_FAILURE;
+ uint32_t checksum = 0;
+ uint32_t item_offset;
+ uint32_t item_length;
+ int i;
+
+ /* Hash the firmware for inclusion in the certificate. */
+ SHA256(fw_item, fw_item_len, digest);
+
+ /* Create the main TOC0 header, containing three items. */
+ memcpy(main_info->name, TOC0_MAIN_INFO_NAME, sizeof(main_info->name));
+ main_info->magic = cpu_to_le32(TOC0_MAIN_INFO_MAGIC);
+ main_info->checksum = cpu_to_le32(BROM_STAMP_VALUE);
+ main_info->num_items = cpu_to_le32(TOC0_DEFAULT_NUM_ITEMS);
+ memcpy(main_info->end, TOC0_MAIN_INFO_END, sizeof(main_info->end));
+
+ /* The first item links the ROTPK to the signing key. */
+ item_offset = sizeof(*main_info) +
+ sizeof(*item_info) * TOC0_DEFAULT_NUM_ITEMS;
+ /* Using an existing key item avoids needing the root private key. */
+ if (key_item) {
+ item_length = sizeof(*key_item);
+ if (toc0_verify_key_item(key_item, item_length,
+ root_key, &fw_key))
+ goto err;
+ memcpy(buf + item_offset, key_item, item_length);
+ } else if (toc0_create_key_item(buf + item_offset, &item_length,
+ root_key, fw_key)) {
+ goto err;
+ }
+
+ item_info->name = cpu_to_le32(TOC0_ITEM_INFO_NAME_KEY);
+ item_info->offset = cpu_to_le32(item_offset);
+ item_info->length = cpu_to_le32(item_length);
+ memcpy(item_info->end, TOC0_ITEM_INFO_END, sizeof(item_info->end));
+
+ /* The second item contains a certificate signed by the firmware key. */
+ item_offset = item_offset + item_length;
+ if (toc0_create_cert_item(buf + item_offset, &item_length,
+ fw_key, digest))
+ goto err;
+
+ item_info++;
+ item_info->name = cpu_to_le32(TOC0_ITEM_INFO_NAME_CERT);
+ item_info->offset = cpu_to_le32(item_offset);
+ item_info->length = cpu_to_le32(item_length);
+ memcpy(item_info->end, TOC0_ITEM_INFO_END, sizeof(item_info->end));
+
+ /* The third item contains the actual boot code. */
+ item_offset = ALIGN(item_offset + item_length, 32);
+ item_length = fw_item_len;
+ if (buf + item_offset != fw_item)
+ memmove(buf + item_offset, fw_item, item_length);
+
+ item_info++;
+ item_info->name = cpu_to_le32(TOC0_ITEM_INFO_NAME_FIRMWARE);
+ item_info->offset = cpu_to_le32(item_offset);
+ item_info->length = cpu_to_le32(item_length);
+ item_info->load_addr = cpu_to_le32(fw_addr);
+ memcpy(item_info->end, TOC0_ITEM_INFO_END, sizeof(item_info->end));
+
+ /* Pad to the required block size with 0xff to be flash-friendly. */
+ item_offset = item_offset + item_length;
+ item_length = ALIGN(item_offset, PAD_SIZE) - item_offset;
+ memset(buf + item_offset, 0xff, item_length);
+
+ /* Fill in the total padded file length. */
+ item_offset = item_offset + item_length;
+ main_info->length = cpu_to_le32(item_offset);
+
+ /* Verify enough space was provided when creating the image. */
+ assert(len >= item_offset);
+
+ /* Calculate the checksum. Yes, it's that simple. */
+ for (i = 0; i < item_offset / 4; ++i)
+ checksum += le32_to_cpu(buf32[i]);
+ main_info->checksum = cpu_to_le32(checksum);
+
+ ret = EXIT_SUCCESS;
+
+err:
+ if (fw_key != orig_fw_key)
+ RSA_free(fw_key);
+
+ return ret;
+}
+
+static const struct toc0_item_info *
+toc0_find_item(const struct toc0_main_info *main_info, uint32_t name,
+ uint32_t *offset, uint32_t *length)
+{
+ const struct toc0_item_info *item_info = (void *)(main_info + 1);
+ uint32_t item_offset, item_length;
+ uint32_t num_items, main_length;
+ int i;
+
+ num_items = le32_to_cpu(main_info->num_items);
+ main_length = le32_to_cpu(main_info->length);
+
+ for (i = 0; i < num_items; ++i, ++item_info) {
+ if (le32_to_cpu(item_info->name) != name)
+ continue;
+
+ item_offset = le32_to_cpu(item_info->offset);
+ item_length = le32_to_cpu(item_info->length);
+
+ if (item_offset > main_length ||
+ item_length > main_length - item_offset)
+ continue;
+
+ *offset = item_offset;
+ *length = item_length;
+
+ return item_info;
+ }
+
+ return NULL;
+}
+
+static int toc0_verify(const uint8_t *buf, uint32_t len, RSA *root_key)
+{
+ const struct toc0_main_info *main_info = (void *)buf;
+ const struct toc0_item_info *item_info;
+ uint8_t digest[SHA256_DIGEST_LENGTH];
+ uint32_t main_length = le32_to_cpu(main_info->length);
+ uint32_t checksum = BROM_STAMP_VALUE;
+ uint32_t *buf32 = (void *)buf;
+ uint32_t length, offset;
+ int ret = EXIT_FAILURE;
+ RSA *fw_key = NULL;
+ int i;
+
+ if (len < main_length)
+ goto err;
+
+ /* Verify the main header. */
+ if (memcmp(main_info->name, TOC0_MAIN_INFO_NAME, sizeof(main_info->name)))
+ goto err;
+ if (le32_to_cpu(main_info->magic) != TOC0_MAIN_INFO_MAGIC)
+ goto err;
+ /* Verify the checksum without modifying the buffer. */
+ for (i = 0; i < main_length / 4; ++i)
+ checksum += le32_to_cpu(buf32[i]);
+ if (checksum != 2 * le32_to_cpu(main_info->checksum))
+ goto err;
+ /* The length must be at least 512 byte aligned. */
+ if (main_length % 512)
+ goto err;
+ if (memcmp(main_info->end, TOC0_MAIN_INFO_END, sizeof(main_info->end)))
+ goto err;
+
+ /* Verify the key item if present (it is optional). */
+ item_info = toc0_find_item(main_info, TOC0_ITEM_INFO_NAME_KEY,
+ &offset, &length);
+ if (!item_info)
+ fw_key = root_key;
+ else if (toc0_verify_key_item(buf + offset, length, root_key, &fw_key))
+ goto err;
+
+ /* Hash the firmware to compare with the certificate. */
+ item_info = toc0_find_item(main_info, TOC0_ITEM_INFO_NAME_FIRMWARE,
+ &offset, &length);
+ if (!item_info) {
+ pr_err("Missing firmware item\n");
+ goto err;
+ }
+ SHA256(buf + offset, length, digest);
+
+ /* Verify the certificate item. */
+ item_info = toc0_find_item(main_info, TOC0_ITEM_INFO_NAME_CERT,
+ &offset, &length);
+ if (!item_info) {
+ pr_err("Missing certificate item\n");
+ goto err;
+ }
+ if (toc0_verify_cert_item(buf + offset, length, fw_key, digest))
+ goto err;
+
+ ret = EXIT_SUCCESS;
+
+err:
+ if (fw_key != root_key)
+ RSA_free(fw_key);
+
+ return ret;
+}
+
+static int toc0_check_params(struct image_tool_params *params)
+{
+ if (!params->dflag)
+ return -EINVAL;
+
+ /*
+ * If a key directory was provided, look for key files there.
+ * Otherwise, look for them in the current directory. The key files are
+ * the "quoted" terms in the description below.
+ *
+ * A summary of the chain of trust on most SoCs:
+ * 1) eFuse contains a SHA256 digest of the public "root key".
+ * 2) Private "root key" signs the certificate item (generated here).
+ * 3) Certificate item contains a SHA256 digest of the firmware item.
+ *
+ * A summary of the chain of trust on the H6 (by default; a bit in the
+ * BROM_CONFIG eFuse makes it work like above):
+ * 1) eFuse contains a SHA256 digest of the public "root key".
+ * 2) Private "root key" signs the "key item" (generated here).
+ * 3) "Key item" contains the public "root key" and public "fw key".
+ * 4) Private "fw key" signs the certificate item (generated here).
+ * 5) Certificate item contains a SHA256 digest of the firmware item.
+ *
+ * This means there are three valid ways to generate a TOC0:
+ * 1) Provide the private "root key" only. This works everywhere.
+ * For H6, the "root key" will also be used as the "fw key".
+ * 2) FOR H6 ONLY: Provide the private "root key" and a separate
+ * private "fw key".
+ * 3) FOR H6 ONLY: Provide the private "fw key" and a pre-existing
+ * "key item" containing the corresponding public "fw key".
+ * In this case, the private "root key" can be kept offline. The
+ * "key item" can be extracted from a TOC0 image generated using
+ * method #2 above.
+ *
+ * Note that until the ROTPK_HASH eFuse is programmed, any "root key"
+ * will be accepted by the BROM.
+ */
+ if (params->keydir) {
+ if (asprintf(&fw_key_file, "%s/%s", params->keydir, fw_key_file) < 0)
+ return -ENOMEM;
+ if (asprintf(&key_item_file, "%s/%s", params->keydir, key_item_file) < 0)
+ return -ENOMEM;
+ if (asprintf(&root_key_file, "%s/%s", params->keydir, root_key_file) < 0)
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int toc0_verify_header(unsigned char *buf, int image_size,
+ struct image_tool_params *params)
+{
+ int ret = EXIT_FAILURE;
+ RSA *root_key = NULL;
+ FILE *fp;
+
+ /* A root public key is optional. */
+ fp = fopen(root_key_file, "rb");
+ if (fp) {
+ pr_info("Verifying image with existing root key\n");
+ root_key = PEM_read_RSAPrivateKey(fp, NULL, NULL, NULL);
+ if (!root_key)
+ root_key = PEM_read_RSAPublicKey(fp, NULL, NULL, NULL);
+ fclose(fp);
+ if (!root_key) {
+ pr_err("Failed to read public key from '%s'\n",
+ root_key_file);
+ goto err;
+ }
+ }
+
+ ret = toc0_verify(buf, image_size, root_key);
+
+err:
+ RSA_free(root_key);
+
+ return ret;
+}
+
+static const char *toc0_item_name(uint32_t name)
+{
+ if (name == TOC0_ITEM_INFO_NAME_CERT)
+ return "Certificate";
+ if (name == TOC0_ITEM_INFO_NAME_FIRMWARE)
+ return "Firmware";
+ if (name == TOC0_ITEM_INFO_NAME_KEY)
+ return "Key";
+ return "(unknown)";
+}
+
+static void toc0_print_header(const void *buf)
+{
+ const struct toc0_main_info *main_info = buf;
+ const struct toc0_item_info *item_info = (void *)(main_info + 1);
+ uint32_t head_length, main_length, num_items;
+ uint32_t item_offset, item_length, item_name;
+ int load_addr = -1;
+ int i;
+
+ num_items = le32_to_cpu(main_info->num_items);
+ head_length = sizeof(*main_info) + num_items * sizeof(*item_info);
+ main_length = le32_to_cpu(main_info->length);
+
+ printf("Allwinner TOC0 Image\n"
+ "Size: %d bytes\n"
+ "Contents: %d items\n"
+ " 00000000:%08x Headers\n",
+ main_length, num_items, head_length);
+
+ for (i = 0; i < num_items; ++i, ++item_info) {
+ item_offset = le32_to_cpu(item_info->offset);
+ item_length = le32_to_cpu(item_info->length);
+ item_name = le32_to_cpu(item_info->name);
+
+ if (item_name == TOC0_ITEM_INFO_NAME_FIRMWARE)
+ load_addr = le32_to_cpu(item_info->load_addr);
+
+ printf(" %08x:%08x %s\n",
+ item_offset, item_length,
+ toc0_item_name(item_name));
+ }
+
+ if (num_items && item_offset + item_length < main_length) {
+ item_offset = item_offset + item_length;
+ item_length = main_length - item_offset;
+
+ printf(" %08x:%08x Padding\n",
+ item_offset, item_length);
+ }
+
+ if (load_addr != -1)
+ printf("Load address: 0x%08x\n", load_addr);
+}
+
+static void toc0_set_header(void *buf, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ uint32_t key_item_len = 0;
+ uint8_t *key_item = NULL;
+ int ret = EXIT_FAILURE;
+ RSA *root_key = NULL;
+ RSA *fw_key = NULL;
+ FILE *fp;
+
+ /* Either a key item or the root private key is required. */
+ fp = fopen(key_item_file, "rb");
+ if (fp) {
+ pr_info("Creating image using existing key item\n");
+ key_item_len = sizeof(struct toc0_key_item);
+ key_item = OPENSSL_malloc(key_item_len);
+ if (!key_item || fread(key_item, key_item_len, 1, fp) != 1) {
+ pr_err("Failed to read key item from '%s'\n",
+ root_key_file);
+ goto err;
+ }
+ fclose(fp);
+ fp = NULL;
+ }
+
+ fp = fopen(root_key_file, "rb");
+ if (fp) {
+ root_key = PEM_read_RSAPrivateKey(fp, NULL, NULL, NULL);
+ if (!root_key)
+ root_key = PEM_read_RSAPublicKey(fp, NULL, NULL, NULL);
+ fclose(fp);
+ fp = NULL;
+ }
+
+ /* When using an existing key item, the root key is optional. */
+ if (!key_item && (!root_key || !RSA_get0_d(root_key))) {
+ pr_err("Failed to read private key from '%s'\n",
+ root_key_file);
+ pr_info("Try 'openssl genrsa -out root_key.pem'\n");
+ goto err;
+ }
+
+ /* The certificate/firmware private key is always required. */
+ fp = fopen(fw_key_file, "rb");
+ if (fp) {
+ fw_key = PEM_read_RSAPrivateKey(fp, NULL, NULL, NULL);
+ fclose(fp);
+ fp = NULL;
+ }
+ if (!fw_key) {
+ /* If the root key is a private key, it can be used instead. */
+ if (root_key && RSA_get0_d(root_key)) {
+ pr_info("Using root key as firmware key\n");
+ fw_key = root_key;
+ } else {
+ pr_err("Failed to read private key from '%s'\n",
+ fw_key_file);
+ goto err;
+ }
+ }
+
+ /* Warn about potential compatibility issues. */
+ if (key_item || fw_key != root_key)
+ pr_warn("Only H6 supports separate root and firmware keys\n");
+
+ ret = toc0_create(buf, params->file_size, root_key, fw_key,
+ key_item, key_item_len,
+ buf + TOC0_DEFAULT_HEADER_LEN,
+ params->orig_file_size, params->addr);
+
+err:
+ OPENSSL_free(key_item);
+ OPENSSL_free(root_key);
+ if (fw_key != root_key)
+ OPENSSL_free(fw_key);
+ if (fp)
+ fclose(fp);
+
+ if (ret != EXIT_SUCCESS)
+ exit(ret);
+}
+
+static int toc0_check_image_type(uint8_t type)
+{
+ return type == IH_TYPE_SUNXI_TOC0 ? 0 : 1;
+}
+
+static int toc0_vrec_header(struct image_tool_params *params,
+ struct image_type_params *tparams)
+{
+ tparams->hdr = calloc(tparams->header_size, 1);
+
+ /* Save off the unpadded data size for SHA256 calculation. */
+ params->orig_file_size = params->file_size - TOC0_DEFAULT_HEADER_LEN;
+
+ /* Return padding to 8K blocks. */
+ return ALIGN(params->file_size, PAD_SIZE) - params->file_size;
+}
+
+U_BOOT_IMAGE_TYPE(
+ sunxi_toc0,
+ "Allwinner TOC0 Boot Image support",
+ TOC0_DEFAULT_HEADER_LEN,
+ NULL,
+ toc0_check_params,
+ toc0_verify_header,
+ toc0_print_header,
+ toc0_set_header,
+ NULL,
+ toc0_check_image_type,
+ NULL,
+ toc0_vrec_header
+);
projects / thirdparty / u-boot.git / commitdiff
