RISC-V: Standardize formatting of SFB ALU conditional move

Standardize the formatting of SFB ALU conditional move operations from:

	beq a2,zero,1f; mv a0,zero; 1: # movcc

to:

	beq	a2,zero,1f	# movcc
	mv	a0,zero
1:

for consistency with other assembly code produced.  No functional change.

	gcc/
	* config/riscv/riscv.md (*mov<GPR:mode><X:mode>cc): Fix output
	pattern formatting.

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c517ae0d0f7226391ae157d61fe6a1be80f38c3e..f4a5ff07fe4da6eb3bf8e55ed5bd5f69fb46c71d 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2254,8 +2254,8 @@
         (match_operand:GPR 4 "sfb_alu_operand" "rJ,IL")))]
   "TARGET_SFB_ALU"
   "@
-   b%C5 %1,%z2,1f; mv %0,%z4; 1: # movcc
-   b%C5 %1,%z2,1f; li %0,%4; 1: # movcc"
+   b%C5\t%1,%z2,1f\t# movcc\;mv\t%0,%z4\n1:
+   b%C5\t%1,%z2,1f\t# movcc\;li\t%0,%4\n1:"
   [(set_attr "length" "8")
    (set_attr "type" "sfb_alu")
    (set_attr "mode" "<GPR:MODE>")])