--- /dev/null
+From d4a4206ebbaf48b55803a7eb34e330530d83a889 Mon Sep 17 00:00:00 2001
+From: Chris Boot <bootc@bootc.net>
+Date: Tue, 24 Apr 2012 07:24:52 +0000
+Subject: e1000e: Disable ASPM L1 on 82574
+
+From: Chris Boot <bootc@bootc.net>
+
+commit d4a4206ebbaf48b55803a7eb34e330530d83a889 upstream.
+
+ASPM on the 82574 causes trouble. Currently the driver disables L0s for
+this NIC but only disables L1 if the MTU is >1500. This patch simply
+causes L1 to be disabled regardless of the MTU setting.
+
+Signed-off-by: Chris Boot <bootc@bootc.net>
+Cc: "Wyborny, Carolyn" <carolyn.wyborny@intel.com>
+Cc: Nix <nix@esperi.org.uk>
+Link: https://lkml.org/lkml/2012/3/19/362
+Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
+Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
+Signed-off-by: Nikola Ciprich <nikola.ciprich@linuxbox.cz>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/e1000e/82571.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/e1000e/82571.c
++++ b/drivers/net/e1000e/82571.c
+@@ -2088,7 +2088,8 @@ struct e1000_info e1000_82574_info = {
+ | FLAG_HAS_AMT
+ | FLAG_HAS_CTRLEXT_ON_LOAD,
+ .flags2 = FLAG2_CHECK_PHY_HANG
+- | FLAG2_DISABLE_ASPM_L0S,
++ | FLAG2_DISABLE_ASPM_L0S
++ | FLAG2_DISABLE_ASPM_L1,
+ .pba = 32,
+ .max_hw_frame_size = DEFAULT_JUMBO,
+ .get_variants = e1000_get_variants_82571,
--- /dev/null
+From 4188bba0e9e7ba58d231b528df495666f2742b74 Mon Sep 17 00:00:00 2001
+From: Al Cooper <acooper@gmail.com>
+Date: Fri, 16 Mar 2012 15:54:17 -0400
+Subject: mmc: Prevent 1.8V switch for SD hosts that don't support UHS modes.
+
+From: Al Cooper <acooper@gmail.com>
+
+commit 4188bba0e9e7ba58d231b528df495666f2742b74 upstream.
+
+The driver should not try to switch to 1.8V when the SD 3.0 host
+controller does not have any UHS capabilities bits set (SDR50, DDR50
+or SDR104). See page 72 of "SD Specifications Part A2 SD Host
+Controller Simplified Specification Version 3.00" under
+"1.8V Signaling Enable". Instead of setting SDR12 and SDR25 in the host
+capabilities data structure for all V3.0 host controllers, only set them
+if SDR104, SDR50 or DDR50 is set in the host capabilities register. This
+will prevent the switch to 1.8V later.
+
+Signed-off-by: Al Cooper <acooper@gmail.com>
+Acked-by: Arindam Nath <arindam.nath@amd.com>
+Acked-by: Philip Rakity <prakity@marvell.com>
+Acked-by: Girish K S <girish.shivananjappa@linaro.org>
+Signed-off-by: Chris Ball <cjb@laptop.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mmc/host/sdhci.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/mmc/host/sdhci.c
++++ b/drivers/mmc/host/sdhci.c
+@@ -2515,8 +2515,9 @@ int sdhci_add_host(struct sdhci_host *ho
+ mmc_card_is_removable(mmc))
+ mmc->caps |= MMC_CAP_NEEDS_POLL;
+
+- /* UHS-I mode(s) supported by the host controller. */
+- if (host->version >= SDHCI_SPEC_300)
++ /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
++ if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
++ SDHCI_SUPPORT_DDR50))
+ mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
+
+ /* SDR104 supports also implies SDR50 support */
--- /dev/null
+From f2815f68dabbb373fd1c9f0fd4a609d486697c2b Mon Sep 17 00:00:00 2001
+From: Subhash Jadavani <subhashj@codeaurora.org>
+Date: Wed, 10 Aug 2011 11:16:01 +0530
+Subject: mmc: sd: Handle SD3.0 cards not supporting UHS-I bus speed mode
+
+From: Subhash Jadavani <subhashj@codeaurora.org>
+
+commit f2815f68dabbb373fd1c9f0fd4a609d486697c2b upstream.
+
+Here is Essential conditions to indicate Version 3.00 Card
+(SD_SPEC=2 and SD_SPEC3=1) :
+(1) The card shall support CMD6
+(2) The card shall support CMD8
+(3) The card shall support CMD42
+(4) User area capacity shall be up to 2GB (SDSC) or 32GB (SDHC)
+ User area capacity shall be more than or equal to 32GB and
+ up to 2TB (SDXC)
+(5) Speed Class shall be supported (SDHC or SDXC)
+
+So even if SD card doesn't support any of the newly defined
+UHS-I bus speed mode, it can advertise itself as SD3.0 cards
+as long as it supports all the essential conditions of
+SD3.0 cards. Given this, these type of cards should atleast
+run in High Speed mode @50MHZ if it supports HS.
+
+But current initialization sequence for SD3.0 cards is
+such that these non-UHS-I SD3.0 cards runs in Default
+Speed mode @25MHz.
+
+This patch makes sure that these non-UHS-I SD3.0 cards run
+in High Speed Mode @50MHz.
+
+Tested this patch with SanDisk Extreme SDHC 8GB Class 10 card.
+
+Reported-by: "Hiremath, Vaibhav" <hvaibhav@ti.com>
+Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
+Signed-off-by: Chris Ball <cjb@laptop.org>
+
+---
+ drivers/mmc/core/sd.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/mmc/core/sd.c
++++ b/drivers/mmc/core/sd.c
+@@ -306,6 +306,9 @@ static int mmc_read_switch(struct mmc_ca
+ goto out;
+ }
+
++ if (status[13] & UHS_SDR50_BUS_SPEED)
++ card->sw_caps.hs_max_dtr = 50000000;
++
+ if (card->scr.sda_spec3) {
+ card->sw_caps.sd3_bus_mode = status[13];
+
+@@ -348,9 +351,6 @@ static int mmc_read_switch(struct mmc_ca
+ }
+
+ card->sw_caps.sd3_curr_limit = status[7];
+- } else {
+- if (status[13] & 0x02)
+- card->sw_caps.hs_max_dtr = 50000000;
+ }
+
+ out:
pch_uart-fix-rx-error-interrupt-setting-issue.patch
pch_uart-fix-parity-setting-issue.patch
squashfs-fix-mount-time-sanity-check-for-corrupted-superblock.patch
+mmc-sd-handle-sd3.0-cards-not-supporting-uhs-i-bus-speed-mode.patch
+mmc-prevent-1.8v-switch-for-sd-hosts-that-don-t-support-uhs-modes.patch
+e1000e-disable-aspm-l1-on-82574.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
