clk: samsung: Add clock PLL support for ARTPEC-8 SoC

Add below clock PLL support for Axis ARTPEC-8 SoC platform:
- pll_1017x: Integer PLL with mid frequency FVCO (950 to 2400 MHz)
             This is used in ARTPEC-8 SoC for shared PLL

- pll_1031x: Integer/Fractional PLL with mid frequency FVCO
             (600 to 1200 MHz)
             This is used in ARTPEC-8 SoC for Audio PLL

FOUT calculation for pll_1017x and pll_1031x:
FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL
FOUT = (((MDIV + KDIV)/65536) x FIN)/(PDIV x 2^SDIV) for fractional PLL

Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Link: https://lore.kernel.org/r/20250825114436.46882-3-ravi.patel@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 3c04a0388ff9c6cec5b9b5779ad0c3be2b11cf07..7bea7be1d7e45c32f0b303ffa55ce9cde4a4f71d 100644 (file)
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -278,7 +278,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
        }
 
        /* Set PLL lock time. */
-       if (pll->type == pll_142xx)
+       if (pll->type == pll_142xx || pll->type == pll_1017x)
                writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
                        pll->lock_reg);
        else
@@ -1330,6 +1330,125 @@ static const struct clk_ops samsung_pll531x_clk_ops = {
        .recalc_rate = samsung_pll531x_recalc_rate,
 };
 
+/*
+ * PLL1031x Clock Type
+ */
+#define PLL1031X_LOCK_FACTOR   (500)
+
+#define PLL1031X_MDIV_MASK     (0x3ff)
+#define PLL1031X_PDIV_MASK     (0x3f)
+#define PLL1031X_SDIV_MASK     (0x7)
+#define PLL1031X_MDIV_SHIFT    (16)
+#define PLL1031X_PDIV_SHIFT    (8)
+#define PLL1031X_SDIV_SHIFT    (0)
+
+#define PLL1031X_KDIV_MASK     (0xffff)
+#define PLL1031X_KDIV_SHIFT    (0)
+#define PLL1031X_MFR_MASK      (0x3f)
+#define PLL1031X_MRR_MASK      (0x1f)
+#define PLL1031X_MFR_SHIFT     (16)
+#define PLL1031X_MRR_SHIFT     (24)
+
+static unsigned long samsung_pll1031x_recalc_rate(struct clk_hw *hw,
+                                                 unsigned long parent_rate)
+{
+       struct samsung_clk_pll *pll = to_clk_pll(hw);
+       u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con3;
+       u64 fvco = parent_rate;
+
+       pll_con0 = readl_relaxed(pll->con_reg);
+       pll_con3 = readl_relaxed(pll->con_reg + 0xc);
+       mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
+       pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
+       sdiv = (pll_con0 >> PLL1031X_SDIV_SHIFT) & PLL1031X_SDIV_MASK;
+       kdiv = (pll_con3 & PLL1031X_KDIV_MASK);
+
+       fvco *= (mdiv << PLL1031X_MDIV_SHIFT) + kdiv;
+       do_div(fvco, (pdiv << sdiv));
+       fvco >>= PLL1031X_MDIV_SHIFT;
+
+       return (unsigned long)fvco;
+}
+
+static bool samsung_pll1031x_mpk_change(u32 pll_con0, u32 pll_con3,
+                                       const struct samsung_pll_rate_table *rate)
+{
+       u32 old_mdiv, old_pdiv, old_kdiv;
+
+       old_mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
+       old_pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
+       old_kdiv = (pll_con3 >> PLL1031X_KDIV_SHIFT) & PLL1031X_KDIV_MASK;
+
+       return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv ||
+               old_kdiv != rate->kdiv);
+}
+
+static int samsung_pll1031x_set_rate(struct clk_hw *hw, unsigned long drate,
+                                    unsigned long prate)
+{
+       struct samsung_clk_pll *pll = to_clk_pll(hw);
+       const struct samsung_pll_rate_table *rate;
+       u32 con0, con3;
+
+       /* Get required rate settings from table */
+       rate = samsung_get_pll_settings(pll, drate);
+       if (!rate) {
+               pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+                      drate, clk_hw_get_name(hw));
+               return -EINVAL;
+       }
+
+       con0 = readl_relaxed(pll->con_reg);
+       con3 = readl_relaxed(pll->con_reg + 0xc);
+
+       if (!(samsung_pll1031x_mpk_change(con0, con3, rate))) {
+               /* If only s change, change just s value only */
+               con0 &= ~(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT);
+               con0 |= rate->sdiv << PLL1031X_SDIV_SHIFT;
+               writel_relaxed(con0, pll->con_reg);
+
+               return 0;
+       }
+
+       /* Set PLL lock time. */
+       writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg);
+
+       /* Set PLL M, P, and S values. */
+       con0 &= ~((PLL1031X_MDIV_MASK << PLL1031X_MDIV_SHIFT) |
+                 (PLL1031X_PDIV_MASK << PLL1031X_PDIV_SHIFT) |
+                 (PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT));
+
+       con0 |= (rate->mdiv << PLL1031X_MDIV_SHIFT) |
+               (rate->pdiv << PLL1031X_PDIV_SHIFT) |
+               (rate->sdiv << PLL1031X_SDIV_SHIFT);
+
+       /* Set PLL K, MFR and MRR values. */
+       con3 = readl_relaxed(pll->con_reg + 0xc);
+       con3 &= ~((PLL1031X_KDIV_MASK << PLL1031X_KDIV_SHIFT) |
+                 (PLL1031X_MFR_MASK << PLL1031X_MFR_SHIFT) |
+                 (PLL1031X_MRR_MASK << PLL1031X_MRR_SHIFT));
+       con3 |= (rate->kdiv << PLL1031X_KDIV_SHIFT) |
+               (rate->mfr << PLL1031X_MFR_SHIFT) |
+               (rate->mrr << PLL1031X_MRR_SHIFT);
+
+       /* Write configuration to PLL */
+       writel_relaxed(con0, pll->con_reg);
+       writel_relaxed(con3, pll->con_reg + 0xc);
+
+       /* Wait for PLL lock if the PLL is enabled */
+       return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
+}
+
+static const struct clk_ops samsung_pll1031x_clk_ops = {
+       .recalc_rate = samsung_pll1031x_recalc_rate,
+       .determine_rate = samsung_pll_determine_rate,
+       .set_rate = samsung_pll1031x_set_rate,
+};
+
+static const struct clk_ops samsung_pll1031x_clk_min_ops = {
+       .recalc_rate = samsung_pll1031x_recalc_rate,
+};
+
 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
                                const struct samsung_pll_clock *pll_clk)
 {
@@ -1378,6 +1497,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
        case pll_1451x:
        case pll_1452x:
        case pll_142xx:
+       case pll_1017x:
                pll->enable_offs = PLL35XX_ENABLE_SHIFT;
                pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
                if (!pll->rate_table)
@@ -1473,6 +1593,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
        case pll_4311:
                init.ops = &samsung_pll531x_clk_ops;
                break;
+       case pll_1031x:
+               if (!pll->rate_table)
+                       init.ops = &samsung_pll1031x_clk_min_ops;
+               else
+                       init.ops = &samsung_pll1031x_clk_ops;
+               break;
        default:
                pr_warn("%s: Unknown pll type for pll clk %s\n",
                        __func__, pll_clk->name);

diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index e9a5f8e0e0a3f30c37b4f3c13c01edc7fb4c4e20..6c8bb7f26da5436dfccae89a95d1b0025f7f3e0b 100644 (file)
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -49,6 +49,8 @@ enum samsung_pll_type {
        pll_0718x,
        pll_0732x,
        pll_4311,
+       pll_1017x,
+       pll_1031x,
 };
 
 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \