]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu: support SDMA v3 struct fw front door load
authorLikun Gao <Likun.Gao@amd.com>
Wed, 16 Aug 2023 05:30:30 +0000 (13:30 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 30 Apr 2024 14:03:42 +0000 (10:03 -0400)
Add support for new SDMA firmware struct (V3) with PSP
front door load type.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

index 4bd4602d11b1e46a4663b03b10017c14096d820a..a551c5b67fdd179ef76f2af9921a22d151029349 100644 (file)
@@ -2464,6 +2464,7 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
                *type = GFX_FW_TYPE_DMUB;
                break;
        case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
+       case AMDGPU_UCODE_ID_SDMA_RS64:
                *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
                break;
        case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
index f0aac8ced4dce5d9883458d0013568393d696a4d..6d23588ef2a2e479df69b014b117c8b5e1b9e16b 100644 (file)
@@ -212,6 +212,7 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,
        const struct common_firmware_header *header = NULL;
        int err, i;
        const struct sdma_firmware_header_v2_0 *sdma_hdr;
+       const struct sdma_firmware_header_v3_0 *sdma_hv3;
        uint16_t version_major;
        char ucode_prefix[30];
        char fw_name[52];
@@ -287,6 +288,15 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,
                        adev->firmware.fw_size +=
                                ALIGN(le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes), PAGE_SIZE);
                        break;
+               case 3:
+                       sdma_hv3 = (const struct sdma_firmware_header_v3_0 *)
+                               adev->sdma.instance[0].fw->data;
+                       info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_RS64];
+                       info->ucode_id = AMDGPU_UCODE_ID_SDMA_RS64;
+                       info->fw = adev->sdma.instance[0].fw;
+                       adev->firmware.fw_size +=
+                               ALIGN(le32_to_cpu(sdma_hv3->ucode_size_bytes), PAGE_SIZE);
+                       break;
                default:
                        err = -EINVAL;
                }
index 42794b1bbe5ad4c2a3aa0b0f0a0e717aa338f85e..f7e69f5e6d73286bb59645b96005cd63c26215df 100644 (file)
@@ -797,6 +797,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
        const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
        const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
        const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
+       const struct sdma_firmware_header_v3_0 *sdmav3_hdr = NULL;
        const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
        const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL;
        const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL;
@@ -818,6 +819,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
        dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
        mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
        sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
+       sdmav3_hdr = (const struct sdma_firmware_header_v3_0 *)ucode->fw->data;
        imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
        vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data;
        umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data;
@@ -834,6 +836,11 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                        ucode_addr = (u8 *)ucode->fw->data +
                                le32_to_cpu(sdma_hdr->ctl_ucode_offset);
                        break;
+               case AMDGPU_UCODE_ID_SDMA_RS64:
+                       ucode->ucode_size = le32_to_cpu(sdmav3_hdr->ucode_size_bytes);
+                       ucode_addr = (u8 *)ucode->fw->data +
+                               le32_to_cpu(sdmav3_hdr->header.ucode_array_offset_bytes);
+                       break;
                case AMDGPU_UCODE_ID_CP_MEC1:
                case AMDGPU_UCODE_ID_CP_MEC2:
                        ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
index 9a061c7b86eeb232dc8f88d02b268de9cb1d2425..a3c04f7110993696157cb06a533349dcd041b7be 100644 (file)
@@ -464,6 +464,7 @@ enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_SDMA7,
        AMDGPU_UCODE_ID_SDMA_UCODE_TH0,
        AMDGPU_UCODE_ID_SDMA_UCODE_TH1,
+       AMDGPU_UCODE_ID_SDMA_RS64,
        AMDGPU_UCODE_ID_CP_CE,
        AMDGPU_UCODE_ID_CP_PFP,
        AMDGPU_UCODE_ID_CP_ME,