clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg

The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
single bit per module.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-10-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 48265276d16934bfc151a232467c68b6ac79b620..f8a68bbc76f29556a05a043d8e9359706881718e 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1177,8 +1177,16 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
        const struct rzg2l_cpg_info *info = priv->info;
        unsigned int reg = info->resets[id].off;
        u32 bitmask = BIT(info->resets[id].bit);
+       s8 monbit = info->resets[id].monbit;
 
-       return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
+       if (info->has_clk_mon_regs) {
+               return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
+       } else if (monbit >= 0) {
+               u32 monbitmask = BIT(monbit);
+
+               return !!(readl(priv->base + CPG_RST_MON) & monbitmask);
+       }
+       return -ENOTSUPP;
 }
 
 static const struct reset_control_ops rzg2l_cpg_reset_ops = {

diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 43ce319a477f5719a64c59378bfcd8a533bec228..6fbb431fb3313909498fdc1c85d13151a0d6711f 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -25,6 +25,7 @@
 #define CPG_PL6_SSEL           (0x414)
 #define CPG_PL6_ETH_SSEL       (0x418)
 #define CPG_PL5_SDIV           (0x420)
+#define CPG_RST_MON            (0x680)
 #define CPG_OTHERFUNC1_REG     (0xBE8)
 
 #define CPG_SIPLL5_STBY_RESETB         BIT(0)
@@ -206,17 +207,22 @@ struct rzg2l_mod_clk {
  *
  * @off: register offset
  * @bit: reset bit
+ * @monbit: monitor bit in CPG_RST_MON register, -1 if none
  */
 struct rzg2l_reset {
        u16 off;
        u8 bit;
+       s8 monbit;
 };
 
-#define DEF_RST(_id, _off, _bit)       \
+#define DEF_RST_MON(_id, _off, _bit, _monbit)  \
        [_id] = { \
                .off = (_off), \
-               .bit = (_bit) \
+               .bit = (_bit), \
+               .monbit = (_monbit) \
        }
+#define DEF_RST(_id, _off, _bit)       \
+       DEF_RST_MON(_id, _off, _bit, -1)
 
 /**
  * struct rzg2l_cpg_info - SoC-specific CPG Description