]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu: pass ip_block in set_powergating_state
authorBoyuan Zhang <boyuan.zhang@amd.com>
Sun, 29 Sep 2024 19:17:51 +0000 (15:17 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 10 Dec 2024 15:26:47 +0000 (10:26 -0500)
Pass ip_block instead of adev in set_powergating_state callback function.
Modify set_powergating_state ip functions for all correspoding ip blocks.

v2: fix a ip block index error.

v3: remove type casting

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Suggested-by: Christian König <christian.koenig@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
82 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/cik_ih.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/cz_ih.c
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/iceland_ih.c
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
drivers/gpu/drm/amd/amdgpu/si.c
drivers/gpu/drm/amd/amdgpu/si_dma.c
drivers/gpu/drm/amd/amdgpu/si_ih.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/amdgpu/soc21.c
drivers/gpu/drm/amd/amdgpu/soc24.c
drivers/gpu/drm/amd/amdgpu/tonga_ih.c
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
drivers/gpu/drm/amd/amdgpu/vega20_ih.c
drivers/gpu/drm/amd/amdgpu/vi.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/include/amd_shared.h
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

index 769200cda626999726d9509e045f1ab53784d5ab..cdea150c801ee95fcb47204f185a4bc4a62fd4cf 100644 (file)
@@ -590,10 +590,10 @@ static int acp_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int acp_set_powergating_state(void *handle,
+static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                     enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        bool enable = (state == AMD_PG_STATE_GATE);
 
        amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);
index 3afcd1e8aa543534808eacd78ff9d63a99bdf163..5030513529228e21154de2414adfac8900933523 100644 (file)
@@ -724,7 +724,9 @@ void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
                /* Disable GFXOFF and PG. Temporary workaround
                 * to fix some compute applications issue on GFX9.
                 */
-               adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)adev, state);
+               struct amdgpu_ip_block *gfx_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
+               if (gfx_block != NULL)
+                       gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state);
        }
        amdgpu_dpm_switch_power_profile(adev,
                                        PP_SMC_POWER_PROFILE_COMPUTE,
index e41182645f9434c7fe8a010ca286d9423d641f0a..643a9a44e61415fe1a20da9988a9920f8bf715b9 100644 (file)
@@ -2199,7 +2199,7 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
                if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
                        continue;
                r = adev->ip_blocks[i].version->funcs->set_powergating_state(
-                       (void *)adev, state);
+                       &adev->ip_blocks[i], state);
                if (r)
                        DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
                                  adev->ip_blocks[i].version->funcs->name, r);
@@ -3174,7 +3174,7 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
                    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
                    adev->ip_blocks[i].version->funcs->set_powergating_state) {
                        /* enable powergating to save power */
-                       r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
+                       r = adev->ip_blocks[i].version->funcs->set_powergating_state(&adev->ip_blocks[i],
                                                                                        state);
                        if (r) {
                                DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
index 263ce1811cc84219fc5a5eaadf3589047d12aca8..bc3b5bfc3423cc9cc70a3d4d7b244fb34cb393a2 100644 (file)
@@ -134,7 +134,7 @@ static int isp_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int isp_set_powergating_state(void *handle,
+static int isp_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                     enum amd_powergating_state state)
 {
        return 0;
index 448f9e742983f3ef0c5fccc18d85f0c2449aa08e..5760fa06197ab10e37553711966f3994ef805d4f 100644 (file)
@@ -3855,7 +3855,7 @@ static int psp_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int psp_set_powergating_state(void *handle,
+static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                     enum amd_powergating_state state)
 {
        return 0;
index 8bf28d33680753be420f3b4f2b1c0a4ff10f4287..1bd804a8fdb581f36a2262ca6e70950c1daac57e 100644 (file)
@@ -638,7 +638,7 @@ static int amdgpu_vkms_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int amdgpu_vkms_set_powergating_state(void *handle,
+static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 110b120d7375d013ffce806e71c1f4ca9a0b17ec..fffca491e3a1e91ce446f63bee03f9b53215fe76 100644 (file)
@@ -652,10 +652,10 @@ static int vpe_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int vpe_set_powergating_state(void *handle,
+static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                     enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        struct amdgpu_vpe *vpe = &adev->vpe;
 
        if (!adev->pm.dpm_enabled)
index e2cb1f080e882314b8759d9c08e7c04b8dc50d5e..b5055181b050051b02bfc5cfaf99a4dfc5e8b2ae 100644 (file)
@@ -2167,7 +2167,7 @@ static int cik_common_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int cik_common_set_powergating_state(void *handle,
+static int cik_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                            enum amd_powergating_state state)
 {
        return 0;
index 1da17755ad538e9884f05b28900533c2d20c2f28..c49482793c12cf46e9bf9cec577df76c8c6e84e7 100644 (file)
@@ -408,7 +408,7 @@ static int cik_ih_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int cik_ih_set_powergating_state(void *handle,
+static int cik_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index ede1a028d48d54805214a73b66477ce71c07daee..8da334c71419a404511ece7297882b3034abde95 100644 (file)
@@ -1204,7 +1204,7 @@ static int cik_sdma_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int cik_sdma_set_powergating_state(void *handle,
+static int cik_sdma_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index d72973bd570dfd3144f80010f569b3a7d87ba7b7..67554e3223869dd95fb7a06b7d4c2cb21a8c700d 100644 (file)
@@ -405,7 +405,7 @@ static int cz_ih_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int cz_ih_set_powergating_state(void *handle,
+static int cz_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        // TODO
index 5098c50d54c85a147cc582ab42840c3868edf8b5..cd874f9e9a70bb656ba1eb9bebb84539f302c544 100644 (file)
@@ -3308,7 +3308,7 @@ static int dce_v10_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int dce_v10_0_set_powergating_state(void *handle,
+static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index c5680ff4ab9fd8f2127c55f83e6d1562b3430e5d..ec908b524f61676dd5c5842faefa64440aee1d55 100644 (file)
@@ -3440,7 +3440,7 @@ static int dce_v11_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int dce_v11_0_set_powergating_state(void *handle,
+static int dce_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index eb7de9122d99f7208e3ca5b1c86ecd10766be5b1..ee7b69a63f1710b323deadeeca0f30f5294a2cf9 100644 (file)
@@ -3130,7 +3130,7 @@ static int dce_v6_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int dce_v6_0_set_powergating_state(void *handle,
+static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 04b79ff87f756c75dba16fa34ef115bea74cf805..cc4f986bd5339aba0f7e667abf652789eca855a8 100644 (file)
@@ -3218,7 +3218,7 @@ static int dce_v8_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int dce_v8_0_set_powergating_state(void *handle,
+static int dce_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index f18522b0b9fe170dd43bde5dc1c507995c7aabaf..d8c4e2132cc7b556fe40007681bcb23856e79e3d 100644 (file)
@@ -3673,7 +3673,7 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
                                               unsigned int vmid);
 
-static int gfx_v10_0_set_powergating_state(void *handle,
+static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state);
 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 {
@@ -7453,7 +7453,7 @@ static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
         * otherwise the gfxoff disallowing will be failed to set.
         */
        if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
-               gfx_v10_0_set_powergating_state(ip_block->adev, AMD_PG_STATE_UNGATE);
+               gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
 
        if (!adev->no_hw_access) {
                if (amdgpu_async_gfx_ring) {
@@ -8341,10 +8341,10 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
        .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
 };
 
-static int gfx_v10_0_set_powergating_state(void *handle,
+static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        bool enable = (state == AMD_PG_STATE_GATE);
 
        if (amdgpu_sriov_vf(adev))
index 00eff426418fe37c340549370b8609ab63bf16ef..c4b62e1610891ded5b3ba401c6665f97abd14b2b 100644 (file)
@@ -5456,10 +5456,10 @@ static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
        amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 }
 
-static int gfx_v11_0_set_powergating_state(void *handle,
+static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                           enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        bool enable = (state == AMD_PG_STATE_GATE);
 
        if (amdgpu_sriov_vf(adev))
index 8a8b55c332c5ab39c5d1c4ebbef7b829fb3f51ee..1330476ba64bc8350bbaeac40be5fa17a814dc6a 100644 (file)
@@ -3862,10 +3862,10 @@ static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
 }
 #endif
 
-static int gfx_v12_0_set_powergating_state(void *handle,
+static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                           enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        bool enable = (state == AMD_PG_STATE_GATE);
 
        if (amdgpu_sriov_vf(adev))
index 41f50bf380c4058af9768b52ea2f31c67975ad78..2e1e8a49c66e502a47998bd864294c30eaa40612 100644 (file)
@@ -3395,11 +3395,11 @@ static int gfx_v6_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int gfx_v6_0_set_powergating_state(void *handle,
+static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        bool gate = false;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (state == AMD_PG_STATE_GATE)
                gate = true;
index 824d5913103b37e3872e3b47079f7374ff0991fa..0124f86f8e63d8d2b48a700bf6c6f025612611d7 100644 (file)
@@ -4869,11 +4869,11 @@ static int gfx_v7_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int gfx_v7_0_set_powergating_state(void *handle,
+static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        bool gate = false;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (state == AMD_PG_STATE_GATE)
                gate = true;
index 5894755b151ac121b19a84f6be78297c38468ab5..f2cc3f562d644c0bbdebe53ab2f5c59652e017e1 100644 (file)
@@ -5365,10 +5365,10 @@ static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
        }
 }
 
-static int gfx_v8_0_set_powergating_state(void *handle,
+static int gfx_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        bool enable = (state == AMD_PG_STATE_GATE);
 
        if (amdgpu_sriov_vf(adev))
index 4806a6ae7d43390cd2e935faf34569091f392155..b4e8bb4fcd7f3b9ff035b4168de6121022eb17fd 100644 (file)
@@ -5230,10 +5230,10 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
        .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
 };
 
-static int gfx_v9_0_set_powergating_state(void *handle,
+static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        bool enable = (state == AMD_PG_STATE_GATE);
 
        switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
index 558c2cf2a2c7b09d193b8bf9b27139604faa779f..98802fb7dd5fba6ccd8df1a0a049ae9dad2d9b5f 100644 (file)
@@ -2768,7 +2768,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
        .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
 };
 
-static int gfx_v9_4_3_set_powergating_state(void *handle,
+static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 697599c46240ed9b7190765f4d48211ebc2f9fbf..73822631069002924d4d693168208ec0be5b3820 100644 (file)
@@ -1131,7 +1131,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
                athub_v2_0_get_clockgating(adev, flags);
 }
 
-static int gmc_v10_0_set_powergating_state(void *handle,
+static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                           enum amd_powergating_state state)
 {
        return 0;
index f893ab4c14df353ff345e9d72bdd398cacd8f1dc..b73cd4f9df48b87e13422b010b1c5c131efdd685 100644 (file)
@@ -1018,7 +1018,7 @@ static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
        athub_v3_0_get_clockgating(adev, flags);
 }
 
-static int gmc_v11_0_set_powergating_state(void *handle,
+static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                           enum amd_powergating_state state)
 {
        return 0;
index d22b027fd0bb8f5a58dcb260efc08ffb55540849..0ed26d24fc9bdb1cf8a5d80996957abc3911ee48 100644 (file)
@@ -1002,7 +1002,7 @@ static void gmc_v12_0_get_clockgating_state(void *handle, u64 *flags)
        athub_v4_1_0_get_clockgating(adev, flags);
 }
 
-static int gmc_v12_0_set_powergating_state(void *handle,
+static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                           enum amd_powergating_state state)
 {
        return 0;
index ca000b3d1afcd19309e8c33313d17325b50c2760..8575b0219e8db60a14da56882baaf46ad32aaefd 100644 (file)
@@ -1100,7 +1100,7 @@ static int gmc_v6_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int gmc_v6_0_set_powergating_state(void *handle,
+static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index b6016f11956ec1abfb32c7b29b5e1f5f1c0e3392..f39eb2d34703ba0d659dbec7321d671922704bc3 100644 (file)
@@ -1337,7 +1337,7 @@ static int gmc_v7_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int gmc_v7_0_set_powergating_state(void *handle,
+static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 12d5967ecd45fe974e064d8e1392c8d020210d32..20a6d6e192eb753be7ed07061652865897192de0 100644 (file)
@@ -1679,7 +1679,7 @@ static int gmc_v8_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int gmc_v8_0_set_powergating_state(void *handle,
+static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 50c5da3020cb317befab39e15ff98fb7283d1deb..0b052068b5002604e0c4f0a9cabf9e90ceed2de7 100644 (file)
@@ -2565,7 +2565,7 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
        athub_v1_0_get_clockgating(adev, flags);
 }
 
-static int gmc_v9_0_set_powergating_state(void *handle,
+static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                        enum amd_powergating_state state)
 {
        return 0;
index 7f45e93c0397b304ddaff74012ec936900650f58..be3a578596ae56ab8c4fa1b7511990fc91e2d642 100644 (file)
@@ -398,7 +398,7 @@ static int iceland_ih_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int iceland_ih_set_powergating_state(void *handle,
+static int iceland_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 38f953fd65d9df535aef333ff7d6c49b56e931cc..b004dc88cbb0ec3597316f6a52c29c6a786ffc57 100644 (file)
@@ -756,10 +756,10 @@ static void ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
        WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
 }
 
-static int ih_v6_0_set_powergating_state(void *handle,
+static int ih_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                         enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        bool enable = (state == AMD_PG_STATE_GATE);
 
        if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
index 61381e0c379514473634d5578037c5b49da6fe13..27d9d49657575d12af4a4a4121c539fe69037454 100644 (file)
@@ -737,10 +737,10 @@ static void ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,
        WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
 }
 
-static int ih_v6_1_set_powergating_state(void *handle,
+static int ih_v6_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                         enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        bool enable = (state == AMD_PG_STATE_GATE);
 
        if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
index d2428cf5d3858b1dd0fde8627a575d6ee7e13145..d37f5a813007ea4170f79e15d1367e7f7be8f1b6 100644 (file)
@@ -727,10 +727,10 @@ static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
        WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
 }
 
-static int ih_v7_0_set_powergating_state(void *handle,
+static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                         enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        bool enable = (state == AMD_PG_STATE_GATE);
 
        if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
index 6e29b69894a57de6b49bd6f5b613caea04990afb..6dc4a1d5c0f4c562a4f76cd12a6327c590fe98e4 100644 (file)
@@ -35,7 +35,7 @@
 
 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v2_0_set_powergating_state(void *handle,
+static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
 
 /**
@@ -154,7 +154,7 @@ static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
 
        if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
              RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
-               jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+               jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
 
        return 0;
 }
@@ -692,10 +692,10 @@ static int jpeg_v2_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int jpeg_v2_0_set_powergating_state(void *handle,
+static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                        enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if (state == adev->jpeg.cur_state)
index 9ac421486f05fde3d1b5bca4d8e523c0da2887d4..105b81e88fd808179aac57977106269d4b5081c6 100644 (file)
@@ -38,7 +38,7 @@
 
 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v2_5_set_powergating_state(void *handle,
+static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
 
@@ -219,7 +219,7 @@ static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
 
                if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
                      RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
-                       jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                       jpeg_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
 
                if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
                        amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
@@ -541,10 +541,10 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int jpeg_v2_5_set_powergating_state(void *handle,
+static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if (state == adev->jpeg.cur_state)
index e0df6800502ca8e7ac4f3497a46c9a7543e477d4..3ee2502361a2ffcce664cdcd95aae81414767c54 100644 (file)
@@ -36,7 +36,7 @@
 
 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v3_0_set_powergating_state(void *handle,
+static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
 
 /**
@@ -168,7 +168,7 @@ static int jpeg_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
 
        if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
              RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
-               jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+               jpeg_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
 
        return 0;
 }
@@ -483,10 +483,10 @@ static int jpeg_v3_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int jpeg_v3_0_set_powergating_state(void *handle,
+static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if(state == adev->jpeg.cur_state)
index eca1963c33b6bf5f109bc965f289ffbfa85854d4..94f713f502eb4b28d56320ef490457161ac49596 100644 (file)
@@ -39,7 +39,7 @@
 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);
 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v4_0_set_powergating_state(void *handle,
+static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);
 
@@ -206,7 +206,7 @@ static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
        if (!amdgpu_sriov_vf(adev)) {
                if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
                        RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
-                       jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                       jpeg_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
        }
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
                amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
@@ -652,10 +652,10 @@ static int jpeg_v4_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int jpeg_v4_0_set_powergating_state(void *handle,
+static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if (amdgpu_sriov_vf(adev)) {
index 67b51bcbacd19772903ea5b189269ec1d2986a20..921acef89e960f3b27b39559abc85018d0511119 100644 (file)
@@ -43,7 +43,7 @@ enum jpeg_engin_status {
 
 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v4_0_3_set_powergating_state(void *handle,
+static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
@@ -379,7 +379,7 @@ static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
 
        if (!amdgpu_sriov_vf(adev)) {
                if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
-                       ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                       ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
        }
 
        return ret;
@@ -968,10 +968,10 @@ static int jpeg_v4_0_3_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int jpeg_v4_0_3_set_powergating_state(void *handle,
+static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if (amdgpu_sriov_vf(adev)) {
index 1d9e3b101c3a3225bdb8f181d88746adafc17372..2240cf6600736f67eb4f5c71de7f71165478f403 100644 (file)
@@ -48,7 +48,7 @@
 
 static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v4_0_5_set_powergating_state(void *handle,
+static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
 
 static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);
@@ -236,7 +236,7 @@ static int jpeg_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
                if (!amdgpu_sriov_vf(adev)) {
                        if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
                            RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))
-                               jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                               jpeg_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
                }
        }
        return 0;
@@ -684,10 +684,10 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int jpeg_v4_0_5_set_powergating_state(void *handle,
+static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if (amdgpu_sriov_vf(adev)) {
index 58fb1e5fa89c481fc5411189762f88bd1b347c81..2a929d89f42e668795c54f61fbd74086d13dc4ce 100644 (file)
@@ -36,7 +36,7 @@
 
 static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v5_0_0_set_powergating_state(void *handle,
+static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
 
 /**
@@ -172,7 +172,7 @@ static int jpeg_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
 
        if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
              RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
-               jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+               jpeg_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
 
        return 0;
 }
@@ -577,10 +577,10 @@ static int jpeg_v5_0_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int jpeg_v5_0_0_set_powergating_state(void *handle,
+static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if (state == adev->jpeg.cur_state)
index 0820ed62e2e8ed7e7eb2d1db008511da5face99f..f51b5dae3701f9341e7e81bafbecf7a085db579f 100644 (file)
@@ -677,7 +677,7 @@ static int navi10_ih_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int navi10_ih_set_powergating_state(void *handle,
+static int navi10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                           enum amd_powergating_state state)
 {
        return 0;
index 3bad565ded73d04010f96082843c3af10f403015..c6d843cc9423ab823cbe5361e6450f559e17ccb5 100644 (file)
@@ -1070,7 +1070,7 @@ static int nv_common_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int nv_common_set_powergating_state(void *handle,
+static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                           enum amd_powergating_state state)
 {
        /* TODO */
index 7948d74f872256bb43bd2d7e899aef0889a6d259..0c32e614d8e0b0fd6939eb37b4473e4419e600dd 100644 (file)
@@ -1087,7 +1087,7 @@ static int sdma_v2_4_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int sdma_v2_4_set_powergating_state(void *handle,
+static int sdma_v2_4_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 9a3d729545a7c6712888996e22e81fdba09ebaaf..18f29e2be82894e33369d7851358cf33f6eb86f9 100644 (file)
@@ -1506,7 +1506,7 @@ static int sdma_v3_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int sdma_v3_0_set_powergating_state(void *handle,
+static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 3f59595577276ff7376ca56e207b3f4bc9271b8c..a2f5f2be699b7df02d9e47a30416b2df81c564d9 100644 (file)
@@ -2312,10 +2312,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int sdma_v4_0_set_powergating_state(void *handle,
+static int sdma_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
        case IP_VERSION(4, 1, 0):
index a050773df44f63fc940ad2ccbd90ea4de4cd5a04..ced17a6fe77a82fd1fdb3514a63f3e077a004c61 100644 (file)
@@ -1892,7 +1892,7 @@ static int sdma_v4_4_2_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int sdma_v4_4_2_set_powergating_state(void *handle,
+static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index fa9b4093495702a06cbfb18701023e03f2a4db21..07e9a3eec7e5372ca319fc1fe8655df5e08d83f2 100644 (file)
@@ -1877,7 +1877,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int sdma_v5_0_set_powergating_state(void *handle,
+static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index ba5160399ab2a03e80c6aa4f57264febd5f28e11..d2e9a4db8b021ccff1dbe5f3c1b368aef4d71d39 100644 (file)
@@ -1841,7 +1841,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int sdma_v5_2_set_powergating_state(void *handle,
+static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index d46128b0ec9202fdcd27f9423826406b3c49b261..f48c6aeb2af2a7be524d1cc1777b1acfac7c9557 100644 (file)
@@ -1607,7 +1607,7 @@ static int sdma_v6_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int sdma_v6_0_set_powergating_state(void *handle,
+static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index d2ce6b6a7ff64e0d07a122eb158b42a77916c574..1a5fc7bc7289c4279990fc1a0c6e23a7ef4d1cae 100644 (file)
@@ -1530,7 +1530,7 @@ static int sdma_v7_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int sdma_v7_0_set_powergating_state(void *handle,
+static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 00f63d3fbea7157e486350018e2c3e975cbaa1d0..e32615630cca6539c876010921de1003a09e962f 100644 (file)
@@ -2655,7 +2655,7 @@ static int si_common_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int si_common_set_powergating_state(void *handle,
+static int si_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                            enum amd_powergating_state state)
 {
        return 0;
index 47647a6083e8b11acb8b957c181f6b592382c145..4b278904cfd99b1e02a44d5168023dc64a5c80fa 100644 (file)
@@ -672,12 +672,12 @@ static int si_dma_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int si_dma_set_powergating_state(void *handle,
+static int si_dma_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        u32 tmp;
 
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        WREG32(DMA_PGFSM_WRITE,  0x00002000);
        WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
index 2ec1ebe4db11fc5edf2a5b3be9301099f3d12073..ec756d24aaa7aac9a15d099c7b6286cba82f3441 100644 (file)
@@ -269,7 +269,7 @@ static int si_ih_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int si_ih_set_powergating_state(void *handle,
+static int si_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index ede072758dabf1569993980717df8ba5c5322708..1eb6a226ff10becb7f6f9f9e28c3583dcf768fbe 100644 (file)
@@ -1473,7 +1473,7 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
                adev->df.funcs->get_clockgating_state(adev, flags);
 }
 
-static int soc15_common_set_powergating_state(void *handle,
+static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                            enum amd_powergating_state state)
 {
        /* todo */
index d6999835918fa0d8d4d9fe0f6a52cb56af6f4804..b270037f0b9bd23feea2875b7feb3c3b331f6155 100644 (file)
@@ -954,10 +954,10 @@ static int soc21_common_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int soc21_common_set_powergating_state(void *handle,
+static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                           enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
        case IP_VERSION(6, 0, 0):
index be96de92b2f5df99343904db5acb3374d680aac1..ee96d9e303a88d4963c36849b7989d515c964219 100644 (file)
@@ -542,10 +542,10 @@ static int soc24_common_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int soc24_common_set_powergating_state(void *handle,
+static int soc24_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                              enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
        case IP_VERSION(7, 0, 0):
index 5a04a677013808405162cfe76960eb33190f4952..7c02eb0e1540f7c7a9d03f5d94243c6ac8e2e7b4 100644 (file)
@@ -454,7 +454,7 @@ static int tonga_ih_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int tonga_ih_set_powergating_state(void *handle,
+static int tonga_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index bdbca25d80c498bd1e4376263cf5ea26acca0118..c66fe0c8d5e9e449a68e9cdbb50ac07f65e970ff 100644 (file)
@@ -796,7 +796,7 @@ static int uvd_v3_1_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int uvd_v3_1_set_powergating_state(void *handle,
+static int uvd_v3_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index a836dc9cfcadeba8651e7192a3914d73f38c55b5..1f3da607c0d62613e53bc19cd0d138d0784c0350 100644 (file)
@@ -714,7 +714,7 @@ static int uvd_v4_2_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int uvd_v4_2_set_powergating_state(void *handle,
+static int uvd_v4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        /* This doesn't actually powergate the UVD block.
@@ -724,7 +724,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
         * revisit this when there is a cleaner line between
         * the smc and the hw blocks
         */
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (state == AMD_PG_STATE_GATE) {
                uvd_v4_2_stop(adev);
index ab55fae3569e4918be0dc23d900850b9be6087c9..50577cc79dcb5285db1a5fe24f20ee65867ea4cf 100644 (file)
@@ -817,7 +817,7 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int uvd_v5_0_set_powergating_state(void *handle,
+static int uvd_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        /* This doesn't actually powergate the UVD block.
@@ -827,7 +827,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,
         * revisit this when there is a cleaner line between
         * the smc and the hw blocks
         */
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret = 0;
 
        if (state == AMD_PG_STATE_GATE) {
index 39f8c3d3a135f448da8fa578c7c21505dd0cb3e4..4f5dc46802e20cc98eb740c6d59f82622e3ee6e1 100644 (file)
@@ -1476,7 +1476,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int uvd_v6_0_set_powergating_state(void *handle,
+static int uvd_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        /* This doesn't actually powergate the UVD block.
@@ -1486,7 +1486,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
         * revisit this when there is a cleaner line between
         * the smc and the hw blocks
         */
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret = 0;
 
        WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
index c1ed91b39415438025410c61fd151be534555294..552866990db2f9a2bbbb877fceb863985c839299 100644 (file)
@@ -596,7 +596,7 @@ static int vce_v2_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int vce_v2_0_set_powergating_state(void *handle,
+static int vce_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        /* This doesn't actually powergate the VCE block.
@@ -606,7 +606,7 @@ static int vce_v2_0_set_powergating_state(void *handle,
         * revisit this when there is a cleaner line between
         * the smc and the hw blocks
         */
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (state == AMD_PG_STATE_GATE)
                return vce_v2_0_stop(adev);
index 6bb318a06f1976e7cbdb07bafde331843189bcba..6f4a2476b9fd338b4a7f92dbe12a90a9794b9396 100644 (file)
@@ -801,7 +801,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int vce_v3_0_set_powergating_state(void *handle,
+static int vce_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        /* This doesn't actually powergate the VCE block.
@@ -811,7 +811,7 @@ static int vce_v3_0_set_powergating_state(void *handle,
         * revisit this when there is a cleaner line between
         * the smc and the hw blocks
         */
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret = 0;
 
        if (state == AMD_PG_STATE_GATE) {
index 79ee555768a589d9e357a9cd195202f44cfc9319..04bfa3b59f7580bde55e4c4a140da7c1c3650965 100644 (file)
@@ -691,7 +691,7 @@ static int vce_v4_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int vce_v4_0_set_powergating_state(void *handle,
+static int vce_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        /* This doesn't actually powergate the VCE block.
@@ -701,7 +701,7 @@ static int vce_v4_0_set_powergating_state(void *handle,
         * revisit this when there is a cleaner line between
         * the smc and the hw blocks
         */
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (state == AMD_PG_STATE_GATE)
                return vce_v4_0_stop(adev);
index 7ad2ab3affe430795cf8a82ba86e61caebbe9bfa..32b0159953f3533fb43c952ebadb4ee123146b01 100644 (file)
@@ -85,7 +85,8 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev);
 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
+static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
+                               enum amd_powergating_state state);
 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
                                int inst_idx, struct dpg_pause_state *new_state);
 
@@ -281,7 +282,7 @@ static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
        if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
                (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
                 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
-               vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+               vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
        }
 
        return 0;
@@ -1799,7 +1800,7 @@ static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t coun
        }
 }
 
-static int vcn_v1_0_set_powergating_state(void *handle,
+static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        /* This doesn't actually powergate the VCN block.
@@ -1810,7 +1811,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
         * the smc and the hw blocks
         */
        int ret;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (state == adev->vcn.cur_state)
                return 0;
index f34cab96d0b473ff4188e9013adc90fd4010f091..798d06563c65a1a94330299625595f82cc6fd47b 100644 (file)
@@ -92,7 +92,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v2_0_set_powergating_state(void *handle,
+static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
                                int inst_idx, struct dpg_pause_state *new_state);
@@ -318,7 +318,7 @@ static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
        if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
            (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
              RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
-               vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+               vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
 
        return 0;
 }
@@ -1796,7 +1796,7 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
 }
 
 
-static int vcn_v2_0_set_powergating_state(void *handle,
+static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        /* This doesn't actually powergate the VCN block.
@@ -1807,7 +1807,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
         * the smc and the hw blocks
         */
        int ret;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (amdgpu_sriov_vf(adev)) {
                adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
index beab2c24042d81e53e290dcbd03429a384176bd3..d00406e057d7a4692ce4763c2a438f1baf7959ee 100644 (file)
@@ -95,7 +95,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {
 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v2_5_set_powergating_state(void *handle,
+static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
                                int inst_idx, struct dpg_pause_state *new_state);
@@ -399,7 +399,7 @@ static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
                if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
                    (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
                     RREG32_SOC15(VCN, i, mmUVD_STATUS)))
-                       vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                       vcn_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
 
                if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
                        amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
@@ -1825,10 +1825,10 @@ static int vcn_v2_5_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int vcn_v2_5_set_powergating_state(void *handle,
+static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if (amdgpu_sriov_vf(adev))
index 6d047257490c68b7978ee4cdd44543e423324a3e..d761bc7c31bce3c324f9d3f1179826ebacb9da38 100644 (file)
@@ -105,7 +105,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v3_0_set_powergating_state(void *handle,
+static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                        enum amd_powergating_state state);
 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
                        int inst_idx, struct dpg_pause_state *new_state);
@@ -430,9 +430,9 @@ static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
 
                if (!amdgpu_sriov_vf(adev)) {
                        if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
-                                       (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
-                                        RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
-                               vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                               (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+                                RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
+                               vcn_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
                        }
                }
        }
@@ -2159,10 +2159,10 @@ static int vcn_v3_0_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int vcn_v3_0_set_powergating_state(void *handle,
+static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        /* for SRIOV, guest should not control VCN Power-gating
index fa1d81b94172f7f5988b4955e7ba8cad21966f3d..53338f71d372cc1f2cf864067317d492cf7e66fd 100644 (file)
@@ -96,7 +96,7 @@ static int amdgpu_ih_clientid_vcns[] = {
 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v4_0_set_powergating_state(void *handle,
+static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
         enum amd_powergating_state state);
 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
         int inst_idx, struct dpg_pause_state *new_state);
@@ -366,9 +366,9 @@ static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
                        continue;
                if (!amdgpu_sriov_vf(adev)) {
                        if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
-                        (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
-                                RREG32_SOC15(VCN, i, regUVD_STATUS))) {
-                        vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                               (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+                                RREG32_SOC15(VCN, i, regUVD_STATUS))) {
+                               vcn_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
                        }
                }
                if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
@@ -2046,9 +2046,10 @@ static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_sta
  *
  * Set VCN block powergating state
  */
-static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
+static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
+                                         enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        /* for SRIOV, guest should not control VCN Power-gating
index 9da9a99d465a796722319e6048349fd60c9fb164..53b4a3a2890b747a523ff9295cd6d3ace0aec6d4 100644 (file)
@@ -87,7 +87,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v4_0_3_set_powergating_state(void *handle,
+static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
                enum amd_powergating_state state);
 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
                int inst_idx, struct dpg_pause_state *new_state);
@@ -349,7 +349,7 @@ static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
        cancel_delayed_work_sync(&adev->vcn.idle_work);
 
        if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
-               vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
+               vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
 
        return 0;
 }
@@ -1653,10 +1653,10 @@ static int vcn_v4_0_3_set_clockgating_state(void *handle,
  *
  * Set VCN block powergating state
  */
-static int vcn_v4_0_3_set_powergating_state(void *handle,
+static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        /* for SRIOV, guest should not control VCN Power-gating
index f0ec8bc031c64f82a9c6d142ccfc78d84b3a2c40..13c0fc9f98943886afc9408f890fd0f412b30922 100644 (file)
@@ -95,7 +95,7 @@ static int amdgpu_ih_clientid_vcns[] = {
 
 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v4_0_5_set_powergating_state(void *handle,
+static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
                enum amd_powergating_state state);
 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
                int inst_idx, struct dpg_pause_state *new_state);
@@ -309,7 +309,7 @@ static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
                        if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
                                (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
                                RREG32_SOC15(VCN, i, regUVD_STATUS))) {
-                               vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                               vcn_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
                        }
                }
        }
@@ -1531,9 +1531,10 @@ static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_s
  *
  * Set VCN block powergating state
  */
-static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_state state)
+static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
+               enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if (state == adev->vcn.cur_state)
index bc8324966469fc09f327b8523d36afb238758357..99d60088a24c1bbb1206e8331c3b85a757b0e608 100644 (file)
@@ -78,7 +78,7 @@ static int amdgpu_ih_clientid_vcns[] = {
 
 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v5_0_0_set_powergating_state(void *handle,
+static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                enum amd_powergating_state state);
 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
                int inst_idx, struct dpg_pause_state *new_state);
@@ -283,7 +283,7 @@ static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
                        if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
                                (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
                                RREG32_SOC15(VCN, i, regUVD_STATUS))) {
-                               vcn_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                               vcn_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
                        }
                }
        }
@@ -1268,9 +1268,10 @@ static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_s
  *
  * Set VCN block powergating state
  */
-static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_state state)
+static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
+               enum amd_powergating_state state)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        int ret;
 
        if (state == adev->vcn.cur_state)
index 0fedadd0a6a43e30034401377f850aaa24728072..039f1ae2df023879d6f75a45da3cc39c4d74bfd2 100644 (file)
@@ -616,7 +616,7 @@ static int vega10_ih_set_clockgating_state(void *handle,
 
 }
 
-static int vega10_ih_set_powergating_state(void *handle,
+static int vega10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index 1c9aff742e4328fcfee8b677c621a59d62805f7b..a8e88c9f6ae52ccad5c92578ba803eff29cbfb00 100644 (file)
@@ -708,7 +708,7 @@ static int vega20_ih_set_clockgating_state(void *handle,
 
 }
 
-static int vega20_ih_set_powergating_state(void *handle,
+static int vega20_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index a83505815d398cd39271e4ce27adaf9cc655c7f2..5b945d4d81b7a1700488bbf338791408a5f3f529 100644 (file)
@@ -1988,7 +1988,7 @@ static int vi_common_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int vi_common_set_powergating_state(void *handle,
+static int vi_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                            enum amd_powergating_state state)
 {
        return 0;
index 48be917e7bc550065acb383cd239c9d5c2ea7d83..e27a5667852d941add5a5219e15fa6307c689cbd 100644 (file)
@@ -961,7 +961,7 @@ static int dm_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int dm_set_powergating_state(void *handle,
+static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
                  enum amd_powergating_state state)
 {
        return 0;
index 7eefcb0f50703f7b7e9a4146678b79520437cc67..0f20abbfd38195f03e2ee7a2e67b05a6cecca8a2 100644 (file)
@@ -403,7 +403,7 @@ struct amd_ip_funcs {
        int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
        int (*set_clockgating_state)(void *handle,
                                     enum amd_clockgating_state state);
-       int (*set_powergating_state)(void *handle,
+       int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
                                     enum amd_powergating_state state);
        void (*get_clockgating_state)(void *handle, u64 *flags);
        void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
index f0f81ecd9ad6a563e9d6dfd0f80503e11f85a5eb..bb8b0799ab7c8107b2e4a844335935a43d5d1a76 100644 (file)
@@ -3183,7 +3183,7 @@ static int kv_dpm_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int kv_dpm_set_powergating_state(void *handle,
+static int kv_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state)
 {
        return 0;
index ee23a0f897c50c13b2a28cc009ad0703cff6266f..ed8f755e9ff6687f8746a336e968fc3b6b717062 100644 (file)
@@ -7855,7 +7855,7 @@ static int si_dpm_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int si_dpm_set_powergating_state(void *handle,
+static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                        enum amd_powergating_state state)
 {
        return 0;
index 90500b419d604b10a1cf2aafdcfb76fc4d3a1803..a3d1c5aa3b3ee04713e2f6d9216a2ef2e7d0fc93 100644 (file)
@@ -244,7 +244,7 @@ static bool pp_is_idle(void *handle)
        return false;
 }
 
-static int pp_set_powergating_state(void *handle,
+static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                    enum amd_powergating_state state)
 {
        return 0;
index dc372d39cb8d14fced5c538471bd5c712baf88fa..cb89656864aa0fbd21bed270cdb561a2b7e08934 100644 (file)
@@ -2208,7 +2208,7 @@ static int smu_set_clockgating_state(void *handle,
        return 0;
 }
 
-static int smu_set_powergating_state(void *handle,
+static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                     enum amd_powergating_state state)
 {
        return 0;