+2019-05-19 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/constraints.md (define_register_constraint "wo"):
+ Delete.
+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
+ RS6000_CONSTRAINT_wo.
+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
+ (rs6000_init_hard_regno_mode_ok): Adjust.
+ * config/rs6000/rs6000.md: Replace "wo" constraint by "wa" with "p9v".
+ * config/rs6000/altivec.md: Ditto.
+ * doc/md.texi (Machine Constraints): Adjust.
+
2019-05-18 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin-c.c (darwin_register_objc_includes): Do not
;; Slightly prefer vperm, since the target does not overlap the source
(define_insn "altivec_vperm_<mode>_direct"
- [(set (match_operand:VM 0 "register_operand" "=v,?wo")
- (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo")
+ [(set (match_operand:VM 0 "register_operand" "=v,?wa")
+ (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa")
(match_operand:VM 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wo")]
+ (match_operand:V16QI 3 "register_operand" "v,wa")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecperm")
+ (set_attr "isa" "*,p9v")])
(define_insn "altivec_vperm_v8hiv16qi"
- [(set (match_operand:V16QI 0 "register_operand" "=v,?wo")
- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,wo")
+ [(set (match_operand:V16QI 0 "register_operand" "=v,?wa")
+ (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,wa")
(match_operand:V8HI 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wo")]
+ (match_operand:V16QI 3 "register_operand" "v,wa")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecperm")
+ (set_attr "isa" "*,p9v")])
(define_expand "altivec_vperm_<mode>_uns"
[(set (match_operand:VM 0 "register_operand")
})
(define_insn "*altivec_vperm_<mode>_uns_internal"
- [(set (match_operand:VM 0 "register_operand" "=v,?wo")
- (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo")
+ [(set (match_operand:VM 0 "register_operand" "=v,?wa")
+ (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa")
(match_operand:VM 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wo")]
+ (match_operand:V16QI 3 "register_operand" "v,wa")]
UNSPEC_VPERM_UNS))]
"TARGET_ALTIVEC"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecperm")
+ (set_attr "isa" "*,p9v")])
(define_expand "vec_permv16qi"
[(set (match_operand:V16QI 0 "register_operand")
})
(define_insn "*altivec_vpermr_<mode>_internal"
- [(set (match_operand:VM 0 "register_operand" "=v,?wo")
- (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo")
+ [(set (match_operand:VM 0 "register_operand" "=v,?wa")
+ (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa")
(match_operand:VM 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wo")]
+ (match_operand:V16QI 3 "register_operand" "v,wa")]
UNSPEC_VPERMR))]
"TARGET_P9_VECTOR"
"@
vpermr %0,%1,%2,%3
xxpermr %x0,%x1,%x3"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecperm")
+ (set_attr "isa" "*,p9v")])
(define_insn "altivec_vrfip" ; ceil
[(set (match_operand:V4SF 0 "register_operand" "=v")
"")
(define_insn "vperm_v8hiv4si"
- [(set (match_operand:V4SI 0 "register_operand" "=v,?wo")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,wo")
+ [(set (match_operand:V4SI 0 "register_operand" "=v,?wa")
+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,wa")
(match_operand:V4SI 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wo")]
+ (match_operand:V16QI 3 "register_operand" "v,wa")]
UNSPEC_VPERMSI))]
"TARGET_ALTIVEC"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecperm")
+ (set_attr "isa" "*,p9v")])
(define_insn "vperm_v16qiv8hi"
- [(set (match_operand:V8HI 0 "register_operand" "=v,?wo")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,wo")
+ [(set (match_operand:V8HI 0 "register_operand" "=v,?wa")
+ (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,wa")
(match_operand:V8HI 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wo")]
+ (match_operand:V16QI 3 "register_operand" "v,wa")]
UNSPEC_VPERMHI))]
"TARGET_ALTIVEC"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecperm")
+ (set_attr "isa" "*,p9v")])
(define_expand "vec_unpacku_hi_v16qi"
;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode
(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
-(define_register_constraint "wo" "rs6000_constraints[RS6000_CONSTRAINT_wo]"
- "VSX register if the -mpower9-vector option was used or NO_REGS.")
-
(define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]"
"VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.")
"wk reg_class = %s\n"
"wl reg_class = %s\n"
"wm reg_class = %s\n"
- "wo reg_class = %s\n"
"wp reg_class = %s\n"
"wq reg_class = %s\n"
"wr reg_class = %s\n"
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
}
+ /* Support for new D-form instructions. */
if (TARGET_P9_VECTOR)
- {
- /* Support for new D-form instructions. */
- rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
-
- /* Support for ISA 3.0 (power9) vectors. */
- rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
- }
+ rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
/* Support for new direct moves (ISA 3.0 + 64bit). */
if (TARGET_DIRECT_MOVE_128)
RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
RS6000_CONSTRAINT_wm, /* VSX register for direct move */
- RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
[(set_attr "type" "store")])
(define_insn_and_split "bswaphi2_reg"
- [(set (match_operand:HI 0 "gpc_reg_operand" "=&r,wo")
+ [(set (match_operand:HI 0 "gpc_reg_operand" "=&r,wa")
(bswap:HI
- (match_operand:HI 1 "gpc_reg_operand" "r,wo")))
+ (match_operand:HI 1 "gpc_reg_operand" "r,wa")))
(clobber (match_scratch:SI 2 "=&r,X"))]
""
"@
operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
}
[(set_attr "length" "12,4")
- (set_attr "type" "*,vecperm")])
+ (set_attr "type" "*,vecperm")
+ (set_attr "isa" "*,p9v")])
;; We are always BITS_BIG_ENDIAN, so the bit positions below in
;; zero_extract insns do not change for -mlittle.
(define_insn_and_split "bswapsi2_reg"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,wo")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,wa")
(bswap:SI
- (match_operand:SI 1 "gpc_reg_operand" "r,wo")))]
+ (match_operand:SI 1 "gpc_reg_operand" "r,wa")))]
""
"@
#
(const_int -256))))]
""
[(set_attr "length" "12,4")
- (set_attr "type" "*,vecperm")])
+ (set_attr "type" "*,vecperm")
+ (set_attr "isa" "*,p9v")])
;; On systems with LDBRX/STDBRX generate the loads/stores directly, just like
;; we do for L{H,W}BRX and ST{H,W}BRX above. If not, we have to generate more
[(set_attr "type" "store")])
(define_insn "bswapdi2_xxbrd"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=wo")
- (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "wo")))]
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=wa")
+ (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "wa")))]
"TARGET_P9_VECTOR"
"xxbrd %x0,%x1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecperm")
+ (set_attr "isa" "p9v")])
(define_insn "bswapdi2_reg"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
r, wY, Z, ^wb, $wv, ^wi,
- wo, wo, wv, wi, *i, wv,
+ wa, wa, wv, wi, *i, wv,
wv")
(match_operand:DI 1 "input_operand"
"8, 8, 8, 4, 4, 4,
16, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 8,
- 4")])
+ 4")
+ (set_attr "isa"
+ "*, *, *, *, *, *,
+ *, *, *, *, *, *,
+ p9v, p9v, *, *, *, *,
+ *")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand")
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r, r, r, r,
m, ^d, ^d, wY, Z, $wb,
- $wv, ^wi, wo, wo, wv, wi,
+ $wv, ^wi, wa, wa, wv, wi,
wi, wv, wv, r, *h, *h,
?r, ?wg, ?r, ?wj")
4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4,
4, 8, 4, 4, 4, 4,
- 4, 4, 4, 4")])
+ 4, 4, 4, 4")
+ (set_attr "isa"
+ "*, *, *, *, *, *,
+ *, *, *, *, *, *,
+ *, *, p9v, p9v, *, *,
+ *, *, *, *, *, *,
+ *, *, *, *")])
; Some DImode loads are best done as a load of -1 followed by a mask
; instruction.
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, <VSa>, <VSa>, r, we, ?wQ,
- ?&r, ??r, ??Y, <??r>, wo, v,
+ ?&r, ??r, ??Y, <??r>, wa, v,
?<VSa>, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"vecstore, vecload, vecsimple, mffgpr, mftgpr, load,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
-
(set_attr "length"
"4, 4, 4, 8, 4, 8,
8, 8, 8, 8, 4, 4,
- 4, 20, 8, 4, 4")])
+ 4, 20, 8, 4, 4")
+ (set_attr "isa"
+ "*, *, *, *, *, *,
+ *, *, *, *, p9v, *,
+ *, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, <VSa>, <VSa>, ??r, ??Y, <??r>,
- wo, v, ?<VSa>, v, <??r>,
+ wa, v, ?<VSa>, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"vecstore, vecload, vecsimple, load, store, *,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
-
(set_attr "length"
"4, 4, 4, 16, 16, 16,
4, 4, 4, 20, 16,
- 4, 4")])
+ 4, 4")
+ (set_attr "isa"
+ "*, *, *, *, *, *,
+ p9v, *, *, *, *,
+ *, *")])
;; Explicit load/store expanders for the builtin functions
(define_expand "vsx_load_<mode>"
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=d, d, wr, wr")
(vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "gpc_reg_operand" "<VSa>, <VSa>, wm, wo")
+ (match_operand:VSX_D 1 "gpc_reg_operand" "<VSa>, <VSa>, wm, wa")
(parallel
[(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))]
else
gcc_unreachable ();
}
- [(set_attr "type" "veclogical,mftgpr,mftgpr,vecperm")])
+ [(set_attr "type" "veclogical,mftgpr,mftgpr,vecperm")
+ (set_attr "isa" "*,*,*,p9v")])
;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load"
When using any of the register constraints (@code{wa}, @code{wd},
@code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
-@code{wl}, @code{wm}, @code{wo}, @code{wp}, @code{wq}, @code{ws},
+@code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws},
@code{wt}, @code{wu}, @code{wv}, @code{ww}, or @code{wy})
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
@item wn
No register (NO_REGS).
-@item wo
-VSX register to use for ISA 3.0 vector instructions, or NO_REGS.
-
@item wp
VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
projects / thirdparty / gcc.git / commitdiff
