drm/i915/power: convert {SKL, ICL}_PW_CTL_IDX_TO_PG() macros to a function

Add pw_ctl_idx_to_pg() helper function to deduplicate the open-coded
usage of the {SKL,ICL}_PW_CTL_IDX_TO_PG() macros.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/3aa74825db0b900f93b94aa89d0242a354929b85.1750855148.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 9d60dfc4939df0729d49e84b9451b0c6fe91c3f2..4a876fa815bd1e0db60a1d806aa5b076f99e922e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -36,16 +36,15 @@
 
 /*
  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
- * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
- */
-#define  SKL_PW_CTL_IDX_TO_PG(pw_idx)          \
-       ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
-/*
- * PG0 is HW controlled, so doesn't have a corresponding power well control knob
- * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
+ *
+ * {ICL,SKL}_DISP_PW1_IDX..{ICL,SKL}_DISP_PW4_IDX -> PG1..PG4
  */
-#define  ICL_PW_CTL_IDX_TO_PG(pw_idx)          \
-       ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
+static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx)
+{
+       int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1;
+
+       return pw_idx - pw1_idx + SKL_PG1;
+}
 
 struct i915_power_well_regs {
        i915_reg_t bios;
@@ -363,8 +362,7 @@ static void hsw_power_well_enable(struct intel_display *display,
        if (power_well->desc->has_fuses) {
                enum skl_power_gate pg;
 
-               pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
-                                                SKL_PW_CTL_IDX_TO_PG(pw_idx);
+               pg = pw_idx_to_pg(display, pw_idx);
 
                /* Wa_16013190616:adlp */
                if (display->platform.alderlake_p && pg == SKL_PG1)
@@ -388,8 +386,8 @@ static void hsw_power_well_enable(struct intel_display *display,
        if (power_well->desc->has_fuses) {
                enum skl_power_gate pg;
 
-               pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
-                                                SKL_PW_CTL_IDX_TO_PG(pw_idx);
+               pg = pw_idx_to_pg(display, pw_idx);
+
                gen9_wait_for_power_well_fuses(display, pg);
        }