]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
phy: qualcomm: qmp-pcie: define several new registers
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Mon, 21 Oct 2024 10:33:11 +0000 (13:33 +0300)
committerVinod Koul <vkoul@kernel.org>
Sun, 8 Dec 2024 16:00:08 +0000 (21:30 +0530)
Define several registers to be used by PCIe QMP PHYs on v6 platforms.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-5-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h

index 0ca79333d94261610f7274968c96362dcfb1f354..45397cb3c0c6fd2cd989ddc600510589792a3b1a 100644 (file)
@@ -14,4 +14,7 @@
 #define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE    0x20
 #define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS         0x94
 
+#define QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2          0x024
+#define QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2          0x028
+
 #endif
index 08299d2b78f096fa5f9388a4d54ddfa85667b18c..aa5afb921f12c07e0648f69433a2e6e2fb756c07 100644 (file)
@@ -17,6 +17,8 @@
 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG3                0x0cc
 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG6                0x0d8
 #define QPHY_V6_PCS_REFGEN_REQ_CONFIG1         0x0dc
+#define QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB                0x168
+#define QPHY_V6_PCS_G3S2_PRE_GAIN              0x170
 #define QPHY_V6_PCS_RX_SIGDET_LVL              0x188
 #define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L       0x190
 #define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H       0x194
index 23ffcfae9efab4a9e081414f9b3bbd0079d34f18..f47fdc9cecda8c4fe46c83e6449d68c033cd7fe2 100644 (file)
@@ -6,6 +6,7 @@
 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
 #define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
 
+#define QSERDES_V6_TX_BIST_MODE_LANENO                         0x00
 #define QSERDES_V6_TX_CLKBUF_ENABLE                            0x08
 #define QSERDES_V6_TX_TX_EMP_POST1_LVL                         0x0c
 #define QSERDES_V6_TX_TX_DRV_LVL                               0x14