[AArch64] Fix bogus MOVPRFX warning for GPR form of CPY

One of the MOVPRFX tests has:

  output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1'

But X1 and Z1 are not the same register, so the instruction is
actually OK.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
	registers in an instruction prefixed by MOVPRFX.

gas/
	* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
	to be prefixed by MOVPRFX.
	* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 72fac529637103c0923f5bfbdd07acfeb9ba15aa..d11b98099aacb165ab5c0110589c7324944806ef 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
+       to be prefixed by MOVPRFX.
+       * testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
+       * testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
+
 2019-05-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
        Backport from mainline

diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_25.d b/gas/testsuite/gas/aarch64/sve-movprfx_25.d
index 15738564627dbb82676c435b2e3bc5a505948d58..2b4f654823ba4c1d198c3c137e652b551cbdc416 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve-movprfx_25.d
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_25.d
@@ -21,7 +21,7 @@ Disassembly of section .*:
 [^:]+: 04d12461        movprfx z1.d, p1/m, z3.d
 [^:]+: 05e8a441        mov     z1.d, p1/m, x2
 [^:]+: 04d12461        movprfx z1.d, p1/m, z3.d
-[^:]+: 05e8a421        mov     z1.d, p1/m, x1  // note: output register of preceding `movprfx' used as input at operand 3
+[^:]+: 05e8a421        mov     z1.d, p1/m, x1
 [^:]+: 04d12461        movprfx z1.d, p1/m, z3.d
 [^:]+: 05e08441        mov     z1.d, p1/m, d2
 [^:]+: 04d12461        movprfx z1.d, p1/m, z3.d

diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_25.l b/gas/testsuite/gas/aarch64/sve-movprfx_25.l
index ec7e2dbd60e1b22219e01b664427a05b11630e15..259ad555475be41724360786fa744c767c5a0569 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve-movprfx_25.l
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_25.l
@@ -1,5 +1,4 @@
 [^:]*: Assembler messages:
 .*: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `cpy z1.d,p9/m,#12'
 .*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `cpy z1.d,p1/z,#12'
-.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1'
 .*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,d1'

diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_25.s b/gas/testsuite/gas/aarch64/sve-movprfx_25.s
index 58124cee1ca1d567407f6081321703a346459399..0e64763de192edf222083586d1806bfb710cd4b0 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve-movprfx_25.s
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_25.s
@@ -29,7 +29,7 @@ f:
    movprfx z1.d, p1/m, z3.d
    cpy z1.d, p1/m, x2
 
-   /* Not OK, scalar but register z1 and x1 are architecturally the same.  */
+   /* OK, scalar predicated, alias mov.  */
    movprfx z1.d, p1/m, z3.d
    cpy z1.d, p1/m, x1
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 66a8fa3110c80a2d962e48cb1ecbeb3767b2dca1..065b1b9526dde477c31d47e226f879a295e42f86 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
+       registers in an instruction prefixed by MOVPRFX.
+
 2019-04-16  Sudakshina Das  <sudi.das@arm.com>
 
        Backport from mainline.

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 519bcb059644c9d4bea9c79b7c062ce9ecf50818..2d2752fd595c8ff5ec03a3bfe09245e455d11f52 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4902,11 +4902,6 @@ verify_constraints (const struct aarch64_inst *inst,
                  case AARCH64_OPND_Vm:
                  case AARCH64_OPND_Sn:
                  case AARCH64_OPND_Sm:
-                 case AARCH64_OPND_Rn:
-                 case AARCH64_OPND_Rm:
-                 case AARCH64_OPND_Rn_SP:
-                 case AARCH64_OPND_Rt_SP:
-                 case AARCH64_OPND_Rm_SP:
                    if (inst_op.reg.regno == blk_dest.reg.regno)
                      {
                        num_op_used++;