net: stmmac: qcom-ethqos: add rgmii set/clear functions

The driver has a lot of bit manipulation of the RGMII registers. Add
a pair of helpers to set bits and clear bits, converting the various
calls to rgmii_updatel() as appropriate.

Most of the change was done via this sed script:

/rgmii_updatel/ {
	N
	/,$/N
	/mask, / ! {
		s|rgmii_updatel\(([^,]*,\s+([^,]*),\s+)\2,\s+|rgmii_setmask(\1|
		s|rgmii_updatel\(([^,]*,\s+([^,]*),\s+)0,\s+|rgmii_clrmask(\1|
		s|^\s+$||
	}
}

and then formatting tweaked where necessary.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/E1vM2mw-0000000FRTo-0End@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index ae3cf163005be0db45624eec9ca56bff3b92f112..1f84bd821c4eaa769b671a64d5568ffd7f686e3b 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -137,6 +137,18 @@ static void rgmii_updatel(struct qcom_ethqos *ethqos, u32 mask, u32 val,
        rgmii_writel(ethqos, temp, offset);
 }
 
+static void rgmii_setmask(struct qcom_ethqos *ethqos, u32 mask,
+                         unsigned int offset)
+{
+       rgmii_updatel(ethqos, mask, mask, offset);
+}
+
+static void rgmii_clrmask(struct qcom_ethqos *ethqos, u32 mask,
+                         unsigned int offset)
+{
+       rgmii_updatel(ethqos, mask, 0, offset);
+}
+
 static void rgmii_dump(void *priv)
 {
        struct qcom_ethqos *ethqos = priv;
@@ -194,8 +206,7 @@ qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable)
 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
 {
        qcom_ethqos_set_sgmii_loopback(ethqos, true);
-       rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
-                     RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
+       rgmii_setmask(ethqos, RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
 }
 
 static const struct ethqos_emac_por emac_v2_3_0_por[] = {
@@ -304,27 +315,25 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
        u32 val;
 
        /* Set CDR_EN */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
-                     SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
+       rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
 
        /* Set CDR_EXT_EN */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
-                     SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);
+       rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
+                     SDCC_HC_REG_DLL_CONFIG);
 
        /* Clear CK_OUT_EN */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
-                     0, SDCC_HC_REG_DLL_CONFIG);
+       rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
+                     SDCC_HC_REG_DLL_CONFIG);
 
        /* Set DLL_EN */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
-                     SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
+       rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
 
        if (!ethqos->has_emac_ge_3) {
-               rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
-                             0, SDCC_HC_REG_DLL_CONFIG);
+               rgmii_clrmask(ethqos, SDCC_DLL_MCLK_GATING_EN,
+                             SDCC_HC_REG_DLL_CONFIG);
 
-               rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
-                             0, SDCC_HC_REG_DLL_CONFIG);
+               rgmii_clrmask(ethqos, SDCC_DLL_CDR_FINE_PHASE,
+                             SDCC_HC_REG_DLL_CONFIG);
        }
 
        /* Wait for CK_OUT_EN clear */
@@ -340,8 +349,8 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
                dev_err(dev, "Clear CK_OUT_EN timedout\n");
 
        /* Set CK_OUT_EN */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
-                     SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);
+       rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
+                     SDCC_HC_REG_DLL_CONFIG);
 
        /* Wait for CK_OUT_EN set */
        retry = 1000;
@@ -357,12 +366,12 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
                dev_err(dev, "Set CK_OUT_EN timedout\n");
 
        /* Set DDR_CAL_EN */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
-                     SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
+       rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
+                     SDCC_HC_REG_DLL_CONFIG2);
 
        if (!ethqos->has_emac_ge_3) {
-               rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
-                             0, SDCC_HC_REG_DLL_CONFIG2);
+               rgmii_clrmask(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
+                             SDCC_HC_REG_DLL_CONFIG2);
 
                rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
                              0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
@@ -370,8 +379,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
                rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
                              BIT(2), SDCC_HC_REG_DLL_CONFIG2);
 
-               rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
-                             SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
+               rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
                              SDCC_HC_REG_DLL_CONFIG2);
        }
 
@@ -392,8 +400,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
                phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;
 
        /* Disable loopback mode */
-       rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
-                     0, RGMII_IO_MACRO_CONFIG2);
+       rgmii_clrmask(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
+                     RGMII_IO_MACRO_CONFIG2);
 
        /* Determine if this platform wants loopback enabled after programming */
        if (ethqos->rgmii_config_loopback_en)
@@ -402,29 +410,26 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
                loopback = 0;
 
        /* Select RGMII, write 0 to interface select */
-       rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
-                     0, RGMII_IO_MACRO_CONFIG);
+       rgmii_clrmask(ethqos, RGMII_CONFIG_INTF_SEL, RGMII_IO_MACRO_CONFIG);
 
        switch (speed) {
        case SPEED_1000:
-               rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
-                             RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
-                             0, RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
-                             RGMII_CONFIG_POS_NEG_DATA_SEL,
+               rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
                              RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
-                             RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
-                             0, RGMII_IO_MACRO_CONFIG2);
+               rgmii_clrmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
+                             RGMII_IO_MACRO_CONFIG);
+               rgmii_setmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
+                             RGMII_IO_MACRO_CONFIG);
+               rgmii_setmask(ethqos, RGMII_CONFIG_PROG_SWAP,
+                             RGMII_IO_MACRO_CONFIG);
+               rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
+                             RGMII_IO_MACRO_CONFIG2);
 
                rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
                              phase_shift, RGMII_IO_MACRO_CONFIG2);
-               rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
-                             0, RGMII_IO_MACRO_CONFIG2);
-               rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
-                             RGMII_CONFIG2_RX_PROG_SWAP,
+               rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
+                             RGMII_IO_MACRO_CONFIG2);
+               rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
                              RGMII_IO_MACRO_CONFIG2);
 
                /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
@@ -439,87 +444,78 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
                        rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
                                      57, SDCC_HC_REG_DDR_CONFIG);
                }
-               rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
-                             SDCC_DDR_CONFIG_PRG_DLY_EN,
+               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
                              SDCC_HC_REG_DDR_CONFIG);
                rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
                              loopback, RGMII_IO_MACRO_CONFIG);
                break;
 
        case SPEED_100:
-               rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
-                             RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
-                             RGMII_CONFIG_BYPASS_TX_ID_EN,
+               rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
+                             RGMII_IO_MACRO_CONFIG);
+               rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
+                             RGMII_IO_MACRO_CONFIG);
+               rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
                              RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
-                             0, RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
-                             0, RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
-                             0, RGMII_IO_MACRO_CONFIG2);
+               rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP,
+                             RGMII_IO_MACRO_CONFIG);
+               rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
+                             RGMII_IO_MACRO_CONFIG2);
                rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
                              phase_shift, RGMII_IO_MACRO_CONFIG2);
                rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
                              BIT(6), RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
-                             0, RGMII_IO_MACRO_CONFIG2);
+               rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
+                             RGMII_IO_MACRO_CONFIG2);
 
                if (ethqos->has_emac_ge_3)
-                       rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
-                                     RGMII_CONFIG2_RX_PROG_SWAP,
+                       rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
                                      RGMII_IO_MACRO_CONFIG2);
                else
-                       rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
-                                     0, RGMII_IO_MACRO_CONFIG2);
+                       rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
+                                     RGMII_IO_MACRO_CONFIG2);
 
                /* Write 0x5 to PRG_RCLK_DLY_CODE */
                rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
                              (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
-               rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
-                             SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
+               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
                              SDCC_HC_REG_DDR_CONFIG);
-               rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
-                             SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
+               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
                              SDCC_HC_REG_DDR_CONFIG);
                rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
                              loopback, RGMII_IO_MACRO_CONFIG);
                break;
 
        case SPEED_10:
-               rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
-                             RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
-                             RGMII_CONFIG_BYPASS_TX_ID_EN,
+               rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
+                             RGMII_IO_MACRO_CONFIG);
+               rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
+                             RGMII_IO_MACRO_CONFIG);
+               rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
                              RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
-                             0, RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
-                             0, RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
-                             0, RGMII_IO_MACRO_CONFIG2);
+               rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP,
+                             RGMII_IO_MACRO_CONFIG);
+               rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
+                             RGMII_IO_MACRO_CONFIG2);
                rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
                              phase_shift, RGMII_IO_MACRO_CONFIG2);
                rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
                              BIT(12) | GENMASK(9, 8),
                              RGMII_IO_MACRO_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
-                             0, RGMII_IO_MACRO_CONFIG2);
+               rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
+                             RGMII_IO_MACRO_CONFIG2);
                if (ethqos->has_emac_ge_3)
-                       rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
-                                     RGMII_CONFIG2_RX_PROG_SWAP,
+                       rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
                                      RGMII_IO_MACRO_CONFIG2);
                else
-                       rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
-                                     0, RGMII_IO_MACRO_CONFIG2);
+                       rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
+                                     RGMII_IO_MACRO_CONFIG2);
                /* Write 0x5 to PRG_RCLK_DLY_CODE */
                rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
                              (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
-               rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
-                             SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
+               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
                              SDCC_HC_REG_DDR_CONFIG);
-               rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
-                             SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
+               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
                              SDCC_HC_REG_DDR_CONFIG);
                rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
                              loopback, RGMII_IO_MACRO_CONFIG);
@@ -547,12 +543,12 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed)
        /* Initialize the DLL first */
 
        /* Set DLL_RST */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
-                     SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
+       rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_RST,
+                     SDCC_HC_REG_DLL_CONFIG);
 
        /* Set PDN */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
-                     SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
+       rgmii_setmask(ethqos, SDCC_DLL_CONFIG_PDN,
+                     SDCC_HC_REG_DLL_CONFIG);
 
        if (ethqos->has_emac_ge_3) {
                if (speed == SPEED_1000) {
@@ -566,21 +562,18 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed)
        }
 
        /* Clear DLL_RST */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
-                     SDCC_HC_REG_DLL_CONFIG);
+       rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
 
        /* Clear PDN */
-       rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
-                     SDCC_HC_REG_DLL_CONFIG);
+       rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
 
        if (speed != SPEED_100 && speed != SPEED_10) {
                /* Set DLL_EN */
-               rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
-                             SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
+               rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_EN,
+                             SDCC_HC_REG_DLL_CONFIG);
 
                /* Set CK_OUT_EN */
-               rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
-                             SDCC_DLL_CONFIG_CK_OUT_EN,
+               rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
                              SDCC_HC_REG_DLL_CONFIG);
 
                /* Set USR_CTL bit 26 with mask of 3 bits */
@@ -631,15 +624,13 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos, int speed)
 
        switch (speed) {
        case SPEED_2500:
-               rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
-                             RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
+               rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
                              RGMII_IO_MACRO_CONFIG2);
                ethqos_set_serdes_speed(ethqos, SPEED_2500);
                ethqos_pcs_set_inband(priv, false);
                break;
        case SPEED_1000:
-               rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
-                             RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
+               rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
                              RGMII_IO_MACRO_CONFIG2);
                ethqos_set_serdes_speed(ethqos, SPEED_1000);
                ethqos_pcs_set_inband(priv, true);