4.18-stable patches

added patches:
	revert-drm-amd-pp-send-khz-clock-values-to-dc-for-smu7-8.patch

diff --git a/queue-4.18/revert-drm-amd-pp-send-khz-clock-values-to-dc-for-smu7-8.patch b/queue-4.18/revert-drm-amd-pp-send-khz-clock-values-to-dc-for-smu7-8.patch
new file mode 100644 (file)
index 0000000..0f96ccc
--- /dev/null
+++ b/queue-4.18/revert-drm-amd-pp-send-khz-clock-values-to-dc-for-smu7-8.patch
@@ -0,0 +1,79 @@
+From cc2e9e80548eb54cbb9bf06392fb35b91e918831 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Tue, 9 Oct 2018 17:08:58 +0200
+Subject: Revert "drm/amd/pp: Send khz clock values to DC for smu7/8"
+
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+This reverts commit 93b100ddda3be284be160e9ccba28c7f8f21ab73 which was
+commit c3cb424a086921f6bb0449b10d998352a756d6d5 upstream.
+
+It was not needed for 4.18.y and caused problems there.
+
+Reported-by: Alexander Deucher <Alexander.Deucher@amd.com>
+Cc: Harry Wentland <harry.wentland@amd.com>
+Cc: Sasha Levin <alexander.levin@microsoft.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c |    8 ++++----
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c |    6 +++---
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -4555,12 +4555,12 @@ static int smu7_get_sclks(struct pp_hwmg
+                       return -EINVAL;
+               dep_sclk_table = table_info->vdd_dep_on_sclk;
+               for (i = 0; i < dep_sclk_table->count; i++)
+-                      clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
++                      clocks->clock[i] = dep_sclk_table->entries[i].clk;
+               clocks->count = dep_sclk_table->count;
+       } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
+               sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
+               for (i = 0; i < sclk_table->count; i++)
+-                      clocks->clock[i] = sclk_table->entries[i].clk * 10;
++                      clocks->clock[i] = sclk_table->entries[i].clk;
+               clocks->count = sclk_table->count;
+       }
+ 
+@@ -4592,7 +4592,7 @@ static int smu7_get_mclks(struct pp_hwmg
+                       return -EINVAL;
+               dep_mclk_table = table_info->vdd_dep_on_mclk;
+               for (i = 0; i < dep_mclk_table->count; i++) {
+-                      clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
++                      clocks->clock[i] = dep_mclk_table->entries[i].clk;
+                       clocks->latency[i] = smu7_get_mem_latency(hwmgr,
+                                               dep_mclk_table->entries[i].clk);
+               }
+@@ -4600,7 +4600,7 @@ static int smu7_get_mclks(struct pp_hwmg
+       } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
+               mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
+               for (i = 0; i < mclk_table->count; i++)
+-                      clocks->clock[i] = mclk_table->entries[i].clk * 10;
++                      clocks->clock[i] = mclk_table->entries[i].clk;
+               clocks->count = mclk_table->count;
+       }
+       return 0;
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+@@ -1605,17 +1605,17 @@ static int smu8_get_clock_by_type(struct
+       switch (type) {
+       case amd_pp_disp_clock:
+               for (i = 0; i < clocks->count; i++)
+-                      clocks->clock[i] = data->sys_info.display_clock[i] * 10;
++                      clocks->clock[i] = data->sys_info.display_clock[i];
+               break;
+       case amd_pp_sys_clock:
+               table = hwmgr->dyn_state.vddc_dependency_on_sclk;
+               for (i = 0; i < clocks->count; i++)
+-                      clocks->clock[i] = table->entries[i].clk * 10;
++                      clocks->clock[i] = table->entries[i].clk;
+               break;
+       case amd_pp_mem_clock:
+               clocks->count = SMU8_NUM_NBPMEMORYCLOCK;
+               for (i = 0; i < clocks->count; i++)
+-                      clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10;
++                      clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
+               break;
+       default:
+               return -1;

diff --git a/queue-4.18/series b/queue-4.18/series
index 01e7cf121f3ddbfe4bd4149c76b6d124ecc7579e..a167f2751feab2fdff8bbed273ce1dab05cef841 100644 (file)
--- a/queue-4.18/series
+++ b/queue-4.18/series
@@ -166,3 +166,4 @@ ocfs2-fix-locking-for-res-tracking-and-dlm-tracking_list.patch
 hid-i2c-hid-disable-runtime-pm-operations-on-hantick-touchpad.patch
 ixgbe-check-return-value-of-napi_complete_done.patch
 dm-thin-metadata-fix-__udivdi3-undefined-on-32-bit.patch
+revert-drm-amd-pp-send-khz-clock-values-to-dc-for-smu7-8.patch