RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs

Some test cases explicitly set -march or -mcpu with extensions which
are not compatible with the E ABI variants.  This leads to spurious
errors when toolchain has been configured for RV32E base ISA and
ILP32E ABI:
  cc1: error: ILP32E ABI does not support the 'D' extension

Also, test gcc.target/riscv/rvv/base/pr119164.c implicitly requires
rv64 since it explicitly selects -march=rv64gcv_zvl256b:
  cc1: error: ABI requires '-march=rv32'

Testing done:
 - Ensured cross riscv64-unknown-linux-gnu has no difference in test
   output with and without the patch.
 - For riscv32-unknown-elf  there are no new failures. Test case pr119164.c
   no longer fails and is now marked as unsupported.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-xt-c908.c: Disable for E ABI variants.
	* gcc.target/riscv/mcpu-xt-c908v.c: Ditto.
	* gcc.target/riscv/mcpu-xt-c910.c: Ditto.
	* gcc.target/riscv/mcpu-xt-c910v2.c: Ditto.
	* gcc.target/riscv/mcpu-xt-c920.c: Ditto.
	* gcc.target/riscv/mcpu-xt-c920v2.c: Ditto.
	* gcc.target/riscv/pr118241.c: Ditto.
	* gcc.target/riscv/pr120223.c: Ditto.
	* gcc.target/riscv/rvv/base/pr119164.c: Disable for E ABI variants
	and for 32-bit ISA.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
index cb28baf1ce7216ce897850e6baa35893f08ca836..4ad82a81dec850daf0b05ab9132575a8c4390ea2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */
 /* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
index 1b1ee188229f00fb77d9e87c6e680899d8e21ace..bb9e3109920a470d98e5fea7ca7be91997a08af5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */
 /* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
index 1e276659c3ea206bc9590cba9b742abb323b87d3..397e7b192670ceabea30e8655b17a769ef31aca9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */
 /* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
index 6a54f0988780bbc78bebf7e1cb4a2e4ea7124280..9e39c9f89eb4d262343f5cb9ea383c977105c246 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */
 /* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
index 6bcd687e74248bb971f129842cd9a77036fa891f..4cce90a1e9458c97c00b026d77d4331801b5ac02 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */
 /* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
index 36a6267849bfbb4a69ccf6dad2bf7295b9ff5c95..1f21d07f37ad37995b175f7559d8697c135372d1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */
 /* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */

diff --git a/gcc/testsuite/gcc.target/riscv/pr118241.c b/gcc/testsuite/gcc.target/riscv/pr118241.c
index f1dc44bce0ca4ecb55ce2d5b43f8c2837b01ef3a..768ea050f1aa2f4daa932eec79b029793fdf8300 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/pr118241.c
+++ b/gcc/testsuite/gcc.target/riscv/pr118241.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-options "-march=rv64gc_zicbop" { target { rv64 } } } */
 /* { dg-options "-march=rv32gc_zicbop" { target { rv32 } } } */
 /* { dg-skip-if "" { *-*-* } { "-O0" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/pr120223.c b/gcc/testsuite/gcc.target/riscv/pr120223.c
index fae21b6d1ece0757a1c92acb2e4cfaeb8ffad1f0..d6afd866c58531a9df43c8cff0bf97df1bd78ee5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/pr120223.c
+++ b/gcc/testsuite/gcc.target/riscv/pr120223.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-options "-mcpu=thead-c906" }  */
 long foo(long x) { return x ^ 0x80000000; }
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
index a39a7f177f054196e2ea93d9cd418c89422e490e..266e9485880c042c45a9816cd48ae50ccf4083fb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
@@ -1,7 +1,7 @@
 /* Reduced from SPEC2017 blender: node_texture_util.c.
    The conditional function call was tripping mode switching state machine */
 
-/* { dg-do compile } */
+/* { dg-do compile  { target { rv64 && { ! riscv_abi_e } } } } */
 /* { dg-options " -Ofast -march=rv64gcv_zvl256b -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 void *a;