net: stmmac: imx: convert to PHY_INTF_SEL_xxx

Convert dwmac-imx to use the PHY_INTF_SEL_xxx definitions rather than
constants via:
- ensuring that the prefix for the MASK and value definitions is the
  same.
- using FIELD_PREP() to shift the PHY_INTF_SEL_xxx definition to the
  appropriate bitfield.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vFt4n-0000000Choy-0IeG@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
index 147fa08d5b6e75d96c19f939a249829f737ad763..4fbee59e7337ca3c646b65a4c5ed80796ec8887a 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
@@ -23,18 +23,25 @@
 #include "stmmac_platform.h"
 
 #define GPR_ENET_QOS_INTF_MODE_MASK    GENMASK(21, 16)
-#define GPR_ENET_QOS_INTF_SEL_MII      (0x0 << 16)
-#define GPR_ENET_QOS_INTF_SEL_RMII     (0x4 << 16)
-#define GPR_ENET_QOS_INTF_SEL_RGMII    (0x1 << 16)
+#define GPR_ENET_QOS_INTF_SEL_MASK     GENMASK(20, 16)
+#define GPR_ENET_QOS_INTF_SEL_MII      FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \
+                                                  PHY_INTF_SEL_GMII_MII)
+#define GPR_ENET_QOS_INTF_SEL_RMII     FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \
+                                                  PHY_INTF_SEL_RMII)
+#define GPR_ENET_QOS_INTF_SEL_RGMII    FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \
+                                                  PHY_INTF_SEL_RGMII)
 #define GPR_ENET_QOS_CLK_GEN_EN                (0x1 << 19)
 #define GPR_ENET_QOS_CLK_TX_CLK_SEL    (0x1 << 20)
 #define GPR_ENET_QOS_RGMII_EN          (0x1 << 21)
 
 #define MX93_GPR_ENET_QOS_INTF_MODE_MASK       GENMASK(3, 0)
-#define MX93_GPR_ENET_QOS_INTF_MASK            GENMASK(3, 1)
-#define MX93_GPR_ENET_QOS_INTF_SEL_MII         (0x0 << 1)
-#define MX93_GPR_ENET_QOS_INTF_SEL_RMII                (0x4 << 1)
-#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII       (0x1 << 1)
+#define MX93_GPR_ENET_QOS_INTF_SEL_MASK                GENMASK(3, 1)
+#define MX93_GPR_ENET_QOS_INTF_SEL_MII         FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \
+                                                          PHY_INTF_SEL_GMII_MII)
+#define MX93_GPR_ENET_QOS_INTF_SEL_RMII                FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \
+                                                          PHY_INTF_SEL_RMII)
+#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII       FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \
+                                                          PHY_INTF_SEL_RGMII)
 #define MX93_GPR_ENET_QOS_CLK_GEN_EN           (0x1 << 0)
 #define MX93_GPR_ENET_QOS_CLK_SEL_MASK         BIT_MASK(0)
 #define MX93_GPR_CLK_SEL_OFFSET                        (4)
@@ -241,7 +248,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
        if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
                return;
 
-       iface &= MX93_GPR_ENET_QOS_INTF_MASK;
+       iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK;
        if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
                return;