--- /dev/null
+From 1aa772be0444a2bd06957f6d31865e80e6ae4244 Mon Sep 17 00:00:00 2001
+From: Francesco Dolcini <francesco.dolcini@toradex.com>
+Date: Fri, 4 Oct 2024 17:24:17 +0200
+Subject: dt-bindings: net: fec: add pps channel property
+
+From: Francesco Dolcini <francesco.dolcini@toradex.com>
+
+commit 1aa772be0444a2bd06957f6d31865e80e6ae4244 upstream.
+
+Add fsl,pps-channel property to select where to connect the PPS signal.
+This depends on the internal SoC routing and on the board, for example
+on the i.MX8 SoC it can be connected to an external pin (using channel 1)
+or to internal eDMA as DMA request (channel 0).
+
+Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ Documentation/devicetree/bindings/net/fsl,fec.yaml | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/fsl,fec.yaml
++++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml
+@@ -182,6 +182,13 @@ properties:
+ description:
+ Register bits of stop mode control, the format is <&gpr req_gpr req_bit>.
+
++ fsl,pps-channel:
++ $ref: /schemas/types.yaml#/definitions/uint32
++ default: 0
++ description:
++ Specifies to which timer instance the PPS signal is routed.
++ enum: [0, 1, 2, 3]
++
+ mdio:
+ $ref: mdio.yaml#
+ unevaluatedProperties: false