writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
}
+static int amd_sdw_set_device_state(struct amd_sdw_manager *amd_manager, u32 target_device_state)
+{
+ u32 sdw_dev_state;
+
+ sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE);
+ switch (amd_manager->instance) {
+ case ACP_SDW0:
+ u32p_replace_bits(&sdw_dev_state, target_device_state,
+ AMD_SDW0_DEVICE_STATE_MASK);
+ break;
+ case ACP_SDW1:
+ u32p_replace_bits(&sdw_dev_state, target_device_state,
+ AMD_SDW1_DEVICE_STATE_MASK);
+ break;
+ default:
+ return -EINVAL;
+ }
+ writel(sdw_dev_state, amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE);
+ sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE);
+ dev_dbg(amd_manager->dev, "AMD_SDW_DEVICE_STATE:0x%x\n", sdw_dev_state);
+ return 0;
+}
+
static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg,
int cmd_offset)
{
if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
amd_sdw_wake_enable(amd_manager, false);
- return amd_sdw_clock_stop(amd_manager);
+ ret = amd_sdw_clock_stop(amd_manager);
+ if (ret)
+ return ret;
} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
amd_sdw_wake_enable(amd_manager, false);
/*
ret = amd_sdw_clock_stop(amd_manager);
if (ret)
return ret;
- return amd_deinit_sdw_manager(amd_manager);
+ ret = amd_deinit_sdw_manager(amd_manager);
+ if (ret)
+ return ret;
+ }
+ if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) {
+ ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3);
+ if (ret)
+ return ret;
}
return 0;
}
}
if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
amd_sdw_wake_enable(amd_manager, true);
- return amd_sdw_clock_stop(amd_manager);
+ ret = amd_sdw_clock_stop(amd_manager);
+ if (ret)
+ return ret;
} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
amd_sdw_wake_enable(amd_manager, true);
ret = amd_sdw_clock_stop(amd_manager);
if (ret)
return ret;
- return amd_deinit_sdw_manager(amd_manager);
+ ret = amd_deinit_sdw_manager(amd_manager);
+ if (ret)
+ return ret;
+ }
+ if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) {
+ ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3);
+ if (ret)
+ return ret;
}
return 0;
}
}
if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
- return amd_sdw_clock_stop_exit(amd_manager);
+ ret = amd_sdw_clock_stop_exit(amd_manager);
+ if (ret)
+ return ret;
} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
return ret;
amd_sdw_set_frameshape(amd_manager);
}
+ if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) {
+ ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D0);
+ if (ret)
+ return ret;
+ }
return 0;
}
#define AMD_SDW_CLK_RESUME_DONE 3
#define AMD_SDW_WAKE_STAT_MASK BIT(16)
#define AMD_SDW_WAKE_INTR_MASK BIT(16)
+#define AMD_SDW_DEVICE_STATE 0x1430
+#define AMD_SDW0_DEVICE_STATE_MASK GENMASK(1, 0)
+#define AMD_SDW1_DEVICE_STATE_MASK GENMASK(3, 2)
+#define AMD_SDW_DEVICE_STATE_D0 0
+#define AMD_SDW_DEVICE_STATE_D3 3
static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {
AMD_SDW_DEFAULT_CLK_FREQ,