re PR target/24772 (Lots of ICEs in vrsave_operation_1 while running the testsuite...

        PR target/24772
        * config/rs6000/predicates.md (vrsave_operation): SET_SRC is a VEC.

        * config/rs6000/rs6000.md (btruncsf2, ceilsf2, floorsf2,
        roundsf2): Remove "s" from mnemonic.

From-SVN: r107085

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index dc84b221de79972deb7610234292ee9e45334bdf..c7f4f79140e331c8ad9f3813baeb54774032ff50 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2005-11-16  David Edelsohn  <edelsohn@gnu.org>
+
+       PR target/24772
+       * config/rs6000/predicates.md (vrsave_operation): SET_SRC is a VEC.
+
+       * config/rs6000/rs6000.md (btruncsf2, ceilsf2, floorsf2,
+       roundsf2): Remove "s" from mnemonic.
+
 2005-11-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 
        * config/bfin/crti.s (__init, __fini): Use appropriate prologue if

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4ce00b0674d506fe2b91656d9415cfc3dc64e4f7..0ede69dcd1f4c3409566edf56aa8c640c25d2e8c 100644 (file)
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1038,10 +1038,9 @@
     return 0;
 
   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
-  src_regno  = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
+  src_regno  = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
 
-  if (dest_regno != VRSAVE_REGNO
-      && src_regno != VRSAVE_REGNO)
+  if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
     return 0;
 
   for (i = 1; i < count; i++)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ee9cc427524adda56717248fad4adf5d75d10ffb..935775aef3f4b585414b9b0f8fcc53033538308f 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5332,7 +5332,7 @@
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
   "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
-  "frizs %0,%1"
+  "friz %0,%1"
   [(set_attr "type" "fp")])
 
 (define_insn "ceildf2"
@@ -5343,10 +5343,10 @@
   [(set_attr "type" "fp")])
 
 (define_insn "ceilsf2"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
   "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
-  "frips %0,%1"
+  "frip %0,%1"
   [(set_attr "type" "fp")])
 
 (define_insn "floordf2"
@@ -5360,7 +5360,7 @@
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
   "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
-  "frims %0,%1"
+  "frim %0,%1"
   [(set_attr "type" "fp")])
 
 (define_insn "rounddf2"
@@ -5374,7 +5374,7 @@
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
   "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
-  "frins %0,%1"
+  "frin %0,%1"
   [(set_attr "type" "fp")])
 
 ; An UNSPEC is used so we don't have to support SImode in FP registers.