platform/x86/amd/pmf: Update sps power thermals according to the platform-profiles

Update power thermals according to the platform-profiles selected by the
user.

Co-developed-by: Patil Rajesh Reddy <Patil.Reddy@amd.com>
Signed-off-by: Patil Rajesh Reddy <Patil.Reddy@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20240306114415.3267603-8-Shyam-sundar.S-k@amd.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h
index 10d5f8cef27e71601178af6627598b688f813a97..907e046c3c967a3b49f54e51abd47236684f1653 100644 (file)
--- a/drivers/platform/x86/amd/pmf/pmf.h
+++ b/drivers/platform/x86/amd/pmf/pmf.h
@@ -55,6 +55,8 @@ struct cookie_header {
 #define GET_STT_LIMIT_APU      0x20
 #define GET_STT_LIMIT_HS2      0x21
 #define SET_P3T                                0x23 /* P3T: Peak Package Power Limit */
+#define SET_PMF_PPT            0x25
+#define SET_PMF_PPT_APU_ONLY   0x26
 
 /* OS slider update notification */
 #define DC_BEST_PERF           0

diff --git a/drivers/platform/x86/amd/pmf/sps.c b/drivers/platform/x86/amd/pmf/sps.c
index 96bd2140302ca77a85b45356083391d785daa386..92f7fb22277dca773a6b88f404bd94ea1e697a9c 100644 (file)
--- a/drivers/platform/x86/amd/pmf/sps.c
+++ b/drivers/platform/x86/amd/pmf/sps.c
@@ -190,6 +190,19 @@ static void amd_pmf_load_defaults_sps(struct amd_pmf_dev *dev)
        amd_pmf_dump_sps_defaults(&config_store);
 }
 
+static void amd_pmf_update_slider_v2(struct amd_pmf_dev *dev, int idx)
+{
+       amd_pmf_send_cmd(dev, SET_PMF_PPT, false, apts_config_store.val[idx].pmf_ppt, NULL);
+       amd_pmf_send_cmd(dev, SET_PMF_PPT_APU_ONLY, false,
+                        apts_config_store.val[idx].ppt_pmf_apu_only, NULL);
+       amd_pmf_send_cmd(dev, SET_STT_MIN_LIMIT, false,
+                        apts_config_store.val[idx].stt_min_limit, NULL);
+       amd_pmf_send_cmd(dev, SET_STT_LIMIT_APU, false,
+                        apts_config_store.val[idx].stt_skin_temp_limit_apu, NULL);
+       amd_pmf_send_cmd(dev, SET_STT_LIMIT_HS2, false,
+                        apts_config_store.val[idx].stt_skin_temp_limit_hs2, NULL);
+}
+
 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
                           struct amd_pmf_static_slider_granular *table)
 {
@@ -222,6 +235,32 @@ void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
        }
 }
 
+static int amd_pmf_update_sps_power_limits_v2(struct amd_pmf_dev *pdev, int pwr_mode)
+{
+       int src, index;
+
+       src = amd_pmf_get_power_source();
+
+       switch (pwr_mode) {
+       case POWER_MODE_PERFORMANCE:
+               index = config_store_v2.sps_idx.power_states[src][POWER_MODE_BEST_PERFORMANCE];
+               amd_pmf_update_slider_v2(pdev, index);
+               break;
+       case POWER_MODE_BALANCED_POWER:
+               index = config_store_v2.sps_idx.power_states[src][POWER_MODE_BALANCED];
+               amd_pmf_update_slider_v2(pdev, index);
+               break;
+       case POWER_MODE_POWER_SAVER:
+               index = config_store_v2.sps_idx.power_states[src][POWER_MODE_BEST_POWER_EFFICIENCY];
+               amd_pmf_update_slider_v2(pdev, index);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf)
 {
        int mode;
@@ -230,6 +269,9 @@ int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf)
        if (mode < 0)
                return mode;
 
+       if (pmf->pmf_if_version == PMF_IF_V2)
+               return amd_pmf_update_sps_power_limits_v2(pmf, mode);
+
        amd_pmf_update_slider(pmf, SLIDER_OP_SET, mode, NULL);
 
        return 0;