arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode

The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode
with MAC Ports 1 and 2 of the instance, which are connected to ENET
Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through
the Serdes2 instance of the SERDES.

Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode
at 5 Gbps each.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Link: https://lore.kernel.org/r/20240502091002.3659435-6-c-vankar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index bb3ca0d17788f21f3d3134c09aafb27fe6831d2a..c4f72004581a852f29b4d1bcbc9844782f175dd6 100644 (file)
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
 
 # Build time test only, enabled by CONFIG_OF_ALL_DTBS
 k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
@@ -151,6 +152,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
        k3-j721s2-evm-pcie1-ep.dtbo
 k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
        k3-j784s4-evm-quad-port-eth-exp1.dtbo
+k3-j784s4-evm-usxgmii-exp1-exp2-dtbs := k3-j784s4-evm.dtb \
+       k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
 dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
        k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
        k3-am625-sk-csi2-imx219.dtb \
@@ -172,7 +175,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
        k3-j721e-evm-pcie0-ep.dtb \
        k3-j721e-sk-csi2-dual-imx219.dtb \
        k3-j721s2-evm-pcie1-ep.dtb \
-       k3-j784s4-evm-quad-port-eth-exp1.dtb
+       k3-j784s4-evm-quad-port-eth-exp1.dtb \
+       k3-j784s4-evm-usxgmii-exp1-exp2.dtb
 
 # Enable support for device-tree overlays
 DTC_FLAGS_k3-am625-beagleplay += -@

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
new file mode 100644 (file)
index 0000000..d5f8c85
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/**
+ * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
+ * and ENET-2 Expansion slots of J784S4 EVM.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-serdes.h"
+
+&{/} {
+       aliases {
+               ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+               ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+               ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+       };
+};
+
+&main_cpsw0 {
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&main_cpsw0_port1 {
+       phy-mode = "usxgmii";
+       mac-address = [00 00 00 00 00 00];
+       phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
+       phy-names = "mac", "serdes";
+       status = "okay";
+       fixed-link {
+               speed = <5000>;
+               full-duplex;
+       };
+};
+
+&main_cpsw0_port2 {
+       phy-mode = "usxgmii";
+       mac-address = [00 00 00 00 00 00];
+       phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
+       phy-names = "mac", "serdes";
+       status = "okay";
+       fixed-link {
+               speed = <5000>;
+               full-duplex;
+       };
+};
+
+&serdes_wiz2 {
+       assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
+       status = "okay";
+};
+
+&serdes2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       serdes2_usxgmii_link: phy@2 {
+               reg = <2>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_USXGMII>;
+               resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
+       };
+};
+
+&serdes_ln_ctrl {
+       idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+                     <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+                     <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+                     <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+                     <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+                     <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
+};