]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
iio: adc: rockchip: Fix clock initialization sequence
authorSimon Xue <xxm@rock-chips.com>
Wed, 12 Mar 2025 06:20:16 +0000 (14:20 +0800)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Mon, 7 Apr 2025 18:32:49 +0000 (19:32 +0100)
clock_set_rate should be executed after devm_clk_get_enabled.

Fixes: 97ad10bb2901 ("iio: adc: rockchip_saradc: Make use of devm_clk_get_enabled")
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20250312062016.137821-1-xxm@rock-chips.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
drivers/iio/adc/rockchip_saradc.c

index 9a099df7951891a7d917e382a5dcad17b544ecee..5e28bd28b81a9a9dc4b0d4f7ea56dc02ea0e19fe 100644 (file)
@@ -520,15 +520,6 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
        if (info->reset)
                rockchip_saradc_reset_controller(info->reset);
 
-       /*
-        * Use a default value for the converter clock.
-        * This may become user-configurable in the future.
-        */
-       ret = clk_set_rate(info->clk, info->data->clk_rate);
-       if (ret < 0)
-               return dev_err_probe(&pdev->dev, ret,
-                                    "failed to set adc clk rate\n");
-
        ret = regulator_enable(info->vref);
        if (ret < 0)
                return dev_err_probe(&pdev->dev, ret,
@@ -555,6 +546,14 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
        if (IS_ERR(info->clk))
                return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
                                     "failed to get adc clock\n");
+       /*
+        * Use a default value for the converter clock.
+        * This may become user-configurable in the future.
+        */
+       ret = clk_set_rate(info->clk, info->data->clk_rate);
+       if (ret < 0)
+               return dev_err_probe(&pdev->dev, ret,
+                                    "failed to set adc clk rate\n");
 
        platform_set_drvdata(pdev, indio_dev);