drm/i915/gt: Add Wa_14019789679

Wa_14019789679 implementation for MTL, ARL and DG2.

v2: Corrected condition

v3:
   - Fix indentation (Jani Nikula)
   - dword size should be 0x1 and
     initialize dword to 0 instead of MI_NOOP (Tejas)
   - Use IS_GFX_GT_IP_RANGE() (Tejas)

v4:
   - 3DSTATE_MESH_CONTROL instruction is 3 dwords long
     Align with dword size. (Roper, Matthew D)
   - Add RCS engine check. (Tejas)

Bspec: 47083

Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240731155614.3460645-1-nitin.r.gote@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2bd8d98d211023cb927aa12caa308243ee5fe3cb..5394bc7d4daf81977265d80fe6f6db62810472fa 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -220,6 +220,7 @@
 #define GFX_OP_DESTBUFFER_INFO  ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
+#define CMD_3DSTATE_MESH_CONTROL ((0x3 << 29) | (0x3 << 27) | (0x0 << 24) | (0x77 << 16) | (0x3))
 
 #define XY_CTRL_SURF_INSTR_SIZE                5
 #define MI_FLUSH_DW_SIZE               3

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 09a287c1aedd67e66eb0fbb3079ee5166143f32f..bfe6d8fc820fec95c1562ec0f143cd1a03529ad0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -974,7 +974,12 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
        if (ret)
                return ret;
 
-       cs = intel_ring_begin(rq, (wal->count * 2 + 2));
+       if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||
+            IS_DG2(rq->i915)) && rq->engine->class == RENDER_CLASS)
+               cs = intel_ring_begin(rq, (wal->count * 2 + 6));
+       else
+               cs = intel_ring_begin(rq, (wal->count * 2 + 2));
+
        if (IS_ERR(cs))
                return PTR_ERR(cs);
 
@@ -1004,6 +1009,15 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
        }
        *cs++ = MI_NOOP;
 
+       /* Wa_14019789679 */
+       if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||
+            IS_DG2(rq->i915)) && rq->engine->class == RENDER_CLASS) {
+               *cs++ = CMD_3DSTATE_MESH_CONTROL;
+               *cs++ = 0;
+               *cs++ = 0;
+               *cs++ = MI_NOOP;
+       }
+
        intel_uncore_forcewake_put__locked(uncore, fw);
        spin_unlock(&uncore->lock);
        intel_gt_mcr_unlock(wal->gt, flags);