perf arm-spe: Add support for SPE Data Source packet on HiSilicon HIP12

Add data source encoding for HiSilicon HIP12 and coresponding mapping
to the perf's memory data source. This will help to synthesize the data
and support upper layer tools like perf-mem and perf-c2c.

Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Cc: CaiJingtao <caijingtao@huawei.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Junhao He <hejunhao3@huawei.com>
Cc: Leo Yan <leo.yan@linux.dev>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: Yushan Wang <wangyushan12@huawei.com>
Cc: Zeng Tao <prime.zeng@hisilicon.com>
Cc: xueshan2@huawei.com
Link: https://lore.kernel.org/r/20250425033845.57671-3-yangyicong@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h
index 488f8e75134959f5263a61230dbde5192e8d4a58..9a5d85cfd1fba6eef9cbb04b00af8b74e58e9428 100644 (file)
--- a/tools/arch/arm64/include/asm/cputype.h
+++ b/tools/arch/arm64/include/asm/cputype.h
@@ -129,6 +129,7 @@
 #define FUJITSU_CPU_PART_A64FX         0x001
 
 #define HISI_CPU_PART_TSV110           0xD01
+#define HISI_CPU_PART_HIP12            0xD06
 
 #define APPLE_CPU_PART_M1_ICESTORM     0x022
 #define APPLE_CPU_PART_M1_FIRESTORM    0x023
@@ -202,6 +203,7 @@
 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
+#define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12)
 #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
 #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
 #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)

diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
index 5d232188643b7440d02199cb5aaf0b920e1554a7..881d9f29c1380b62486f0cd81498750ba06c4b50 100644 (file)
--- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
@@ -82,6 +82,23 @@ enum arm_spe_ampereone_data_source {
        ARM_SPE_AMPEREONE_L2D                           = 0x9,
 };
 
+enum arm_spe_hisi_hip_data_source {
+       ARM_SPE_HISI_HIP_PEER_CPU               = 0,
+       ARM_SPE_HISI_HIP_PEER_CPU_HITM          = 1,
+       ARM_SPE_HISI_HIP_L3                     = 2,
+       ARM_SPE_HISI_HIP_L3_HITM                = 3,
+       ARM_SPE_HISI_HIP_PEER_CLUSTER           = 4,
+       ARM_SPE_HISI_HIP_PEER_CLUSTER_HITM      = 5,
+       ARM_SPE_HISI_HIP_REMOTE_SOCKET          = 6,
+       ARM_SPE_HISI_HIP_REMOTE_SOCKET_HITM     = 7,
+       ARM_SPE_HISI_HIP_LOCAL_MEM              = 8,
+       ARM_SPE_HISI_HIP_REMOTE_MEM             = 9,
+       ARM_SPE_HISI_HIP_NC_DEV                 = 13,
+       ARM_SPE_HISI_HIP_L2                     = 16,
+       ARM_SPE_HISI_HIP_L2_HITM                = 17,
+       ARM_SPE_HISI_HIP_L1                     = 18,
+};
+
 struct arm_spe_record {
        enum arm_spe_sample_type type;
        int err;

diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index 2a9775649cc2c170c173a3c0241e21c998582543..d46e0cccac99a36148b4daa37f2bf2342e6b47ef 100644 (file)
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -571,6 +571,11 @@ static const struct midr_range ampereone_ds_encoding_cpus[] = {
        {},
 };
 
+static const struct midr_range hisi_hip_ds_encoding_cpus[] = {
+       MIDR_ALL_VERSIONS(MIDR_HISI_HIP12),
+       {},
+};
+
 static void arm_spe__sample_flags(struct arm_spe_queue *speq)
 {
        const struct arm_spe_record *record = &speq->decoder->record;
@@ -718,9 +723,100 @@ static void arm_spe__synth_data_source_ampereone(const struct arm_spe_record *re
        arm_spe__synth_data_source_common(&common_record, data_src);
 }
 
+static void arm_spe__synth_data_source_hisi_hip(const struct arm_spe_record *record,
+                                               union perf_mem_data_src *data_src)
+{
+       /* Use common synthesis method to handle store operations */
+       if (record->op & ARM_SPE_OP_ST) {
+               arm_spe__synth_data_source_common(record, data_src);
+               return;
+       }
+
+       switch (record->source) {
+       case ARM_SPE_HISI_HIP_PEER_CPU:
+               data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2;
+               data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
+               break;
+       case ARM_SPE_HISI_HIP_PEER_CPU_HITM:
+               data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2;
+               data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
+               data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
+               break;
+       case ARM_SPE_HISI_HIP_L3:
+               data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
+               data_src->mem_snoop = PERF_MEM_SNOOP_HIT;
+               break;
+       case ARM_SPE_HISI_HIP_L3_HITM:
+               data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
+               data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
+               break;
+       case ARM_SPE_HISI_HIP_PEER_CLUSTER:
+               data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
+               data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
+               break;
+       case ARM_SPE_HISI_HIP_PEER_CLUSTER_HITM:
+               data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
+               data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
+               data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
+               break;
+       case ARM_SPE_HISI_HIP_REMOTE_SOCKET:
+               data_src->mem_lvl = PERF_MEM_LVL_REM_CCE2;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE;
+               data_src->mem_remote = PERF_MEM_REMOTE_REMOTE;
+               data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
+               break;
+       case ARM_SPE_HISI_HIP_REMOTE_SOCKET_HITM:
+               data_src->mem_lvl = PERF_MEM_LVL_REM_CCE2;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE;
+               data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
+               data_src->mem_remote = PERF_MEM_REMOTE_REMOTE;
+               data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
+               break;
+       case ARM_SPE_HISI_HIP_LOCAL_MEM:
+               data_src->mem_lvl = PERF_MEM_LVL_LOC_RAM | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_RAM;
+               data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
+               break;
+       case ARM_SPE_HISI_HIP_REMOTE_MEM:
+               data_src->mem_lvl = PERF_MEM_LVL_REM_RAM1 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_RAM;
+               data_src->mem_remote = PERF_MEM_REMOTE_REMOTE;
+               break;
+       case ARM_SPE_HISI_HIP_NC_DEV:
+               data_src->mem_lvl = PERF_MEM_LVL_IO | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_IO;
+               data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
+               break;
+       case ARM_SPE_HISI_HIP_L2:
+               data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2;
+               data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
+               break;
+       case ARM_SPE_HISI_HIP_L2_HITM:
+               data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2;
+               data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
+               break;
+       case ARM_SPE_HISI_HIP_L1:
+               data_src->mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L1;
+               data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
+               break;
+       default:
+               break;
+       }
+}
+
 static const struct data_source_handle data_source_handles[] = {
        DS(common_ds_encoding_cpus, data_source_common),
        DS(ampereone_ds_encoding_cpus, data_source_ampereone),
+       DS(hisi_hip_ds_encoding_cpus, data_source_hisi_hip),
 };
 
 static void arm_spe__synth_memory_level(const struct arm_spe_record *record,