clk: ti: clkctrl: Fix clkdm_clk handling

[ Upstream commit 1cc54078d104f5b4d7e9f8d55362efa5a8daffdb ]

We need to always call clkdm_clk_enable() and clkdm_clk_disable() even
the clkctrl clock(s) enabled for the domain do not have any gate register
bits. Otherwise clockdomains may never get enabled except when devices get
probed with the legacy "ti,hwmods" devicetree property.

Fixes: 88a172526c32 ("clk: ti: add support for clkctrl clocks")
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 639f515e08f0917e5f0c790f44ed7342336c9238..3325ee43bcc1a402539b1932079928636a4cbc74 100644 (file)
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -137,9 +137,6 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
        int ret;
        union omap4_timeout timeout = { 0 };
 
-       if (!clk->enable_bit)
-               return 0;
-
        if (clk->clkdm) {
                ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
                if (ret) {
@@ -151,6 +148,9 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
                }
        }
 
+       if (!clk->enable_bit)
+               return 0;
+
        val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
 
        val &= ~OMAP4_MODULEMODE_MASK;
@@ -179,7 +179,7 @@ static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
        union omap4_timeout timeout = { 0 };
 
        if (!clk->enable_bit)
-               return;
+               goto exit;
 
        val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);